1 // SPDX-License-Identifier: GPL-2.0+
3 * Atheros AR71xx / AR9xxx GMAC driver
5 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
10 #include <clock_legacy.h>
18 #include <asm/cache.h>
19 #include <linux/bitops.h>
20 #include <linux/compiler.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 #include <linux/mii.h>
27 #include <mach/ath79.h>
29 DECLARE_GLOBAL_DATA_PTR;
38 /* MAC Configuration 1 */
39 #define AG7XXX_ETH_CFG1 0x00
40 #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
41 #define AG7XXX_ETH_CFG1_RX_RST BIT(19)
42 #define AG7XXX_ETH_CFG1_TX_RST BIT(18)
43 #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
44 #define AG7XXX_ETH_CFG1_RX_EN BIT(2)
45 #define AG7XXX_ETH_CFG1_TX_EN BIT(0)
47 /* MAC Configuration 2 */
48 #define AG7XXX_ETH_CFG2 0x04
49 #define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
50 #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
51 #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
52 #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
53 #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
54 #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
55 #define AG7XXX_ETH_CFG2_FDX BIT(0)
57 /* MII Configuration */
58 #define AG7XXX_ETH_MII_MGMT_CFG 0x20
59 #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
62 #define AG7XXX_ETH_MII_MGMT_CMD 0x24
63 #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
66 #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
67 #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
70 #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
73 #define AG7XXX_ETH_MII_MGMT_STATUS 0x30
76 #define AG7XXX_ETH_MII_MGMT_IND 0x34
77 #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
78 #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
80 /* STA Address 1 & 2 */
81 #define AG7XXX_ETH_ADDR1 0x40
82 #define AG7XXX_ETH_ADDR2 0x44
84 /* ETH Configuration 0 - 5 */
85 #define AG7XXX_ETH_FIFO_CFG_0 0x48
86 #define AG7XXX_ETH_FIFO_CFG_1 0x4c
87 #define AG7XXX_ETH_FIFO_CFG_2 0x50
88 #define AG7XXX_ETH_FIFO_CFG_3 0x54
89 #define AG7XXX_ETH_FIFO_CFG_4 0x58
90 #define AG7XXX_ETH_FIFO_CFG_5 0x5c
92 /* DMA Transfer Control for Queue 0 */
93 #define AG7XXX_ETH_DMA_TX_CTRL 0x180
94 #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
96 /* Descriptor Address for Queue 0 Tx */
97 #define AG7XXX_ETH_DMA_TX_DESC 0x184
100 #define AG7XXX_ETH_DMA_TX_STATUS 0x188
103 #define AG7XXX_ETH_DMA_RX_CTRL 0x18c
104 #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
106 /* Pointer to Rx Descriptor */
107 #define AG7XXX_ETH_DMA_RX_DESC 0x190
110 #define AG7XXX_ETH_DMA_RX_STATUS 0x194
112 /* Custom register at 0x1805002C */
113 #define AG7XXX_ETH_XMII 0x2C
114 #define AG7XXX_ETH_XMII_TX_INVERT BIT(31)
115 #define AG7XXX_ETH_XMII_RX_DELAY_LSB 28
116 #define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000
117 #define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \
118 (((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK)
119 #define AG7XXX_ETH_XMII_TX_DELAY_LSB 26
120 #define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000
121 #define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \
122 (((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK)
123 #define AG7XXX_ETH_XMII_GIGE BIT(25)
125 /* Custom register at 0x18070000 */
126 #define AG7XXX_GMAC_ETH_CFG 0x00
127 #define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16
128 #define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000
129 #define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \
130 (((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK)
131 #define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14
132 #define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000
133 #define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \
134 (((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK)
135 #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
136 #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
137 #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
138 #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
139 #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
140 #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
141 #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
142 #define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
143 #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
145 #define CONFIG_TX_DESCR_NUM 8
146 #define CONFIG_RX_DESCR_NUM 8
147 #define CONFIG_ETH_BUFSIZE 2048
148 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
149 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
151 /* DMA descriptor. */
152 struct ag7xxx_dma_desc {
154 #define AG7XXX_DMADESC_IS_EMPTY BIT(31)
155 #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
156 #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
157 #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
163 struct ar7xxx_eth_priv {
164 struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
165 struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
166 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
167 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
170 void __iomem *phyregs;
172 struct eth_device *dev;
173 struct phy_device *phydev;
179 enum ag7xxx_model model;
183 * Switch and MDIO access
185 static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
187 struct ar7xxx_eth_priv *priv = bus->priv;
188 void __iomem *regs = priv->phyregs;
191 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
192 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
193 regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
194 writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
195 regs + AG7XXX_ETH_MII_MGMT_CMD);
197 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
198 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
202 *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
203 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
208 static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
210 struct ar7xxx_eth_priv *priv = bus->priv;
211 void __iomem *regs = priv->phyregs;
214 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
215 regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
216 writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
218 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
219 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
224 static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
226 struct ar7xxx_eth_priv *priv = bus->priv;
231 u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
235 if (priv->model == AG7XXX_MODEL_AG933X ||
236 priv->model == AG7XXX_MODEL_AG953X) {
239 } else if (priv->model == AG7XXX_MODEL_AG934X ||
240 priv->model == AG7XXX_MODEL_AG956X) {
246 if (priv->model == AG7XXX_MODEL_AG956X)
247 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
249 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
253 phy_temp = ((reg >> 6) & 0x7) | 0x10;
254 if (priv->model == AG7XXX_MODEL_AG956X)
255 reg_temp = reg_temp_w & 0x1f;
257 reg_temp = (reg >> 1) & 0x1e;
260 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
265 if (priv->model == AG7XXX_MODEL_AG956X) {
266 phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
267 reg_temp = (reg_temp_w + 1) & 0x1f;
268 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, &rv);
270 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
279 static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
281 struct ar7xxx_eth_priv *priv = bus->priv;
286 u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
289 if (priv->model == AG7XXX_MODEL_AG933X ||
290 priv->model == AG7XXX_MODEL_AG953X) {
293 } else if (priv->model == AG7XXX_MODEL_AG934X ||
294 priv->model == AG7XXX_MODEL_AG956X) {
300 if (priv->model == AG7XXX_MODEL_AG956X)
301 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
303 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
307 if (priv->model == AG7XXX_MODEL_AG956X) {
308 reg_temp = (reg_temp_w + 1) & 0x1f;
309 phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
311 phy_temp = ((reg >> 6) & 0x7) | 0x10;
312 reg_temp = (reg >> 1) & 0x1e;
316 * The switch on AR933x has some special register behavior, which
317 * expects particular write order of their nibbles:
318 * 0x40 ..... MSB first, LSB second
319 * 0x50 ..... MSB first, LSB second
320 * 0x98 ..... LSB first, MSB second
321 * others ... don't care
323 if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
324 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
328 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
332 if (priv->model == AG7XXX_MODEL_AG956X)
333 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val >> 16);
335 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
339 if (priv->model == AG7XXX_MODEL_AG956X) {
340 phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10;
341 reg_temp = reg_temp_w & 0x1f;
344 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
352 static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
357 /* No idea if this is long enough or too long */
358 int timeout_ms = 1000;
360 /* Dummy read followed by PHY read/write command. */
361 ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
364 data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
365 ret = ag7xxx_switch_reg_write(bus, 0x98, data);
369 start = get_timer(0);
371 /* Wait for operation to finish */
373 ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
377 if (get_timer(start) > timeout_ms)
379 } while (data & BIT(31));
381 return data & 0xffff;
384 static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
386 return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
389 static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
394 ret = ag7xxx_mdio_rw(bus, addr, reg, val);
403 static void ag7xxx_dma_clean_tx(struct udevice *dev)
405 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
406 struct ag7xxx_dma_desc *curr, *next;
410 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
411 curr = &priv->tx_mac_descrtable[i];
412 next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
414 curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
415 curr->config = AG7XXX_DMADESC_IS_EMPTY;
416 curr->next_desc = virt_to_phys(next);
419 priv->tx_currdescnum = 0;
421 /* Cache: Flush descriptors, don't care about buffers. */
422 start = (u32)(&priv->tx_mac_descrtable[0]);
423 end = start + sizeof(priv->tx_mac_descrtable);
424 flush_dcache_range(start, end);
427 static void ag7xxx_dma_clean_rx(struct udevice *dev)
429 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
430 struct ag7xxx_dma_desc *curr, *next;
434 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
435 curr = &priv->rx_mac_descrtable[i];
436 next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
438 curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
439 curr->config = AG7XXX_DMADESC_IS_EMPTY;
440 curr->next_desc = virt_to_phys(next);
443 priv->rx_currdescnum = 0;
445 /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
446 start = (u32)(&priv->rx_mac_descrtable[0]);
447 end = start + sizeof(priv->rx_mac_descrtable);
448 flush_dcache_range(start, end);
449 invalidate_dcache_range(start, end);
451 start = (u32)&priv->rxbuffs;
452 end = start + sizeof(priv->rxbuffs);
453 invalidate_dcache_range(start, end);
459 static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
461 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
462 struct ag7xxx_dma_desc *curr;
465 curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
467 /* Cache: Invalidate descriptor. */
469 end = start + sizeof(*curr);
470 invalidate_dcache_range(start, end);
472 if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
473 printf("ag7xxx: Out of TX DMA descriptors!\n");
477 /* Copy the packet into the data buffer. */
478 memcpy(phys_to_virt(curr->data_addr), packet, length);
479 curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
481 /* Cache: Flush descriptor, Flush buffer. */
483 end = start + sizeof(*curr);
484 flush_dcache_range(start, end);
485 start = (u32)phys_to_virt(curr->data_addr);
486 end = start + length;
487 flush_dcache_range(start, end);
489 /* Load the DMA descriptor and start TX DMA. */
490 writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
491 priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
493 /* Switch to next TX descriptor. */
494 priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
499 static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
501 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
502 struct ag7xxx_dma_desc *curr;
503 u32 start, end, length;
505 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
507 /* Cache: Invalidate descriptor. */
509 end = start + sizeof(*curr);
510 invalidate_dcache_range(start, end);
512 /* No packets received. */
513 if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
516 length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
518 /* Cache: Invalidate buffer. */
519 start = (u32)phys_to_virt(curr->data_addr);
520 end = start + length;
521 invalidate_dcache_range(start, end);
523 /* Receive one packet and return length. */
524 *packetp = phys_to_virt(curr->data_addr);
528 static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
531 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
532 struct ag7xxx_dma_desc *curr;
535 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
537 curr->config = AG7XXX_DMADESC_IS_EMPTY;
539 /* Cache: Flush descriptor. */
541 end = start + sizeof(*curr);
542 flush_dcache_range(start, end);
544 /* Switch to next RX descriptor. */
545 priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
550 static int ag7xxx_eth_start(struct udevice *dev)
552 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
554 /* FIXME: Check if link up */
556 /* Clear the DMA rings. */
557 ag7xxx_dma_clean_tx(dev);
558 ag7xxx_dma_clean_rx(dev);
560 /* Load DMA descriptors and start the RX DMA. */
561 writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
562 priv->regs + AG7XXX_ETH_DMA_TX_DESC);
563 writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
564 priv->regs + AG7XXX_ETH_DMA_RX_DESC);
565 writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
566 priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
571 static void ag7xxx_eth_stop(struct udevice *dev)
573 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
575 /* Stop the TX DMA. */
576 writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
577 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
580 /* Stop the RX DMA. */
581 writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
582 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
589 static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
591 struct eth_pdata *pdata = dev_get_platdata(dev);
592 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
593 unsigned char *mac = pdata->enetaddr;
594 u32 macid_lo, macid_hi;
596 macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
597 macid_lo = (mac[5] << 16) | (mac[4] << 24);
599 writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
600 writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
605 static void ag7xxx_hw_setup(struct udevice *dev)
607 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
610 setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
611 AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
612 AG7XXX_ETH_CFG1_SOFT_RST);
616 writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
617 priv->regs + AG7XXX_ETH_CFG1);
619 if (priv->interface == PHY_INTERFACE_MODE_RMII)
620 speed = AG7XXX_ETH_CFG2_IF_10_100;
622 speed = AG7XXX_ETH_CFG2_IF_1000;
624 clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
625 AG7XXX_ETH_CFG2_IF_SPEED_MASK,
626 speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
627 AG7XXX_ETH_CFG2_LEN_CHECK);
629 writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
630 writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
632 writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
633 setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
634 writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
635 writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
636 writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
637 writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
640 static int ag7xxx_mii_get_div(void)
642 ulong freq = get_bus_freq(0);
644 switch (freq / 1000000) {
645 case 150: return 0x7;
646 case 175: return 0x5;
647 case 200: return 0x4;
648 case 210: return 0x9;
649 case 220: return 0x9;
654 static int ag7xxx_mii_setup(struct udevice *dev)
656 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
657 int i, ret, div = ag7xxx_mii_get_div();
660 if (priv->model == AG7XXX_MODEL_AG933X) {
661 /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
662 if (priv->interface == PHY_INTERFACE_MODE_RMII)
666 if (priv->model == AG7XXX_MODEL_AG934X)
668 else if (priv->model == AG7XXX_MODEL_AG953X)
670 else if (priv->model == AG7XXX_MODEL_AG956X)
673 if (priv->model == AG7XXX_MODEL_AG934X ||
674 priv->model == AG7XXX_MODEL_AG953X ||
675 priv->model == AG7XXX_MODEL_AG956X) {
676 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg,
677 priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
678 writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
682 for (i = 0; i < 10; i++) {
683 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
684 priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
685 writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
687 /* Check the switch */
688 ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®);
692 if (reg != 0x18007fff)
701 static int ag933x_phy_setup_wan(struct udevice *dev)
703 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
705 /* Configure switch port 4 (GMAC0) */
706 return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
709 static int ag933x_phy_setup_lan(struct udevice *dev)
711 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
715 /* Reset the switch */
716 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
720 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
725 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
728 } while (reg & BIT(31));
730 /* Configure switch ports 0...3 (GMAC1) */
731 for (i = 0; i < 4; i++) {
732 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
737 /* Enable CPU port */
738 ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
742 for (i = 0; i < 4; i++) {
743 ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
749 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
753 /* Disable Atheros header */
754 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
758 /* Tag priority mapping */
759 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
763 /* Enable ARP packets to the CPU */
764 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®);
768 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
775 static int ag953x_phy_setup_wan(struct udevice *dev)
779 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
781 /* Set wan port connect to GE0 */
782 ret = ag7xxx_switch_reg_read(priv->bus, 0x8, ®);
786 ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28));
790 /* Configure switch port 4 (GMAC0) */
791 ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000);
798 static int ag953x_phy_setup_lan(struct udevice *dev)
800 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
804 /* Reset the switch */
805 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
809 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31));
814 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
817 } while (reg & BIT(31));
819 ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e);
824 ret = ag7xxx_switch_reg_read(priv->bus, 0x4, ®);
828 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6));
832 /* Configure switch ports 0...4 (GMAC1) */
833 for (i = 0; i < 5; i++) {
834 ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000);
839 for (i = 0; i < 5; i++) {
840 ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9));
846 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
850 /* Disable Atheros header */
851 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
855 /* Tag priority mapping */
856 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
860 /* Enable ARP packets to the CPU */
861 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®);
865 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000);
869 /* Enable broadcast packets to the CPU */
870 ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, ®);
874 ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26));
881 static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
883 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
886 if (priv->model == AG7XXX_MODEL_AG953X ||
887 priv->model == AG7XXX_MODEL_AG956X) {
888 ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE,
891 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
892 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
893 ADVERTISE_PAUSE_ASYM);
898 if (priv->model == AG7XXX_MODEL_AG934X) {
899 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
903 } else if (priv->model == AG7XXX_MODEL_AG956X) {
904 ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000,
910 if (priv->model == AG7XXX_MODEL_AG953X ||
911 priv->model == AG7XXX_MODEL_AG956X)
912 return ag7xxx_switch_write(priv->bus, port, MII_BMCR,
913 BMCR_ANENABLE | BMCR_RESET);
915 return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
916 BMCR_ANENABLE | BMCR_RESET);
919 static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
921 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
925 if (priv->model == AG7XXX_MODEL_AG953X ||
926 priv->model == AG7XXX_MODEL_AG956X) {
928 ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, ®);
932 } while (reg & BMCR_RESET);
935 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
939 } while (ret & BMCR_RESET);
945 static int ag933x_phy_setup_common(struct udevice *dev)
947 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
951 if (priv->model == AG7XXX_MODEL_AG933X)
953 else if (priv->model == AG7XXX_MODEL_AG934X ||
954 priv->model == AG7XXX_MODEL_AG953X ||
955 priv->model == AG7XXX_MODEL_AG956X)
960 if (priv->interface == PHY_INTERFACE_MODE_RMII) {
961 ret = ag933x_phy_setup_reset_set(dev, phymax);
965 ret = ag933x_phy_setup_reset_fin(dev, phymax);
969 /* Read out link status */
970 if (priv->model == AG7XXX_MODEL_AG953X)
971 ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, ®);
973 ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
981 for (i = 0; i < phymax; i++) {
982 ret = ag933x_phy_setup_reset_set(dev, i);
987 for (i = 0; i < phymax; i++) {
988 ret = ag933x_phy_setup_reset_fin(dev, i);
993 for (i = 0; i < phymax; i++) {
994 /* Read out link status */
995 if (priv->model == AG7XXX_MODEL_AG953X ||
996 priv->model == AG7XXX_MODEL_AG956X)
997 ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, ®);
999 ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
1007 static int ag934x_phy_setup(struct udevice *dev)
1009 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1013 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
1016 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
1019 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
1022 ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
1025 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
1029 /* AR8327/AR8328 v1.0 fixup */
1030 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
1033 if ((reg & 0xffff) == 0x1201) {
1034 for (i = 0; i < 5; i++) {
1035 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
1038 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
1041 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
1044 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
1050 ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®);
1054 ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
1061 static int ag956x_phy_setup(struct udevice *dev)
1063 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1067 ret = ag7xxx_switch_reg_read(priv->bus, 0x0, ®);
1070 if ((reg & 0xffff) >= 0x1301)
1075 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, BIT(7));
1079 ret = ag7xxx_switch_reg_write(priv->bus, 0xe0, ctrl);
1083 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
1088 * Values suggested by the switch team when s17 in sgmii
1089 * configuration. 0x10(S17_PWS_REG) = 0x602613a0
1091 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x602613a0);
1095 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
1099 /* AR8337/AR8334 v1.0 fixup */
1100 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
1103 if ((reg & 0xffff) == 0x1301) {
1104 for (i = 0; i < 5; i++) {
1105 /* Turn on Gigabit clock */
1106 ret = ag7xxx_switch_write(priv->bus, i, 0x1d, 0x3d);
1109 ret = ag7xxx_switch_write(priv->bus, i, 0x1e, 0x6820);
1118 static int ag7xxx_mac_probe(struct udevice *dev)
1120 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1123 ag7xxx_hw_setup(dev);
1124 ret = ag7xxx_mii_setup(dev);
1128 ag7xxx_eth_write_hwaddr(dev);
1130 if (priv->model == AG7XXX_MODEL_AG933X) {
1131 if (priv->interface == PHY_INTERFACE_MODE_RMII)
1132 ret = ag933x_phy_setup_wan(dev);
1134 ret = ag933x_phy_setup_lan(dev);
1135 } else if (priv->model == AG7XXX_MODEL_AG953X) {
1136 if (priv->interface == PHY_INTERFACE_MODE_RMII)
1137 ret = ag953x_phy_setup_wan(dev);
1139 ret = ag953x_phy_setup_lan(dev);
1140 } else if (priv->model == AG7XXX_MODEL_AG934X) {
1141 ret = ag934x_phy_setup(dev);
1142 } else if (priv->model == AG7XXX_MODEL_AG956X) {
1143 ret = ag956x_phy_setup(dev);
1151 return ag933x_phy_setup_common(dev);
1154 static int ag7xxx_mdio_probe(struct udevice *dev)
1156 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1157 struct mii_dev *bus = mdio_alloc();
1162 bus->read = ag7xxx_mdio_read;
1163 bus->write = ag7xxx_mdio_write;
1164 snprintf(bus->name, sizeof(bus->name), dev->name);
1166 bus->priv = (void *)priv;
1168 return mdio_register(bus);
1171 static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
1175 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
1177 debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
1181 offset = fdt_parent_offset(gd->fdt_blob, offset);
1183 debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
1188 offset = fdt_parent_offset(gd->fdt_blob, offset);
1190 debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
1198 static int ag7xxx_eth_probe(struct udevice *dev)
1200 struct eth_pdata *pdata = dev_get_platdata(dev);
1201 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1202 void __iomem *iobase, *phyiobase;
1205 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
1206 ret = ag7xxx_get_phy_iface_offset(dev);
1209 phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
1211 iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
1212 phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
1214 debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
1215 __func__, iobase, phyiobase, priv);
1216 priv->regs = iobase;
1217 priv->phyregs = phyiobase;
1218 priv->interface = pdata->phy_interface;
1219 priv->model = dev_get_driver_data(dev);
1221 ret = ag7xxx_mdio_probe(dev);
1225 priv->bus = miiphy_get_dev_by_name(dev->name);
1227 ret = ag7xxx_mac_probe(dev);
1228 debug("%s, ret=%d\n", __func__, ret);
1233 static int ag7xxx_eth_remove(struct udevice *dev)
1235 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1238 mdio_unregister(priv->bus);
1239 mdio_free(priv->bus);
1244 static const struct eth_ops ag7xxx_eth_ops = {
1245 .start = ag7xxx_eth_start,
1246 .send = ag7xxx_eth_send,
1247 .recv = ag7xxx_eth_recv,
1248 .free_pkt = ag7xxx_eth_free_pkt,
1249 .stop = ag7xxx_eth_stop,
1250 .write_hwaddr = ag7xxx_eth_write_hwaddr,
1253 static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
1255 struct eth_pdata *pdata = dev_get_platdata(dev);
1256 const char *phy_mode;
1259 pdata->iobase = dev_read_addr(dev);
1260 pdata->phy_interface = -1;
1262 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
1263 ret = ag7xxx_get_phy_iface_offset(dev);
1267 phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
1269 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1270 if (pdata->phy_interface == -1) {
1271 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1278 static const struct udevice_id ag7xxx_eth_ids[] = {
1279 { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
1280 { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
1281 { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X },
1282 { .compatible = "qca,ag956x-mac", .data = AG7XXX_MODEL_AG956X },
1286 U_BOOT_DRIVER(eth_ag7xxx) = {
1287 .name = "eth_ag7xxx",
1289 .of_match = ag7xxx_eth_ids,
1290 .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
1291 .probe = ag7xxx_eth_probe,
1292 .remove = ag7xxx_eth_remove,
1293 .ops = &ag7xxx_eth_ops,
1294 .priv_auto = sizeof(struct ar7xxx_eth_priv),
1295 .plat_auto = sizeof(struct eth_pdata),
1296 .flags = DM_FLAG_ALLOC_PRIV_DMA,