1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
85 #include <asm/cache.h>
89 #include <ppc4xx_enet.h>
94 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
95 #error "CONFIG_MII has to be defined!"
98 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
99 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
102 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
103 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
105 /* Ethernet Transmit and Receive Buffers */
107 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
108 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
110 #define ENET_MAX_MTU PKTSIZE
111 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
113 /*-----------------------------------------------------------------------------+
114 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
115 * Interrupt Controller).
116 *-----------------------------------------------------------------------------*/
117 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
119 #if defined(CONFIG_HAS_ETH3)
120 #if !defined(CONFIG_440GX)
121 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
122 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
124 /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
125 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
126 #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
127 #endif /* !defined(CONFIG_440GX) */
128 #elif defined(CONFIG_HAS_ETH2)
129 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
130 UIC_MASK(ETH_IRQ_NUM(2)))
131 #elif defined(CONFIG_HAS_ETH1)
132 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
134 #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
138 * Define a default version for UIC_ETHxB for non 440GX so that we can
139 * use common code for all 4xx variants
141 #if !defined(UIC_ETHxB)
145 #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
146 #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
147 #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
148 #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
149 #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
151 #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
152 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
155 * We have 3 different interrupt types:
156 * - MAL interrupts indicating successful transfer
157 * - MAL error interrupts indicating MAL related errors
158 * - EMAC interrupts indicating EMAC related errors
160 * All those interrupts can be on different UIC's, but since
161 * now at least all interrupts from one type are on the same
162 * UIC. Only exception is 440GX where the EMAC interrupts are
163 * spread over two UIC's!
165 #if defined(CONFIG_440GX)
166 #define UIC_BASE_MAL UIC1_DCR_BASE
167 #define UIC_BASE_MAL_ERR UIC2_DCR_BASE
168 #define UIC_BASE_EMAC UIC2_DCR_BASE
169 #define UIC_BASE_EMAC_B UIC3_DCR_BASE
171 #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
172 #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
173 #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
174 #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
179 #define BI_PHYMODE_NONE 0
180 #define BI_PHYMODE_ZMII 1
181 #define BI_PHYMODE_RGMII 2
182 #define BI_PHYMODE_GMII 3
183 #define BI_PHYMODE_RTBI 4
184 #define BI_PHYMODE_TBI 5
185 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
186 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
187 defined(CONFIG_405EX)
188 #define BI_PHYMODE_SMII 6
189 #define BI_PHYMODE_MII 7
190 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
191 #define BI_PHYMODE_RMII 8
194 #define BI_PHYMODE_SGMII 9
196 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
197 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
198 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
199 defined(CONFIG_405EX)
200 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
203 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
204 #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
207 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
208 #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
210 #define MAL_RX_CHAN_MUL 1
213 /*--------------------------------------------------------------------+
214 * Fixed PHY (PHY-less) support for Ethernet Ports.
215 *--------------------------------------------------------------------*/
218 * Some boards do not have a PHY for each ethernet port. These ports
219 * are known as Fixed PHY (or PHY-less) ports. For such ports, set
220 * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
221 * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
222 * duplex should be for these ports in the board configuration
226 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
228 * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
229 * #define CONFIG_PHY1_ADDR 1
230 * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
231 * #define CONFIG_PHY3_ADDR 3
233 * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
234 * {devnum, speed, duplex},
236 * #define CONFIG_SYS_FIXED_PHY_PORTS \
237 * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
238 * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
241 #ifndef CONFIG_FIXED_PHY
242 #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
245 #ifndef CONFIG_SYS_FIXED_PHY_PORTS
246 #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
249 struct fixed_phy_port {
250 unsigned int devnum; /* ethernet port */
251 unsigned int speed; /* specified speed 10,100 or 1000 */
252 unsigned int duplex; /* specified duplex FULL or HALF */
255 static const struct fixed_phy_port fixed_phy_port[] = {
256 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
259 /*-----------------------------------------------------------------------------+
260 * Global variables. TX and RX descriptors and buffers.
261 *-----------------------------------------------------------------------------*/
262 #if !defined(CONFIG_NET_MULTI)
263 struct eth_device *emac0_dev = NULL;
267 * Get count of EMAC devices (doesn't have to be the max. possible number
268 * supported by the cpu)
270 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
271 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
272 * 405EX/405EXr eval board, using the same binary.
274 #if defined(CONFIG_BOARD_EMAC_COUNT)
275 #define LAST_EMAC_NUM board_emac_count()
276 #else /* CONFIG_BOARD_EMAC_COUNT */
277 #if defined(CONFIG_HAS_ETH3)
278 #define LAST_EMAC_NUM 4
279 #elif defined(CONFIG_HAS_ETH2)
280 #define LAST_EMAC_NUM 3
281 #elif defined(CONFIG_HAS_ETH1)
282 #define LAST_EMAC_NUM 2
284 #define LAST_EMAC_NUM 1
286 #endif /* CONFIG_BOARD_EMAC_COUNT */
288 /* normal boards start with EMAC0 */
289 #if !defined(CONFIG_EMAC_NR_START)
290 #define CONFIG_EMAC_NR_START 0
293 #define MAL_RX_DESC_SIZE 2048
294 #define MAL_TX_DESC_SIZE 2048
295 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
297 /*-----------------------------------------------------------------------------+
298 * Prototypes and externals.
299 *-----------------------------------------------------------------------------*/
300 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
302 int enetInt (struct eth_device *dev);
303 static void mal_err (struct eth_device *dev, unsigned long isr,
304 unsigned long uic, unsigned long maldef,
305 unsigned long mal_errr);
306 static void emac_err (struct eth_device *dev, unsigned long isr);
308 extern int phy_setup_aneg (char *devname, unsigned char addr);
309 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
310 unsigned char reg, unsigned short *value);
311 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
312 unsigned char reg, unsigned short value);
314 int board_emac_count(void);
316 static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
318 #if defined(CONFIG_440SPE) || \
319 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
320 defined(CONFIG_405EX)
324 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
326 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
329 mfsdr(SDR0_ETH_CFG, val);
330 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
331 mtsdr(SDR0_ETH_CFG, val);
335 static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
337 #if defined(CONFIG_440SPE) || \
338 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
339 defined(CONFIG_405EX)
343 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
345 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
348 mfsdr(SDR0_ETH_CFG, val);
349 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
350 mtsdr(SDR0_ETH_CFG, val);
354 /*-----------------------------------------------------------------------------+
356 | Disable MAL channel, and EMACn
357 +-----------------------------------------------------------------------------*/
358 static void ppc_4xx_eth_halt (struct eth_device *dev)
360 EMAC_4XX_HW_PST hw_p = dev->priv;
363 out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
365 /* 1st reset MAL channel */
366 /* Note: writing a 0 to a channel has no effect */
367 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
368 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
370 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
372 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
375 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
376 udelay (1000); /* Delay 1 MS so as not to hammer the register */
382 /* provide clocks for EMAC internal loopback */
383 emac_loopback_enable(hw_p);
386 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
388 /* remove clocks for EMAC internal loopback */
389 emac_loopback_disable(hw_p);
391 #ifndef CONFIG_NETCONSOLE
392 hw_p->print_speed = 1; /* print speed message again next time */
395 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
396 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
397 mfsdr(SDR0_ETH_CFG, val);
398 val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
399 mtsdr(SDR0_ETH_CFG, val);
405 #if defined (CONFIG_440GX)
406 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
409 unsigned long zmiifer;
410 unsigned long rmiifer;
412 mfsdr(sdr_pfc1, pfc1);
413 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
420 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
421 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
422 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
423 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
424 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
425 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
426 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
427 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
430 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
431 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
432 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
433 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
434 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
435 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
436 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
437 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
440 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
441 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
442 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
443 bis->bi_phymode[1] = BI_PHYMODE_NONE;
444 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
445 bis->bi_phymode[3] = BI_PHYMODE_NONE;
448 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
449 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
450 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
451 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
452 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
453 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
454 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
455 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
458 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
459 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
460 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
461 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
462 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
463 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
464 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
465 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
468 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
469 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
470 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
471 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
472 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
473 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
477 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
479 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
480 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
481 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
482 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
486 /* Ensure we setup mdio for this devnum and ONLY this devnum */
487 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
489 out_be32((void *)ZMII_FER, zmiifer);
490 out_be32((void *)RGMII_FER, rmiifer);
494 #endif /* CONFIG_440_GX */
496 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
497 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
499 unsigned long zmiifer=0x0;
502 mfsdr(sdr_pfc1, pfc1);
503 pfc1 &= SDR0_PFC1_SELECT_MASK;
506 case SDR0_PFC1_SELECT_CONFIG_2:
508 out_be32((void *)ZMII_FER, 0x00);
509 out_be32((void *)RGMII_FER, 0x00000037);
510 bis->bi_phymode[0] = BI_PHYMODE_GMII;
511 bis->bi_phymode[1] = BI_PHYMODE_NONE;
513 case SDR0_PFC1_SELECT_CONFIG_4:
514 /* 2 x RGMII ports */
515 out_be32((void *)ZMII_FER, 0x00);
516 out_be32((void *)RGMII_FER, 0x00000055);
517 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
518 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
520 case SDR0_PFC1_SELECT_CONFIG_6:
522 out_be32((void *)ZMII_FER,
523 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
524 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
525 out_be32((void *)RGMII_FER, 0x00000000);
526 bis->bi_phymode[0] = BI_PHYMODE_SMII;
527 bis->bi_phymode[1] = BI_PHYMODE_SMII;
529 case SDR0_PFC1_SELECT_CONFIG_1_2:
530 /* only 1 x MII supported */
531 out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
532 out_be32((void *)RGMII_FER, 0x00000000);
533 bis->bi_phymode[0] = BI_PHYMODE_MII;
534 bis->bi_phymode[1] = BI_PHYMODE_NONE;
540 /* Ensure we setup mdio for this devnum and ONLY this devnum */
541 zmiifer = in_be32((void *)ZMII_FER);
542 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
543 out_be32((void *)ZMII_FER, zmiifer);
547 #endif /* CONFIG_440EPX */
549 #if defined(CONFIG_405EX)
550 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
555 * The 405EX(r)'s RGMII bridge can operate in one of several
556 * modes, only one of which (2 x RGMII) allows the
557 * simultaneous use of both EMACs on the 405EX.
560 switch (CONFIG_EMAC_PHY_MODE) {
562 case EMAC_PHY_MODE_NONE:
564 rgmiifer |= RGMII_FER_DIS << 0;
565 rgmiifer |= RGMII_FER_DIS << 4;
566 out_be32((void *)RGMII_FER, rgmiifer);
567 bis->bi_phymode[0] = BI_PHYMODE_NONE;
568 bis->bi_phymode[1] = BI_PHYMODE_NONE;
570 case EMAC_PHY_MODE_NONE_RGMII:
571 /* 1 x RGMII port on channel 0 */
572 rgmiifer |= RGMII_FER_RGMII << 0;
573 rgmiifer |= RGMII_FER_DIS << 4;
574 out_be32((void *)RGMII_FER, rgmiifer);
575 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
576 bis->bi_phymode[1] = BI_PHYMODE_NONE;
578 case EMAC_PHY_MODE_RGMII_NONE:
579 /* 1 x RGMII port on channel 1 */
580 rgmiifer |= RGMII_FER_DIS << 0;
581 rgmiifer |= RGMII_FER_RGMII << 4;
582 out_be32((void *)RGMII_FER, rgmiifer);
583 bis->bi_phymode[0] = BI_PHYMODE_NONE;
584 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
586 case EMAC_PHY_MODE_RGMII_RGMII:
587 /* 2 x RGMII ports */
588 rgmiifer |= RGMII_FER_RGMII << 0;
589 rgmiifer |= RGMII_FER_RGMII << 4;
590 out_be32((void *)RGMII_FER, rgmiifer);
591 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
592 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
594 case EMAC_PHY_MODE_NONE_GMII:
595 /* 1 x GMII port on channel 0 */
596 rgmiifer |= RGMII_FER_GMII << 0;
597 rgmiifer |= RGMII_FER_DIS << 4;
598 out_be32((void *)RGMII_FER, rgmiifer);
599 bis->bi_phymode[0] = BI_PHYMODE_GMII;
600 bis->bi_phymode[1] = BI_PHYMODE_NONE;
602 case EMAC_PHY_MODE_NONE_MII:
603 /* 1 x MII port on channel 0 */
604 rgmiifer |= RGMII_FER_MII << 0;
605 rgmiifer |= RGMII_FER_DIS << 4;
606 out_be32((void *)RGMII_FER, rgmiifer);
607 bis->bi_phymode[0] = BI_PHYMODE_MII;
608 bis->bi_phymode[1] = BI_PHYMODE_NONE;
610 case EMAC_PHY_MODE_GMII_NONE:
611 /* 1 x GMII port on channel 1 */
612 rgmiifer |= RGMII_FER_DIS << 0;
613 rgmiifer |= RGMII_FER_GMII << 4;
614 out_be32((void *)RGMII_FER, rgmiifer);
615 bis->bi_phymode[0] = BI_PHYMODE_NONE;
616 bis->bi_phymode[1] = BI_PHYMODE_GMII;
618 case EMAC_PHY_MODE_MII_NONE:
619 /* 1 x MII port on channel 1 */
620 rgmiifer |= RGMII_FER_DIS << 0;
621 rgmiifer |= RGMII_FER_MII << 4;
622 out_be32((void *)RGMII_FER, rgmiifer);
623 bis->bi_phymode[0] = BI_PHYMODE_NONE;
624 bis->bi_phymode[1] = BI_PHYMODE_MII;
630 /* Ensure we setup mdio for this devnum and ONLY this devnum */
631 rgmiifer = in_be32((void *)RGMII_FER);
632 rgmiifer |= (1 << (19-devnum));
633 out_be32((void *)RGMII_FER, rgmiifer);
637 #endif /* CONFIG_405EX */
639 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
640 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
643 u32 zmiifer; /* ZMII0_FER reg. */
644 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
645 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
652 #if defined(CONFIG_460EX)
654 mfsdr(SDR0_ETH_CFG, eth_cfg);
655 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
656 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
657 mode = 11; /* config SGMII */
660 mfsdr(SDR0_ETH_CFG, eth_cfg);
661 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
662 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
663 ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
664 mode = 12; /* config SGMII */
668 * NOTE: 460GT has 2 RGMII bridge cores:
669 * emac0 ------ RGMII0_BASE
673 * emac2 ------ RGMII1_BASE
677 * 460EX has 1 RGMII bridge core:
678 * and RGMII1_BASE is disabled
679 * emac0 ------ RGMII0_BASE
685 * Right now only 2*RGMII is supported. Please extend when needed.
693 /* GMC0 EMAC4_0, ZMII Bridge */
694 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
695 bis->bi_phymode[0] = BI_PHYMODE_MII;
696 bis->bi_phymode[1] = BI_PHYMODE_NONE;
697 bis->bi_phymode[2] = BI_PHYMODE_NONE;
698 bis->bi_phymode[3] = BI_PHYMODE_NONE;
702 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
703 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
704 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
705 bis->bi_phymode[0] = BI_PHYMODE_MII;
706 bis->bi_phymode[1] = BI_PHYMODE_NONE;
707 bis->bi_phymode[2] = BI_PHYMODE_MII;
708 bis->bi_phymode[3] = BI_PHYMODE_NONE;
712 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
713 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
714 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
715 bis->bi_phymode[0] = BI_PHYMODE_RMII;
716 bis->bi_phymode[1] = BI_PHYMODE_RMII;
717 bis->bi_phymode[2] = BI_PHYMODE_NONE;
718 bis->bi_phymode[3] = BI_PHYMODE_NONE;
722 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
724 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
725 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
726 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
727 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
728 bis->bi_phymode[0] = BI_PHYMODE_RMII;
729 bis->bi_phymode[1] = BI_PHYMODE_RMII;
730 bis->bi_phymode[2] = BI_PHYMODE_RMII;
731 bis->bi_phymode[3] = BI_PHYMODE_RMII;
735 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
736 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
737 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
738 bis->bi_phymode[0] = BI_PHYMODE_SMII;
739 bis->bi_phymode[1] = BI_PHYMODE_SMII;
740 bis->bi_phymode[2] = BI_PHYMODE_NONE;
741 bis->bi_phymode[3] = BI_PHYMODE_NONE;
745 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
747 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
748 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
749 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
750 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
751 bis->bi_phymode[0] = BI_PHYMODE_SMII;
752 bis->bi_phymode[1] = BI_PHYMODE_SMII;
753 bis->bi_phymode[2] = BI_PHYMODE_SMII;
754 bis->bi_phymode[3] = BI_PHYMODE_SMII;
757 /* This is the default mode that we want for board bringup - Maple */
759 /* GMC0 EMAC4_0, RGMII Bridge 0 */
760 rmiifer |= RGMII_FER_MDIO(0);
763 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
764 bis->bi_phymode[0] = BI_PHYMODE_GMII;
765 bis->bi_phymode[1] = BI_PHYMODE_NONE;
766 bis->bi_phymode[2] = BI_PHYMODE_NONE;
767 bis->bi_phymode[3] = BI_PHYMODE_NONE;
769 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
770 bis->bi_phymode[0] = BI_PHYMODE_NONE;
771 bis->bi_phymode[1] = BI_PHYMODE_GMII;
772 bis->bi_phymode[2] = BI_PHYMODE_NONE;
773 bis->bi_phymode[3] = BI_PHYMODE_NONE;
778 /* GMC0 EMAC4_0, RGMII Bridge 0 */
779 /* GMC1 EMAC4_2, RGMII Bridge 1 */
780 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
781 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
782 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
783 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
785 bis->bi_phymode[0] = BI_PHYMODE_GMII;
786 bis->bi_phymode[1] = BI_PHYMODE_NONE;
787 bis->bi_phymode[2] = BI_PHYMODE_GMII;
788 bis->bi_phymode[3] = BI_PHYMODE_NONE;
791 /* 2 RGMII - 460EX */
792 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
793 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
794 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
795 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
797 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
798 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
799 bis->bi_phymode[2] = BI_PHYMODE_NONE;
800 bis->bi_phymode[3] = BI_PHYMODE_NONE;
803 /* 4 RGMII - 460GT */
804 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
805 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
806 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
807 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
808 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
809 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
810 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
811 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
812 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
813 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
816 /* 2 SGMII - 460EX */
817 bis->bi_phymode[0] = BI_PHYMODE_SGMII;
818 bis->bi_phymode[1] = BI_PHYMODE_SGMII;
819 bis->bi_phymode[2] = BI_PHYMODE_NONE;
820 bis->bi_phymode[3] = BI_PHYMODE_NONE;
823 /* 3 SGMII - 460GT */
824 bis->bi_phymode[0] = BI_PHYMODE_SGMII;
825 bis->bi_phymode[1] = BI_PHYMODE_SGMII;
826 bis->bi_phymode[2] = BI_PHYMODE_SGMII;
827 bis->bi_phymode[3] = BI_PHYMODE_NONE;
833 /* Set EMAC for MDIO */
834 mfsdr(SDR0_ETH_CFG, eth_cfg);
835 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
836 mtsdr(SDR0_ETH_CFG, eth_cfg);
838 out_be32((void *)RGMII_FER, rmiifer);
839 #if defined(CONFIG_460GT)
840 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
843 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
844 mfsdr(SDR0_ETH_CFG, eth_cfg);
845 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
846 mtsdr(SDR0_ETH_CFG, eth_cfg);
850 #endif /* CONFIG_460EX || CONFIG_460GT */
852 static inline void *malloc_aligned(u32 size, u32 align)
854 return (void *)(((u32)malloc(size + align) + align - 1) &
858 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
861 unsigned long reg = 0;
864 unsigned long duplex;
865 unsigned long failsafe;
867 unsigned short devnum;
868 unsigned short reg_short;
869 #if defined(CONFIG_440GX) || \
870 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
871 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
872 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
873 defined(CONFIG_405EX)
876 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
877 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
878 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
879 defined(CONFIG_405EX)
885 #ifdef CONFIG_4xx_DCACHE
886 static u32 last_used_ea = 0;
888 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
889 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
890 defined(CONFIG_405EX)
894 EMAC_4XX_HW_PST hw_p = dev->priv;
896 /* before doing anything, figure out if we have a MAC address */
898 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
899 printf("ERROR: ethaddr not set!\n");
903 #if defined(CONFIG_440GX) || \
904 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
905 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
906 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
907 defined(CONFIG_405EX)
908 /* Need to get the OPB frequency so we can access the PHY */
909 get_sys_info (&sysinfo);
913 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
915 devnum = hw_p->devnum;
920 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
921 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
922 * is possible that new packets (without relationship with
923 * current transfer) have got the time to arrived before
924 * netloop calls eth_halt
926 printf ("About preceeding transfer (eth%d):\n"
927 "- Sent packet number %d\n"
928 "- Received packet number %d\n"
929 "- Handled packet number %d\n",
932 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
934 hw_p->stats.pkts_tx = 0;
935 hw_p->stats.pkts_rx = 0;
936 hw_p->stats.pkts_handled = 0;
937 hw_p->print_speed = 1; /* print speed message again next time */
940 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
941 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
943 hw_p->rx_slot = 0; /* MAL Receive Slot */
944 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
945 hw_p->rx_u_index = 0; /* Receive User Queue Index */
947 hw_p->tx_slot = 0; /* MAL Transmit Slot */
948 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
949 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
951 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
953 /* NOTE: 440GX spec states that mode is mutually exclusive */
954 /* NOTE: Therefore, disable all other EMACS, since we handle */
955 /* NOTE: only one emac at a time */
957 out_be32((void *)ZMII_FER, 0);
960 #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
961 out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
962 #elif defined(CONFIG_440GX) || \
963 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
964 defined(CONFIG_460EX) || defined(CONFIG_460GT)
965 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
968 out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
969 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
970 #if defined(CONFIG_405EX)
971 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
976 /* provide clocks for EMAC internal loopback */
977 emac_loopback_enable(hw_p);
980 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
982 /* remove clocks for EMAC internal loopback */
983 emac_loopback_disable(hw_p);
986 while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
991 printf("\nProblem resetting EMAC!\n");
993 #if defined(CONFIG_440GX) || \
994 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
995 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
996 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
997 defined(CONFIG_405EX)
998 /* Whack the M1 register */
1000 mode_reg &= ~0x00000038;
1001 opbfreq = sysinfo.freqOPB / 1000000;
1003 else if (opbfreq <= 66)
1004 mode_reg |= EMAC_M1_OBCI_66;
1005 else if (opbfreq <= 83)
1006 mode_reg |= EMAC_M1_OBCI_83;
1007 else if (opbfreq <= 100)
1008 mode_reg |= EMAC_M1_OBCI_100;
1010 mode_reg |= EMAC_M1_OBCI_GT100;
1012 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
1013 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
1015 #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
1016 defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
1017 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
1019 * In SGMII mode, GPCS access is needed for
1020 * communication with the internal SGMII SerDes.
1023 #if defined(CONFIG_GPCS_PHY_ADDR)
1025 reg = CONFIG_GPCS_PHY_ADDR;
1028 #if defined(CONFIG_GPCS_PHY1_ADDR)
1030 reg = CONFIG_GPCS_PHY1_ADDR;
1033 #if defined(CONFIG_GPCS_PHY2_ADDR)
1035 reg = CONFIG_GPCS_PHY2_ADDR;
1038 #if defined(CONFIG_GPCS_PHY3_ADDR)
1040 reg = CONFIG_GPCS_PHY3_ADDR;
1045 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
1046 mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg);
1047 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
1049 /* Configure GPCS interface to recommended setting for SGMII */
1050 miiphy_reset(dev->name, reg);
1051 miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
1052 miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
1053 miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
1055 #endif /* defined(CONFIG_GPCS_PHY_ADDR) */
1057 /* wait for PHY to complete auto negotiation */
1061 reg = CONFIG_PHY_ADDR;
1063 #if defined (CONFIG_PHY1_ADDR)
1065 reg = CONFIG_PHY1_ADDR;
1068 #if defined (CONFIG_PHY2_ADDR)
1070 reg = CONFIG_PHY2_ADDR;
1073 #if defined (CONFIG_PHY3_ADDR)
1075 reg = CONFIG_PHY3_ADDR;
1079 reg = CONFIG_PHY_ADDR;
1083 bis->bi_phynum[devnum] = reg;
1085 if (reg == CONFIG_FIXED_PHY)
1088 #if defined(CONFIG_PHY_RESET)
1090 * Reset the phy, only if its the first time through
1091 * otherwise, just check the speeds & feeds
1093 if (hw_p->first_init == 0) {
1094 #if defined(CONFIG_M88E1111_PHY)
1095 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
1096 miiphy_write (dev->name, reg, 0x18, 0x4101);
1097 miiphy_write (dev->name, reg, 0x09, 0x0e00);
1098 miiphy_write (dev->name, reg, 0x04, 0x01e1);
1100 #if defined(CONFIG_M88E1112_PHY)
1101 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
1103 * Marvell 88E1112 PHY needs to have the SGMII MAC
1104 * interace (page 2) properly configured to
1105 * communicate with the 460EX/GT GPCS interface.
1108 /* Set access to Page 2 */
1109 miiphy_write(dev->name, reg, 0x16, 0x0002);
1111 miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
1112 miiphy_read(dev->name, reg, 0x1a, ®_short);
1113 reg_short |= 0x8000; /* bypass Auto-Negotiation */
1114 miiphy_write(dev->name, reg, 0x1a, reg_short);
1115 miiphy_reset(dev->name, reg); /* reset MAC interface */
1117 /* Reset access to Page 0 */
1118 miiphy_write(dev->name, reg, 0x16, 0x0000);
1120 #endif /* defined(CONFIG_M88E1112_PHY) */
1121 miiphy_reset (dev->name, reg);
1123 #if defined(CONFIG_440GX) || \
1124 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1125 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1126 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1127 defined(CONFIG_405EX)
1129 #if defined(CONFIG_CIS8201_PHY)
1131 * Cicada 8201 PHY needs to have an extended register whacked
1134 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
1135 #if defined(CONFIG_CIS8201_SHORT_ETCH)
1136 miiphy_write (dev->name, reg, 23, 0x1300);
1138 miiphy_write (dev->name, reg, 23, 0x1000);
1141 * Vitesse VSC8201/Cicada CIS8201 errata:
1142 * Interoperability problem with Intel 82547EI phys
1143 * This work around (provided by Vitesse) changes
1144 * the default timer convergence from 8ms to 12ms
1146 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1147 miiphy_write (dev->name, reg, 0x08, 0x0200);
1148 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
1149 miiphy_write (dev->name, reg, 0x02, 0x0004);
1150 miiphy_write (dev->name, reg, 0x01, 0x0671);
1151 miiphy_write (dev->name, reg, 0x00, 0x8fae);
1152 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1153 miiphy_write (dev->name, reg, 0x08, 0x0000);
1154 miiphy_write (dev->name, reg, 0x1f, 0x0000);
1155 /* end Vitesse/Cicada errata */
1157 #endif /* defined(CONFIG_CIS8201_PHY) */
1159 #if defined(CONFIG_ET1011C_PHY)
1161 * Agere ET1011c PHY needs to have an extended register whacked
1164 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
1165 miiphy_read (dev->name, reg, 0x16, ®_short);
1166 reg_short &= ~(0x7);
1167 reg_short |= 0x6; /* RGMII DLL Delay*/
1168 miiphy_write (dev->name, reg, 0x16, reg_short);
1170 miiphy_read (dev->name, reg, 0x17, ®_short);
1171 reg_short &= ~(0x40);
1172 miiphy_write (dev->name, reg, 0x17, reg_short);
1174 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
1176 #endif /* defined(CONFIG_ET1011C_PHY) */
1178 #endif /* defined(CONFIG_440GX) ... */
1179 /* Start/Restart autonegotiation */
1180 phy_setup_aneg (dev->name, reg);
1183 #endif /* defined(CONFIG_PHY_RESET) */
1185 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
1188 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
1190 if ((reg_short & PHY_BMSR_AUTN_ABLE)
1191 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
1192 puts ("Waiting for PHY auto negotiation to complete");
1194 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
1198 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
1199 puts (" TIMEOUT !\n");
1203 if ((i++ % 1000) == 0) {
1206 udelay (1000); /* 1 ms */
1207 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
1210 udelay (500000); /* another 500 ms (results in faster booting) */
1214 if (reg == CONFIG_FIXED_PHY) {
1215 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
1216 if (devnum == fixed_phy_port[i].devnum) {
1217 speed = fixed_phy_port[i].speed;
1218 duplex = fixed_phy_port[i].duplex;
1223 if (i == ARRAY_SIZE(fixed_phy_port)) {
1224 printf("ERROR: PHY (%s) not configured correctly!\n",
1229 speed = miiphy_speed(dev->name, reg);
1230 duplex = miiphy_duplex(dev->name, reg);
1233 if (hw_p->print_speed) {
1234 hw_p->print_speed = 0;
1235 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
1236 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
1240 #if defined(CONFIG_440) && \
1241 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
1242 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1243 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
1244 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
1245 mfsdr(sdr_mfr, reg);
1247 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
1249 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1251 mtsdr(sdr_mfr, reg);
1254 /* Set ZMII/RGMII speed according to the phy link speed */
1255 reg = in_be32((void *)ZMII_SSR);
1256 if ( (speed == 100) || (speed == 1000) )
1257 out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
1259 out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
1261 if ((devnum == 2) || (devnum == 3)) {
1263 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1264 else if (speed == 100)
1265 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
1266 else if (speed == 10)
1267 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
1269 printf("Error in RGMII Speed\n");
1272 out_be32((void *)RGMII_SSR, reg);
1274 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
1276 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1277 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1278 defined(CONFIG_405EX)
1280 rgmii_channel = devnum - 2;
1282 rgmii_channel = devnum;
1285 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
1286 else if (speed == 100)
1287 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
1288 else if (speed == 10)
1289 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
1291 printf("Error in RGMII Speed\n");
1294 out_be32((void *)RGMII_SSR, reg);
1295 #if defined(CONFIG_460GT)
1296 if ((devnum == 2) || (devnum == 3))
1297 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
1301 /* set the Mal configuration reg */
1302 #if defined(CONFIG_440GX) || \
1303 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1304 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1305 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1306 defined(CONFIG_405EX)
1307 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
1308 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
1310 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
1311 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
1312 if (get_pvr() == PVR_440GP_RB) {
1313 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
1318 * Malloc MAL buffer desciptors, make sure they are
1319 * aligned on cache line boundary size
1320 * (401/403/IOP480 = 16, 405 = 32)
1321 * and doesn't cross cache block boundaries.
1323 if (hw_p->first_init == 0) {
1324 debug("*** Allocating descriptor memory ***\n");
1326 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
1328 printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
1332 #ifdef CONFIG_4xx_DCACHE
1333 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
1335 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
1336 bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
1338 bd_uncached = bis->bi_memsize;
1341 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
1343 last_used_ea = bd_uncached;
1344 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
1345 TLB_WORD2_I_ENABLE);
1347 bd_uncached = bd_cached;
1349 hw_p->tx_phys = bd_cached;
1350 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
1351 hw_p->tx = (mal_desc_t *)(bd_uncached);
1352 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
1353 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
1356 for (i = 0; i < NUM_TX_BUFF; i++) {
1357 hw_p->tx[i].ctrl = 0;
1358 hw_p->tx[i].data_len = 0;
1359 if (hw_p->first_init == 0)
1360 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
1362 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
1363 if ((NUM_TX_BUFF - 1) == i)
1364 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
1365 hw_p->tx_run[i] = -1;
1366 debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
1369 for (i = 0; i < NUM_RX_BUFF; i++) {
1370 hw_p->rx[i].ctrl = 0;
1371 hw_p->rx[i].data_len = 0;
1372 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
1373 if ((NUM_RX_BUFF - 1) == i)
1374 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
1375 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
1376 hw_p->rx_ready[i] = -1;
1377 debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
1382 reg |= dev->enetaddr[0]; /* set high address */
1384 reg |= dev->enetaddr[1];
1386 out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
1389 reg |= dev->enetaddr[2]; /* set low address */
1391 reg |= dev->enetaddr[3];
1393 reg |= dev->enetaddr[4];
1395 reg |= dev->enetaddr[5];
1397 out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
1401 /* setup MAL tx & rx channel pointers */
1402 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
1403 mtdcr (maltxctp2r, hw_p->tx_phys);
1405 mtdcr (maltxctp1r, hw_p->tx_phys);
1407 #if defined(CONFIG_440)
1408 mtdcr (maltxbattr, 0x0);
1409 mtdcr (malrxbattr, 0x0);
1412 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1413 mtdcr (malrxctp8r, hw_p->rx_phys);
1414 /* set RX buffer size */
1415 mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
1417 mtdcr (malrxctp1r, hw_p->rx_phys);
1418 /* set RX buffer size */
1419 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
1422 #if defined (CONFIG_440GX)
1424 /* setup MAL tx & rx channel pointers */
1425 mtdcr (maltxbattr, 0x0);
1426 mtdcr (malrxbattr, 0x0);
1427 mtdcr (maltxctp2r, hw_p->tx_phys);
1428 mtdcr (malrxctp2r, hw_p->rx_phys);
1429 /* set RX buffer size */
1430 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
1433 /* setup MAL tx & rx channel pointers */
1434 mtdcr (maltxbattr, 0x0);
1435 mtdcr (maltxctp3r, hw_p->tx_phys);
1436 mtdcr (malrxbattr, 0x0);
1437 mtdcr (malrxctp3r, hw_p->rx_phys);
1438 /* set RX buffer size */
1439 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
1441 #endif /* CONFIG_440GX */
1442 #if defined (CONFIG_460GT)
1444 /* setup MAL tx & rx channel pointers */
1445 mtdcr (maltxbattr, 0x0);
1446 mtdcr (malrxbattr, 0x0);
1447 mtdcr (maltxctp2r, hw_p->tx_phys);
1448 mtdcr (malrxctp16r, hw_p->rx_phys);
1449 /* set RX buffer size */
1450 mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
1453 /* setup MAL tx & rx channel pointers */
1454 mtdcr (maltxbattr, 0x0);
1455 mtdcr (malrxbattr, 0x0);
1456 mtdcr (maltxctp3r, hw_p->tx_phys);
1457 mtdcr (malrxctp24r, hw_p->rx_phys);
1458 /* set RX buffer size */
1459 mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
1461 #endif /* CONFIG_460GT */
1464 /* setup MAL tx & rx channel pointers */
1465 #if defined(CONFIG_440)
1466 mtdcr (maltxbattr, 0x0);
1467 mtdcr (malrxbattr, 0x0);
1469 mtdcr (maltxctp0r, hw_p->tx_phys);
1470 mtdcr (malrxctp0r, hw_p->rx_phys);
1471 /* set RX buffer size */
1472 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
1476 /* Enable MAL transmit and receive channels */
1477 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
1478 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
1480 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1482 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1484 /* set transmit enable & receive enable */
1485 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
1487 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
1489 /* set rx-/tx-fifo size */
1490 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
1493 if (speed == _1000BASET) {
1494 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1495 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1498 mfsdr (sdr_pfc1, pfc1);
1499 pfc1 |= SDR0_PFC1_EM_1000;
1500 mtsdr (sdr_pfc1, pfc1);
1502 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
1503 } else if (speed == _100BASET)
1504 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
1506 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1508 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
1510 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
1512 /* Enable broadcast and indvidual address */
1513 /* TBS: enabling runts as some misbehaved nics will send runts */
1514 out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
1516 /* we probably need to set the tx mode1 reg? maybe at tx time */
1518 /* set transmit request threshold register */
1519 out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1521 /* set receive low/high water mark register */
1522 #if defined(CONFIG_440)
1523 /* 440s has a 64 byte burst length */
1524 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1526 /* 405s have a 16 byte burst length */
1527 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1528 #endif /* defined(CONFIG_440) */
1529 out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
1531 /* Set fifo limit entry in tx mode 0 */
1532 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
1534 out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1537 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1538 if (speed == _100BASET)
1539 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1541 out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1542 out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
1544 if (hw_p->first_init == 0) {
1546 * Connect interrupt service routines
1548 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1549 (interrupt_handler_t *) enetInt, dev);
1552 mtmsr (msr); /* enable interrupts again */
1555 hw_p->first_init = 1;
1561 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
1564 struct enet_frame *ef_ptr;
1565 ulong time_start, time_now;
1566 unsigned long temp_txm0;
1567 EMAC_4XX_HW_PST hw_p = dev->priv;
1569 ef_ptr = (struct enet_frame *) ptr;
1571 /*-----------------------------------------------------------------------+
1572 * Copy in our address into the frame.
1573 *-----------------------------------------------------------------------*/
1574 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1576 /*-----------------------------------------------------------------------+
1577 * If frame is too long or too short, modify length.
1578 *-----------------------------------------------------------------------*/
1579 /* TBS: where does the fragment go???? */
1580 if (len > ENET_MAX_MTU)
1583 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1584 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1585 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
1587 /*-----------------------------------------------------------------------+
1588 * set TX Buffer busy, and send it
1589 *-----------------------------------------------------------------------*/
1590 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1591 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1592 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1593 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1594 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1596 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1597 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1601 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
1602 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1603 #ifdef INFO_4XX_ENET
1604 hw_p->stats.pkts_tx++;
1607 /*-----------------------------------------------------------------------+
1608 * poll unitl the packet is sent and then make sure it is OK
1609 *-----------------------------------------------------------------------*/
1610 time_start = get_timer (0);
1612 temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
1613 /* loop until either TINT turns on or 3 seconds elapse */
1614 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1615 /* transmit is done, so now check for errors
1616 * If there is an error, an interrupt should
1617 * happen when we return
1619 time_now = get_timer (0);
1620 if ((time_now - time_start) > 3000) {
1629 int enetInt (struct eth_device *dev)
1632 int rc = -1; /* default to not us */
1640 EMAC_4XX_HW_PST hw_p;
1643 * Because the mal is generic, we need to get the current
1646 #if defined(CONFIG_NET_MULTI)
1647 dev = eth_get_dev();
1654 /* enter loop that stays in interrupt code until nothing to service */
1658 uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
1659 uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
1660 uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
1661 uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
1663 if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
1664 && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
1665 && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
1670 /* get and clear controller status interrupts */
1671 /* look at MAL and EMAC error interrupts */
1672 if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
1673 /* we have a MAL error interrupt */
1674 mal_isr = mfdcr(malesr);
1675 mal_err(dev, mal_isr, uic_mal_err,
1676 MAL_UIC_DEF, MAL_UIC_ERR);
1678 /* clear MAL error interrupt status bits */
1679 mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
1680 UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
1685 /* look for EMAC errors */
1686 if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
1687 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1688 emac_err(dev, emac_isr);
1690 /* clear EMAC error interrupt status bits */
1691 mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
1692 mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
1697 /* handle MAX TX EOB interrupt from a tx */
1698 if (uic_mal & UIC_MAL_TXEOB) {
1699 /* clear MAL interrupt status bits */
1700 mal_eob = mfdcr(maltxeobisr);
1701 mtdcr(maltxeobisr, mal_eob);
1702 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
1704 /* indicate that we serviced an interrupt */
1709 /* handle MAL RX EOB interupt from a receive */
1710 /* check for EOB on valid channels */
1711 if (uic_mal & UIC_MAL_RXEOB) {
1712 mal_eob = mfdcr(malrxeobisr);
1714 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
1715 /* push packet to upper layer */
1716 enet_rcv(dev, emac_isr);
1718 /* clear MAL interrupt status bits */
1719 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
1721 /* indicate that we serviced an interrupt */
1731 /*-----------------------------------------------------------------------------+
1733 *-----------------------------------------------------------------------------*/
1734 static void mal_err (struct eth_device *dev, unsigned long isr,
1735 unsigned long uic, unsigned long maldef,
1736 unsigned long mal_errr)
1738 EMAC_4XX_HW_PST hw_p = dev->priv;
1740 mtdcr (malesr, isr); /* clear interrupt */
1742 /* clear DE interrupt */
1743 mtdcr (maltxdeir, 0xC0000000);
1744 mtdcr (malrxdeir, 0x80000000);
1746 #ifdef INFO_4XX_ENET
1747 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1750 eth_init (hw_p->bis); /* start again... */
1753 /*-----------------------------------------------------------------------------+
1754 * EMAC Error Routine
1755 *-----------------------------------------------------------------------------*/
1756 static void emac_err (struct eth_device *dev, unsigned long isr)
1758 EMAC_4XX_HW_PST hw_p = dev->priv;
1760 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1761 out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
1764 /*-----------------------------------------------------------------------------+
1765 * enet_rcv() handles the ethernet receive data
1766 *-----------------------------------------------------------------------------*/
1767 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1769 struct enet_frame *ef_ptr;
1770 unsigned long data_len;
1771 unsigned long rx_eob_isr;
1772 EMAC_4XX_HW_PST hw_p = dev->priv;
1778 rx_eob_isr = mfdcr (malrxeobisr);
1779 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
1781 mtdcr (malrxeobisr, rx_eob_isr);
1784 while (1) { /* do all */
1787 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1788 || (loop_count >= NUM_RX_BUFF))
1793 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
1795 if (data_len > ENET_MAX_MTU) /* Check len */
1798 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1800 hw_p->stats.rx_err_log[hw_p->
1803 hw_p->rx_err_index++;
1804 if (hw_p->rx_err_index ==
1806 hw_p->rx_err_index =
1809 } /* data_len < max mtu */
1811 if (!data_len) { /* no data */
1812 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1814 hw_p->stats.data_len_err++; /* Error at Rx */
1819 /* Check if user has already eaten buffer */
1820 /* if not => ERROR */
1821 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1822 if (hw_p->is_receiving)
1823 printf ("ERROR : Receive buffers are full!\n");
1826 hw_p->stats.rx_frames++;
1827 hw_p->stats.rx += data_len;
1828 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1830 #ifdef INFO_4XX_ENET
1831 hw_p->stats.pkts_rx++;
1836 hw_p->rx_ready[hw_p->rx_i_index] = i;
1838 if (NUM_RX_BUFF == hw_p->rx_i_index)
1839 hw_p->rx_i_index = 0;
1842 if (NUM_RX_BUFF == hw_p->rx_slot)
1846 * free receive buffer only when
1847 * buffer has been handled (eth_rx)
1848 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1852 } /* if EMACK_RXCHL */
1856 static int ppc_4xx_eth_rx (struct eth_device *dev)
1861 EMAC_4XX_HW_PST hw_p = dev->priv;
1863 hw_p->is_receiving = 1; /* tell driver */
1867 * use ring buffer and
1868 * get index from rx buffer desciptor queue
1870 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1871 if (user_index == -1) {
1873 break; /* nothing received - leave for() loop */
1877 mtmsr (msr & ~(MSR_EE));
1879 length = hw_p->rx[user_index].data_len & 0x0fff;
1881 /* Pass the packet up to the protocol layers. */
1882 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1883 /* NetReceive(NetRxPackets[i], length); */
1884 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1885 (u32)hw_p->rx[user_index].data_ptr +
1887 NetReceive (NetRxPackets[user_index], length - 4);
1888 /* Free Recv Buffer */
1889 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1890 /* Free rx buffer descriptor queue */
1891 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1893 if (NUM_RX_BUFF == hw_p->rx_u_index)
1894 hw_p->rx_u_index = 0;
1896 #ifdef INFO_4XX_ENET
1897 hw_p->stats.pkts_handled++;
1900 mtmsr (msr); /* Enable IRQ's */
1903 hw_p->is_receiving = 0; /* tell driver */
1908 int ppc_4xx_eth_initialize (bd_t * bis)
1910 static int virgin = 0;
1911 struct eth_device *dev;
1913 EMAC_4XX_HW_PST hw = NULL;
1914 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1918 #if defined(CONFIG_440GX)
1921 mfsdr (sdr_pfc1, pfc1);
1922 pfc1 &= ~(0x01e00000);
1924 mtsdr (sdr_pfc1, pfc1);
1927 /* first clear all mac-addresses */
1928 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1929 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1931 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1932 int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
1934 default: /* fall through */
1936 eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
1937 hw_addr[eth_num] = 0x0;
1939 #ifdef CONFIG_HAS_ETH1
1941 eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
1942 hw_addr[eth_num] = 0x100;
1945 #ifdef CONFIG_HAS_ETH2
1947 eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
1948 #if defined(CONFIG_460GT)
1949 hw_addr[eth_num] = 0x300;
1951 hw_addr[eth_num] = 0x400;
1955 #ifdef CONFIG_HAS_ETH3
1957 eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
1958 #if defined(CONFIG_460GT)
1959 hw_addr[eth_num] = 0x400;
1961 hw_addr[eth_num] = 0x600;
1968 /* set phy num and mode */
1969 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1970 bis->bi_phymode[0] = 0;
1972 #if defined(CONFIG_PHY1_ADDR)
1973 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1974 bis->bi_phymode[1] = 0;
1976 #if defined(CONFIG_440GX)
1977 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1978 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1979 bis->bi_phymode[2] = 2;
1980 bis->bi_phymode[3] = 2;
1983 #if defined(CONFIG_440GX) || \
1984 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1985 defined(CONFIG_405EX)
1986 ppc_4xx_eth_setup_bridge(0, bis);
1989 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1991 * See if we can actually bring up the interface,
1992 * otherwise, skip it
1994 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1995 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1999 /* Allocate device structure */
2000 dev = (struct eth_device *) malloc (sizeof (*dev));
2002 printf ("ppc_4xx_eth_initialize: "
2003 "Cannot allocate eth_device %d\n", eth_num);
2006 memset(dev, 0, sizeof(*dev));
2008 /* Allocate our private use data */
2009 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
2011 printf ("ppc_4xx_eth_initialize: "
2012 "Cannot allocate private hw data for eth_device %d",
2017 memset(hw, 0, sizeof(*hw));
2019 hw->hw_addr = hw_addr[eth_num];
2020 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
2021 hw->devnum = eth_num;
2022 hw->print_speed = 1;
2024 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
2025 dev->priv = (void *) hw;
2026 dev->init = ppc_4xx_eth_init;
2027 dev->halt = ppc_4xx_eth_halt;
2028 dev->send = ppc_4xx_eth_send;
2029 dev->recv = ppc_4xx_eth_rx;
2032 /* set the MAL IER ??? names may change with new spec ??? */
2033 #if defined(CONFIG_440SPE) || \
2034 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
2035 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2036 defined(CONFIG_405EX)
2038 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
2039 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
2042 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
2043 MAL_IER_OPBE | MAL_IER_PLBE;
2045 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
2046 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
2047 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
2048 mtdcr (malier, mal_ier);
2050 /* install MAL interrupt handler */
2051 irq_install_handler (VECNUM_MAL_SERR,
2052 (interrupt_handler_t *) enetInt,
2054 irq_install_handler (VECNUM_MAL_TXEOB,
2055 (interrupt_handler_t *) enetInt,
2057 irq_install_handler (VECNUM_MAL_RXEOB,
2058 (interrupt_handler_t *) enetInt,
2060 irq_install_handler (VECNUM_MAL_TXDE,
2061 (interrupt_handler_t *) enetInt,
2063 irq_install_handler (VECNUM_MAL_RXDE,
2064 (interrupt_handler_t *) enetInt,
2069 #if defined(CONFIG_NET_MULTI)
2075 #if defined(CONFIG_NET_MULTI)
2076 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
2077 miiphy_register (dev->name,
2078 emac4xx_miiphy_read, emac4xx_miiphy_write);
2081 } /* end for each supported device */
2086 #if !defined(CONFIG_NET_MULTI)
2087 void eth_halt (void) {
2089 ppc_4xx_eth_halt(emac0_dev);
2095 int eth_init (bd_t *bis)
2097 ppc_4xx_eth_initialize(bis);
2099 return ppc_4xx_eth_init(emac0_dev, bis);
2101 printf("ERROR: ethaddr not set!\n");
2106 int eth_send(volatile void *packet, int length)
2108 return (ppc_4xx_eth_send(emac0_dev, packet, length));
2113 return (ppc_4xx_eth_rx(emac0_dev));
2116 int emac4xx_miiphy_initialize (bd_t * bis)
2118 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
2119 miiphy_register ("ppc_4xx_eth0",
2120 emac4xx_miiphy_read, emac4xx_miiphy_write);
2125 #endif /* !defined(CONFIG_NET_MULTI) */