2 #include <linux/mtd/mtd.h>
4 #include <linux/mtd/nand.h>
6 #if defined CONFIG_NAND_DOLPHIN
7 #include <asm/arch/sprd_nfc_reg_v2.h>
8 #elif defined CONFIG_NAND_SC8830
9 #include <asm/arch/sprd_nfc_reg_v2.h>
10 #elif defined CONFIG_NAND_TIGER
11 #include <asm/arch/sprd_nfc_reg_v2.h>
12 #elif defined CONFIG_NAND_SC8810
13 #include <asm/arch/regs_nfc.h>
15 #include "asm/arch/nand_controller.h"
18 #define BOOTLOADER_HEADER_OFFSET 32
19 #define CONFIG_SYS_SPL_ECC_POS 8
20 #if defined CONFIG_SPX30G
21 #define MAX_SPL_SIZE 0x8000
23 #define MAX_SPL_SIZE 0x6000
27 #if defined CONFIG_NAND_SC7710G2
28 struct bootloader_header
30 uint32_t version; //version, fot tiger this member must be 0
31 uint32_t magic_num; //0xaa55a5a5
33 uint32_t hash_len;//word length, only used when secure boot enable
34 uint32_t acycle; // 3, 4, 5
35 uint32_t bus_width; //0 ,1
36 uint32_t spare_size; //spare part sise for one sector
37 uint32_t ecc_mode; //0--1bit, 1--2bit,2--4bit,3--8bit,4--12bit, 5--16bit, 6--24bit
38 uint32_t ecc_pos; // ecc postion at spare part
39 uint32_t sct_per_page; //sector per page
42 uint32_t ecc_value[27];
46 * spare info data is don't used at the romcode, so the fdl only set the s_info size to 1, and the data value 0xff
48 void set_header_info(u8 *bl_data, struct mtd_info *nand, int ecc_pos)
50 struct bootloader_header *header;
51 struct nand_chip *chip = nand->priv;
52 struct sc8810_ecc_param param;
54 header = (struct bootloader_header *)(bl_data + BOOTLOADER_HEADER_OFFSET);
55 memset(header, 0, sizeof(struct bootloader_header));
56 memset(ecc, 0xff, sizeof(ecc));
58 header->version = 0x1;
59 header->sct_size = chip->ecc.size;
60 header->hash_len = 0x400;
61 if (chip->options & NAND_BUSWIDTH_16){
62 header->bus_width = 1;
64 if(nand->writesize > 512) {
65 if (chip->chipsize > (128 << 20)){
73 /* One more address cycle for devices > 32MiB */
74 if (chip->chipsize > (32 << 20)){
84 header->magic_num = 0xaa55a5a5;
85 header->spare_size = (nand->oobsize/chip->ecc.steps);
86 header->ecc_mode = ecc_mode_convert(chip->eccbitmode);
87 header->ecc_pos = ecc_pos;
88 header->sct_size = (nand->writesize/chip->ecc.steps);
90 header->sct_per_page = chip->ecc.steps;
94 param.sp_size = sizeof(ecc);
96 param.m_size = chip->ecc.size;
97 param.p_mbuf = (u8 *)bl_data;
100 sc8810_ecc_encode(¶m);
101 memcpy(header->ecc_value, ecc, sizeof(ecc));
105 static int nand_write_spl_page(u8 *buf, struct mtd_info *mtd, u32 pg, u32 ecc_pos)
109 struct nand_chip *chip = mtd->priv;
110 int eccbytes = chip->ecc.bytes;
114 uint8_t *ecc_calc = chip->buffers->ecccalc;
115 eccsteps = chip->ecc.steps;
116 eccsize = chip->ecc.size;
117 spare_per_sct = mtd->oobsize / eccsteps;
118 memset(chip->buffers->ecccode, 0xff, mtd->oobsize);
120 page = (int)(pg >> chip->page_shift);
122 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
124 for (i = 0; i < eccsteps; i ++, buf += eccsize) {
125 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
126 chip->write_buf(mtd, buf, eccsize);
127 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
128 memcpy(chip->buffers->ecccode + i * spare_per_sct + ecc_pos, &ecc_calc[0], eccbytes);
130 chip->write_buf(mtd, chip->buffers->ecccode, mtd->oobsize);
131 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
132 chip->waitfunc(mtd, chip);
137 #elif defined CONFIG_NAND_DOLPHIN
139 struct bootloader_header
141 uint32_t version; //version
142 uint32_t magic_num; //0xaa55a5a5
144 uint32_t hash_len; //word length, only used when secure boot enable
145 uint32_t sct_size; //
146 uint32_t acycle; // 3, 4, 5
147 uint32_t bus_width; //0 ,1
148 uint32_t spare_size; //spare part sise for one sector
149 uint32_t ecc_mode; //0--1bit, 1--2bit,2--4bit,3--8bit,4--12bit, 5--16bit, 6--24bit
150 uint32_t ecc_pos; // ecc postion at spare part
151 uint32_t sct_per_page; //sector per page
154 uint32_t ecc_value[27];
158 * spare info data is don't used at the romcode, so the fdl only set the s_info size to 1, and the data value 0xff
160 static void set_header_info(u8 *bl_data, struct mtd_info *nand, int ecc_pos)
162 struct bootloader_header *header;
163 struct nand_chip *chip = nand->priv;
164 struct sprd_ecc_param param;
167 header = (struct bootloader_header *)(bl_data + BOOTLOADER_HEADER_OFFSET);
168 memset(header, 0, sizeof(struct bootloader_header));
169 memset(ecc, 0xff, sizeof(ecc));
171 header->sct_size = chip->ecc.size;
172 if (chip->options & NAND_BUSWIDTH_16) {
173 header->bus_width = 1;
175 if(nand->writesize > 512) {
176 if (chip->chipsize > (128 << 20)) {
184 /* One more address cycle for devices > 32MiB */
186 if (chip->chipsize > (32 << 20)) {
194 header->magic_num = 0xaa55a5a5;
195 header->spare_size = (nand->oobsize/chip->ecc.steps);
196 header->ecc_mode = ecc_mode_convert(chip->eccbitmode);
197 /*ecc is at the last postion at spare part*/
198 header->ecc_pos = header->spare_size - (chip->ecc.bytes);
199 header->sct_per_page = chip->ecc.steps;
201 header->info_pos = header->ecc_pos;
202 header->info_size = 0;
206 param.sinfo_size = 1;
208 param.sp_size = sizeof(ecc);
209 param.m_size = chip->ecc.size;
210 param.p_mbuf = (u8 *)bl_data;
213 sprd_ecc_encode(¶m);
214 memcpy(header->ecc_value, ecc, sizeof(ecc));
217 static int nand_write_spl_page(u8 *buf, struct mtd_info *mtd, u32 pg, u32 ecc_pos)
219 struct nand_chip *chip = mtd->priv;
221 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, pg);
222 //chip->ecc.write_page(mtd, chip, buf);
223 chip->ecc.write_page(mtd, chip, buf);
224 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
225 chip->waitfunc(mtd, chip);
231 #elif defined CONFIG_NAND_SC8830
232 struct bootloader_header
234 uint32_t version; //version
235 uint32_t magic_num; //0xaa55a5a5
237 uint32_t hash_len; //word length, only used when secure boot enable
238 uint32_t sct_size; //
239 uint32_t acycle; // 3, 4, 5
240 uint32_t bus_width; //0 ,1
241 uint32_t spare_size; //spare part sise for one sector
242 uint32_t ecc_mode; //0--1bit, 1--2bit,2--4bit,3--8bit,4--12bit, 5--16bit, 6--24bit
243 uint32_t ecc_pos; // ecc postion at spare part
244 uint32_t sct_per_page; //sector per page
247 uint32_t ecc_value[27];
248 uint32_t page_per_blk;
249 uint32_t img_page[5];
253 * spare info data is don't used at the romcode, so the fdl only set the s_info size to 1, and the data value 0xff
255 static void set_header_info(u8 *bl_data, struct mtd_info *nand, int ecc_pos)
257 struct bootloader_header *header;
258 struct nand_chip *chip = nand->priv;
259 struct sprd_ecc_param param;
262 header = (struct bootloader_header *)(bl_data + BOOTLOADER_HEADER_OFFSET);
263 memset(header, 0, sizeof(struct bootloader_header));
264 memset(ecc, 0xff, sizeof(ecc));
266 header->sct_size = chip->ecc.size;
267 if (chip->options & NAND_BUSWIDTH_16) {
268 header->bus_width = 1;
270 if(nand->writesize > 512) {
271 if (chip->chipsize > (128 << 20)) {
279 /* One more address cycle for devices > 32MiB */
281 if (chip->chipsize > (32 << 20)) {
289 header->magic_num = 0xaa55a5a5;
290 header->spare_size = (nand->oobsize/chip->ecc.steps);
291 header->ecc_mode = ecc_mode_convert(chip->eccbitmode);
293 header->ecc_pos = chip->ecc.layout->eccpos[0];
294 header->sct_per_page = chip->ecc.steps;
296 header->info_pos = chip->ecc.layout->oobfree[0].offset;
297 header->info_size = chip->ecc.layout->oobfree[0].length;
298 #ifdef CONFIG_SECURE_BOOT
299 header->hash_len = CONFIG_SPL_HASH_LEN>>2;
301 header->hash_len = 0;
306 param.sinfo_size = 1;
308 param.sp_size = sizeof(ecc);
309 param.m_size = chip->ecc.size;
310 param.p_mbuf = (u8 *)bl_data;
313 sprd_ecc_encode(¶m);
314 memcpy(header->ecc_value, ecc, sizeof(ecc));
317 static int nand_write_spl_page(u8 *buf, struct mtd_info *mtd, u32 pg, u32 ecc_pos)
319 struct nand_chip *chip = mtd->priv;
321 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, pg);
322 //chip->ecc.write_page(mtd, chip, buf);
323 chip->ecc.write_page(mtd, chip, buf);
324 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
325 chip->waitfunc(mtd, chip);
332 static void set_header_info(u8 *bl_data, struct mtd_info *nand, int ecc_pos)
337 static int nand_write_spl_page(u8 *buf, struct mtd_info *mtd, u32 pg, u32 ecc_pos)
343 int sprd_nand_write_spl(u8 *buf, struct mtd_info *mtd)
352 set_header_info(buf, mtd, CONFIG_SYS_SPL_ECC_POS);
354 /* write spl to flash*/
355 for (i = 0; i < 2; i++)
357 pg_start = i * MAX_SPL_SIZE / mtd->writesize;
358 pg_end = (i + 1) * MAX_SPL_SIZE / mtd->writesize;
360 for(pg = pg_start; pg < pg_end; pg += 1) {
361 ret = nand_write_spl_page(data, mtd, pg, CONFIG_SYS_SPL_ECC_POS);
362 data += mtd->writesize;