1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/mutex.h>
15 #include <linux/math64.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
18 #include <linux/sort.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/of_platform.h>
22 #include <linux/spi/flash.h>
23 #include <linux/mtd/spi-nor.h>
25 /* Define max times to check status register before we give up. */
28 * For everything but full-chip erase; probably could be much smaller, but kept
29 * around for safety for now
31 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
34 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
39 #define SPI_NOR_MAX_ID_LEN 6
40 #define SPI_NOR_MAX_ADDR_WIDTH 4
42 struct spi_nor_read_command {
46 enum spi_nor_protocol proto;
49 struct spi_nor_pp_command {
51 enum spi_nor_protocol proto;
54 enum spi_nor_read_command_index {
57 SNOR_CMD_READ_1_1_1_DTR,
63 SNOR_CMD_READ_1_2_2_DTR,
69 SNOR_CMD_READ_1_4_4_DTR,
75 SNOR_CMD_READ_1_8_8_DTR,
80 enum spi_nor_pp_command_index {
96 struct spi_nor_flash_parameter {
100 struct spi_nor_hwcaps hwcaps;
101 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
102 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
104 int (*quad_enable)(struct spi_nor *nor);
107 struct sfdp_parameter_header {
111 u8 length; /* in double words */
112 u8 parameter_table_pointer[3]; /* byte address */
116 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
117 #define SFDP_PARAM_HEADER_PTP(p) \
118 (((p)->parameter_table_pointer[2] << 16) | \
119 ((p)->parameter_table_pointer[1] << 8) | \
120 ((p)->parameter_table_pointer[0] << 0))
122 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
123 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
124 #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
126 #define SFDP_SIGNATURE 0x50444653U
127 #define SFDP_JESD216_MAJOR 1
128 #define SFDP_JESD216_MINOR 0
129 #define SFDP_JESD216A_MINOR 5
130 #define SFDP_JESD216B_MINOR 6
133 u32 signature; /* Ox50444653U <=> "SFDP" */
136 u8 nph; /* 0-base number of parameter headers */
139 /* Basic Flash Parameter Table. */
140 struct sfdp_parameter_header bfpt_header;
143 /* Basic Flash Parameter Table */
146 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
147 * They are indexed from 1 but C arrays are indexed from 0.
149 #define BFPT_DWORD(i) ((i) - 1)
150 #define BFPT_DWORD_MAX 16
152 /* The first version of JESB216 defined only 9 DWORDs. */
153 #define BFPT_DWORD_MAX_JESD216 9
156 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
157 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
158 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
159 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
160 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
161 #define BFPT_DWORD1_DTR BIT(19)
162 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
163 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
164 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
167 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
168 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
171 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
172 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
177 * (from JESD216 rev B)
178 * Quad Enable Requirements (QER):
179 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
180 * reads based on instruction. DQ3/HOLD# functions are hold during
182 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
183 * two data bytes where bit 1 of the second byte is one.
185 * Writing only one byte to the status register has the side-effect of
186 * clearing status register 2, including the QE bit. The 100b code is
187 * used if writing one byte to the status register does not modify
189 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
190 * one data byte where bit 6 is one.
192 * - 011b: QE is bit 7 of status register 2. It is set via Write status
193 * register 2 instruction 3Eh with one data byte where bit 7 is one.
195 * The status register 2 is read using instruction 3Fh.
196 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
197 * two data bytes where bit 1 of the second byte is one.
199 * In contrast to the 001b code, writing one byte to the status
200 * register does not modify status register 2.
201 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
202 * Read Status instruction 05h. Status register2 is read using
203 * instruction 35h. QE is set via Writ Status instruction 01h with
204 * two data bytes where bit 1 of the second byte is one.
207 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
208 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
209 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
210 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
211 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
212 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
213 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
216 u32 dwords[BFPT_DWORD_MAX];
220 * struct spi_nor_fixups - SPI NOR fixup hooks
221 * @post_bfpt: called after the BFPT table has been parsed
223 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
224 * table is broken or not available.
226 struct spi_nor_fixups {
227 int (*post_bfpt)(struct spi_nor *nor,
228 const struct sfdp_parameter_header *bfpt_header,
229 const struct sfdp_bfpt *bfpt,
230 struct spi_nor_flash_parameter *params);
237 * This array stores the ID bytes.
238 * The first three bytes are the JEDIC ID.
239 * JEDEC ID zero means "no ID" (mostly older chips).
241 u8 id[SPI_NOR_MAX_ID_LEN];
244 /* The size listed here is what works with SPINOR_OP_SE, which isn't
245 * necessarily called a "sector" by the vendor.
247 unsigned sector_size;
254 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
255 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
256 #define SST_WRITE BIT(2) /* use SST byte programming */
257 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
258 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
259 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
260 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
261 #define USE_FSR BIT(7) /* use flag status register */
262 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
263 #define SPI_NOR_HAS_TB BIT(9) /*
264 * Flash SR has Top/Bottom (TB) protect
265 * bit. Must be used with
268 #define SPI_S3AN BIT(10) /*
269 * Xilinx Spartan 3AN In-System Flash
270 * (MFR cannot be used for probing
271 * because it has the same value as
274 #define SPI_NOR_4B_OPCODES BIT(11) /*
275 * Use dedicated 4byte address op codes
276 * to support memory size above 128Mib.
278 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
279 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
280 #define USE_CLSR BIT(14) /* use CLSR command */
281 #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
283 /* Part specific fixup hooks. */
284 const struct spi_nor_fixups *fixups;
286 int (*quad_enable)(struct spi_nor *nor);
289 #define JEDEC_MFR(info) ((info)->id[0])
292 * Read the status register, returning its value in the location
293 * Return the status register value.
294 * Returns negative if error occurred.
296 static int read_sr(struct spi_nor *nor)
301 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
303 pr_err("error %d reading SR\n", (int) ret);
311 * Read the flag status register, returning its value in the location
312 * Return the status register value.
313 * Returns negative if error occurred.
315 static int read_fsr(struct spi_nor *nor)
320 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
322 pr_err("error %d reading FSR\n", ret);
330 * Read configuration register, returning its value in the
331 * location. Return the configuration register value.
332 * Returns negative if error occurred.
334 static int read_cr(struct spi_nor *nor)
339 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
341 dev_err(nor->dev, "error %d reading CR\n", ret);
349 * Write status register 1 byte
350 * Returns negative if error occurred.
352 static int write_sr(struct spi_nor *nor, u8 val)
354 nor->cmd_buf[0] = val;
355 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
359 * Set write enable latch with Write Enable command.
360 * Returns negative if error occurred.
362 static int write_enable(struct spi_nor *nor)
364 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
368 * Send write disable instruction to the chip.
370 static int write_disable(struct spi_nor *nor)
372 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
375 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
381 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
385 for (i = 0; i < size; i++)
386 if (table[i][0] == opcode)
389 /* No conversion found, keep input op code. */
393 static u8 spi_nor_convert_3to4_read(u8 opcode)
395 static const u8 spi_nor_3to4_read[][2] = {
396 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
397 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
398 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
399 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
400 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
401 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
402 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
403 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
405 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
406 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
407 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
410 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
411 ARRAY_SIZE(spi_nor_3to4_read));
414 static u8 spi_nor_convert_3to4_program(u8 opcode)
416 static const u8 spi_nor_3to4_program[][2] = {
417 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
418 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
419 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
420 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
421 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
424 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
425 ARRAY_SIZE(spi_nor_3to4_program));
428 static u8 spi_nor_convert_3to4_erase(u8 opcode)
430 static const u8 spi_nor_3to4_erase[][2] = {
431 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
432 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
433 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
436 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
437 ARRAY_SIZE(spi_nor_3to4_erase));
440 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
442 /* Do some manufacturer fixups first */
443 switch (JEDEC_MFR(nor->info)) {
444 case SNOR_MFR_SPANSION:
445 /* No small sector erase for 4-byte command set */
446 nor->erase_opcode = SPINOR_OP_SE;
447 nor->mtd.erasesize = nor->info->sector_size;
454 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
455 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
456 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
458 if (!spi_nor_has_uniform_erase(nor)) {
459 struct spi_nor_erase_map *map = &nor->erase_map;
460 struct spi_nor_erase_type *erase;
463 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
464 erase = &map->erase_type[i];
466 spi_nor_convert_3to4_erase(erase->opcode);
471 /* Enable/disable 4-byte addressing mode. */
472 static int set_4byte(struct spi_nor *nor, bool enable)
475 bool need_wren = false;
478 switch (JEDEC_MFR(nor->info)) {
480 case SNOR_MFR_MICRON:
481 /* Some Micron need WREN command; all will accept it */
484 case SNOR_MFR_MACRONIX:
485 case SNOR_MFR_WINBOND:
489 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
490 status = nor->write_reg(nor, cmd, NULL, 0);
494 if (!status && !enable &&
495 JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND) {
497 * On Winbond W25Q256FV, leaving 4byte mode causes
498 * the Extended Address Register to be set to 1, so all
499 * 3-byte-address reads come from the second 16M.
500 * We must clear the register to enable normal behavior.
504 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
511 nor->cmd_buf[0] = enable << 7;
512 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
516 static int s3an_sr_ready(struct spi_nor *nor)
521 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
523 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
527 return !!(val & XSR_RDY);
530 static int spi_nor_sr_ready(struct spi_nor *nor)
532 int sr = read_sr(nor);
536 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
538 dev_err(nor->dev, "Erase Error occurred\n");
540 dev_err(nor->dev, "Programming Error occurred\n");
542 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
546 return !(sr & SR_WIP);
549 static int spi_nor_fsr_ready(struct spi_nor *nor)
551 int fsr = read_fsr(nor);
555 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
557 dev_err(nor->dev, "Erase operation failed.\n");
559 dev_err(nor->dev, "Program operation failed.\n");
561 if (fsr & FSR_PT_ERR)
563 "Attempted to modify a protected sector.\n");
565 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
569 return fsr & FSR_READY;
572 static int spi_nor_ready(struct spi_nor *nor)
576 if (nor->flags & SNOR_F_READY_XSR_RDY)
577 sr = s3an_sr_ready(nor);
579 sr = spi_nor_sr_ready(nor);
582 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
589 * Service routine to read status register until ready, or timeout occurs.
590 * Returns non-zero if error.
592 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
593 unsigned long timeout_jiffies)
595 unsigned long deadline;
596 int timeout = 0, ret;
598 deadline = jiffies + timeout_jiffies;
601 if (time_after_eq(jiffies, deadline))
604 ret = spi_nor_ready(nor);
613 dev_err(nor->dev, "flash operation timed out\n");
618 static int spi_nor_wait_till_ready(struct spi_nor *nor)
620 return spi_nor_wait_till_ready_with_timeout(nor,
621 DEFAULT_READY_WAIT_JIFFIES);
625 * Erase the whole flash memory
627 * Returns 0 if successful, non-zero otherwise.
629 static int erase_chip(struct spi_nor *nor)
631 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
633 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
636 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
640 mutex_lock(&nor->lock);
643 ret = nor->prepare(nor, ops);
645 dev_err(nor->dev, "failed in the preparation.\n");
646 mutex_unlock(&nor->lock);
653 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
656 nor->unprepare(nor, ops);
657 mutex_unlock(&nor->lock);
661 * This code converts an address to the Default Address Mode, that has non
662 * power of two page sizes. We must support this mode because it is the default
663 * mode supported by Xilinx tools, it can access the whole flash area and
664 * changing over to the Power-of-two mode is irreversible and corrupts the
666 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
669 static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
674 offset = addr % nor->page_size;
675 page = addr / nor->page_size;
676 page <<= (nor->page_size > 512) ? 10 : 9;
678 return page | offset;
682 * Initiate the erasure of a single sector
684 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
686 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
689 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
690 addr = spi_nor_s3an_addr_convert(nor, addr);
693 return nor->erase(nor, addr);
696 * Default implementation, if driver doesn't have a specialized HW
699 for (i = nor->addr_width - 1; i >= 0; i--) {
700 buf[i] = addr & 0xff;
704 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
708 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
709 * @erase: pointer to a structure that describes a SPI NOR erase type
710 * @dividend: dividend value
711 * @remainder: pointer to u32 remainder (will be updated)
713 * Return: the result of the division
715 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
716 u64 dividend, u32 *remainder)
718 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
719 *remainder = (u32)dividend & erase->size_mask;
720 return dividend >> erase->size_shift;
724 * spi_nor_find_best_erase_type() - find the best erase type for the given
725 * offset in the serial flash memory and the
726 * number of bytes to erase. The region in
727 * which the address fits is expected to be
729 * @map: the erase map of the SPI NOR
730 * @region: pointer to a structure that describes a SPI NOR erase region
731 * @addr: offset in the serial flash memory
732 * @len: number of bytes to erase
734 * Return: a pointer to the best fitted erase type, NULL otherwise.
736 static const struct spi_nor_erase_type *
737 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
738 const struct spi_nor_erase_region *region,
741 const struct spi_nor_erase_type *erase;
744 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
747 * Erase types are ordered by size, with the smallest erase type at
750 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
751 /* Does the erase region support the tested erase type? */
752 if (!(erase_mask & BIT(i)))
755 erase = &map->erase_type[i];
757 /* Don't erase more than what the user has asked for. */
758 if (erase->size > len)
761 /* Alignment is not mandatory for overlaid regions */
762 if (region->offset & SNOR_OVERLAID_REGION)
765 spi_nor_div_by_erase_size(erase, addr, &rem);
776 * spi_nor_region_next() - get the next spi nor region
777 * @region: pointer to a structure that describes a SPI NOR erase region
779 * Return: the next spi nor region or NULL if last region.
781 static struct spi_nor_erase_region *
782 spi_nor_region_next(struct spi_nor_erase_region *region)
784 if (spi_nor_region_is_last(region))
791 * spi_nor_find_erase_region() - find the region of the serial flash memory in
792 * which the offset fits
793 * @map: the erase map of the SPI NOR
794 * @addr: offset in the serial flash memory
796 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
799 static struct spi_nor_erase_region *
800 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
802 struct spi_nor_erase_region *region = map->regions;
803 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
804 u64 region_end = region_start + region->size;
806 while (addr < region_start || addr >= region_end) {
807 region = spi_nor_region_next(region);
809 return ERR_PTR(-EINVAL);
811 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
812 region_end = region_start + region->size;
819 * spi_nor_init_erase_cmd() - initialize an erase command
820 * @region: pointer to a structure that describes a SPI NOR erase region
821 * @erase: pointer to a structure that describes a SPI NOR erase type
823 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
826 static struct spi_nor_erase_command *
827 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
828 const struct spi_nor_erase_type *erase)
830 struct spi_nor_erase_command *cmd;
832 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
834 return ERR_PTR(-ENOMEM);
836 INIT_LIST_HEAD(&cmd->list);
837 cmd->opcode = erase->opcode;
840 if (region->offset & SNOR_OVERLAID_REGION)
841 cmd->size = region->size;
843 cmd->size = erase->size;
849 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
850 * @erase_list: list of erase commands
852 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
854 struct spi_nor_erase_command *cmd, *next;
856 list_for_each_entry_safe(cmd, next, erase_list, list) {
857 list_del(&cmd->list);
863 * spi_nor_init_erase_cmd_list() - initialize erase command list
864 * @nor: pointer to a 'struct spi_nor'
865 * @erase_list: list of erase commands to be executed once we validate that the
866 * erase can be performed
867 * @addr: offset in the serial flash memory
868 * @len: number of bytes to erase
870 * Builds the list of best fitted erase commands and verifies if the erase can
873 * Return: 0 on success, -errno otherwise.
875 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
876 struct list_head *erase_list,
879 const struct spi_nor_erase_map *map = &nor->erase_map;
880 const struct spi_nor_erase_type *erase, *prev_erase = NULL;
881 struct spi_nor_erase_region *region;
882 struct spi_nor_erase_command *cmd = NULL;
886 region = spi_nor_find_erase_region(map, addr);
888 return PTR_ERR(region);
890 region_end = spi_nor_region_end(region);
893 erase = spi_nor_find_best_erase_type(map, region, addr, len);
895 goto destroy_erase_cmd_list;
897 if (prev_erase != erase ||
898 region->offset & SNOR_OVERLAID_REGION) {
899 cmd = spi_nor_init_erase_cmd(region, erase);
902 goto destroy_erase_cmd_list;
905 list_add_tail(&cmd->list, erase_list);
913 if (len && addr >= region_end) {
914 region = spi_nor_region_next(region);
916 goto destroy_erase_cmd_list;
917 region_end = spi_nor_region_end(region);
925 destroy_erase_cmd_list:
926 spi_nor_destroy_erase_cmd_list(erase_list);
931 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
932 * @nor: pointer to a 'struct spi_nor'
933 * @addr: offset in the serial flash memory
934 * @len: number of bytes to erase
936 * Build a list of best fitted erase commands and execute it once we validate
937 * that the erase can be performed.
939 * Return: 0 on success, -errno otherwise.
941 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
943 LIST_HEAD(erase_list);
944 struct spi_nor_erase_command *cmd, *next;
947 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
951 list_for_each_entry_safe(cmd, next, &erase_list, list) {
952 nor->erase_opcode = cmd->opcode;
956 ret = spi_nor_erase_sector(nor, addr);
958 goto destroy_erase_cmd_list;
963 ret = spi_nor_wait_till_ready(nor);
965 goto destroy_erase_cmd_list;
967 list_del(&cmd->list);
973 destroy_erase_cmd_list:
974 spi_nor_destroy_erase_cmd_list(&erase_list);
979 * Erase an address range on the nor chip. The address range may extend
980 * one or more erase sectors. Return an error is there is a problem erasing.
982 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
984 struct spi_nor *nor = mtd_to_spi_nor(mtd);
989 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
990 (long long)instr->len);
992 if (spi_nor_has_uniform_erase(nor)) {
993 div_u64_rem(instr->len, mtd->erasesize, &rem);
1001 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
1005 /* whole-chip erase? */
1006 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1007 unsigned long timeout;
1011 if (erase_chip(nor)) {
1017 * Scale the timeout linearly with the size of the flash, with
1018 * a minimum calibrated to an old 2MB flash. We could try to
1019 * pull these from CFI/SFDP, but these values should be good
1022 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1023 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1024 (unsigned long)(mtd->size / SZ_2M));
1025 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1029 /* REVISIT in some cases we could speed up erasing large regions
1030 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1031 * to use "small sector erase", but that's not always optimal.
1034 /* "sector"-at-a-time erase */
1035 } else if (spi_nor_has_uniform_erase(nor)) {
1039 ret = spi_nor_erase_sector(nor, addr);
1043 addr += mtd->erasesize;
1044 len -= mtd->erasesize;
1046 ret = spi_nor_wait_till_ready(nor);
1051 /* erase multiple sectors */
1053 ret = spi_nor_erase_multi_sectors(nor, addr, len);
1061 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
1066 /* Write status register and ensure bits in mask match written values */
1067 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
1072 ret = write_sr(nor, status_new);
1076 ret = spi_nor_wait_till_ready(nor);
1084 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
1087 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
1090 struct mtd_info *mtd = &nor->mtd;
1091 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1092 int shift = ffs(mask) - 1;
1100 pow = ((sr & mask) ^ mask) >> shift;
1101 *len = mtd->size >> pow;
1102 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
1105 *ofs = mtd->size - *len;
1110 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
1111 * @locked is false); 0 otherwise
1113 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1122 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
1125 /* Requested range is a sub-range of locked range */
1126 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
1128 /* Requested range does not overlap with locked range */
1129 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
1132 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1135 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
1138 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1141 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
1145 * Lock a region of the flash. Compatible with ST Micro and similar flash.
1146 * Supports the block protection bits BP{0,1,2} in the status register
1147 * (SR). Does not support these features found in newer SR bitfields:
1148 * - SEC: sector/block protect - only handle SEC=0 (block protect)
1149 * - CMP: complement protect - only support CMP=0 (range is not complemented)
1151 * Support for the following is provided conditionally for some flash:
1152 * - TB: top/bottom protect
1154 * Sample table portion for 8MB flash (Winbond w25q64fw):
1156 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
1157 * --------------------------------------------------------------------------
1158 * X | X | 0 | 0 | 0 | NONE | NONE
1159 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
1160 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
1161 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
1162 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
1163 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
1164 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
1165 * X | X | 1 | 1 | 1 | 8 MB | ALL
1166 * ------|-------|-------|-------|-------|---------------|-------------------
1167 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
1168 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
1169 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
1170 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
1171 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
1172 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
1174 * Returns negative on errors, 0 on success.
1176 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1178 struct mtd_info *mtd = &nor->mtd;
1179 int status_old, status_new;
1180 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1181 u8 shift = ffs(mask) - 1, pow, val;
1183 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1186 status_old = read_sr(nor);
1190 /* If nothing in our range is unlocked, we don't need to do anything */
1191 if (stm_is_locked_sr(nor, ofs, len, status_old))
1194 /* If anything below us is unlocked, we can't use 'bottom' protection */
1195 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
1196 can_be_bottom = false;
1198 /* If anything above us is unlocked, we can't use 'top' protection */
1199 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1203 if (!can_be_bottom && !can_be_top)
1206 /* Prefer top, if both are valid */
1207 use_top = can_be_top;
1209 /* lock_len: length of region that should end up locked */
1211 lock_len = mtd->size - ofs;
1213 lock_len = ofs + len;
1216 * Need smallest pow such that:
1218 * 1 / (2^pow) <= (len / size)
1220 * so (assuming power-of-2 size) we do:
1222 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
1224 pow = ilog2(mtd->size) - ilog2(lock_len);
1225 val = mask - (pow << shift);
1228 /* Don't "lock" with no region! */
1232 status_new = (status_old & ~mask & ~SR_TB) | val;
1234 /* Disallow further writes if WP pin is asserted */
1235 status_new |= SR_SRWD;
1238 status_new |= SR_TB;
1240 /* Don't bother if they're the same */
1241 if (status_new == status_old)
1244 /* Only modify protection if it will not unlock other areas */
1245 if ((status_new & mask) < (status_old & mask))
1248 return write_sr_and_check(nor, status_new, mask);
1252 * Unlock a region of the flash. See stm_lock() for more info
1254 * Returns negative on errors, 0 on success.
1256 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1258 struct mtd_info *mtd = &nor->mtd;
1259 int status_old, status_new;
1260 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1261 u8 shift = ffs(mask) - 1, pow, val;
1263 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1266 status_old = read_sr(nor);
1270 /* If nothing in our range is locked, we don't need to do anything */
1271 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
1274 /* If anything below us is locked, we can't use 'top' protection */
1275 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
1278 /* If anything above us is locked, we can't use 'bottom' protection */
1279 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1281 can_be_bottom = false;
1283 if (!can_be_bottom && !can_be_top)
1286 /* Prefer top, if both are valid */
1287 use_top = can_be_top;
1289 /* lock_len: length of region that should remain locked */
1291 lock_len = mtd->size - (ofs + len);
1296 * Need largest pow such that:
1298 * 1 / (2^pow) >= (len / size)
1300 * so (assuming power-of-2 size) we do:
1302 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
1304 pow = ilog2(mtd->size) - order_base_2(lock_len);
1305 if (lock_len == 0) {
1306 val = 0; /* fully unlocked */
1308 val = mask - (pow << shift);
1309 /* Some power-of-two sizes are not supported */
1314 status_new = (status_old & ~mask & ~SR_TB) | val;
1316 /* Don't protect status register if we're fully unlocked */
1318 status_new &= ~SR_SRWD;
1321 status_new |= SR_TB;
1323 /* Don't bother if they're the same */
1324 if (status_new == status_old)
1327 /* Only modify protection if it will not lock other areas */
1328 if ((status_new & mask) > (status_old & mask))
1331 return write_sr_and_check(nor, status_new, mask);
1335 * Check if a region of the flash is (completely) locked. See stm_lock() for
1338 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1339 * negative on errors.
1341 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1345 status = read_sr(nor);
1349 return stm_is_locked_sr(nor, ofs, len, status);
1352 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1354 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1357 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
1361 ret = nor->flash_lock(nor, ofs, len);
1363 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
1367 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1369 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1372 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1376 ret = nor->flash_unlock(nor, ofs, len);
1378 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1382 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1384 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1387 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1391 ret = nor->flash_is_locked(nor, ofs, len);
1393 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1398 * Write status Register and configuration register with 2 bytes
1399 * The first byte will be written to the status register, while the
1400 * second byte will be written to the configuration register.
1401 * Return negative if error occurred.
1403 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1409 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1412 "error while writing configuration register\n");
1416 ret = spi_nor_wait_till_ready(nor);
1419 "timeout while writing configuration register\n");
1427 * macronix_quad_enable() - set QE bit in Status Register.
1428 * @nor: pointer to a 'struct spi_nor'
1430 * Set the Quad Enable (QE) bit in the Status Register.
1432 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1434 * Return: 0 on success, -errno otherwise.
1436 static int macronix_quad_enable(struct spi_nor *nor)
1443 if (val & SR_QUAD_EN_MX)
1448 write_sr(nor, val | SR_QUAD_EN_MX);
1450 ret = spi_nor_wait_till_ready(nor);
1455 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1456 dev_err(nor->dev, "Macronix Quad bit not set\n");
1464 * spansion_quad_enable() - set QE bit in Configuraiton Register.
1465 * @nor: pointer to a 'struct spi_nor'
1467 * Set the Quad Enable (QE) bit in the Configuration Register.
1468 * This function is kept for legacy purpose because it has been used for a
1469 * long time without anybody complaining but it should be considered as
1470 * deprecated and maybe buggy.
1471 * First, this function doesn't care about the previous values of the Status
1472 * and Configuration Registers when it sets the QE bit (bit 1) in the
1473 * Configuration Register: all other bits are cleared, which may have unwanted
1474 * side effects like removing some block protections.
1475 * Secondly, it uses the Read Configuration Register (35h) instruction though
1476 * some very old and few memories don't support this instruction. If a pull-up
1477 * resistor is present on the MISO/IO1 line, we might still be able to pass the
1478 * "read back" test because the QSPI memory doesn't recognize the command,
1479 * so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
1481 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1484 * Return: 0 on success, -errno otherwise.
1486 static int spansion_quad_enable(struct spi_nor *nor)
1488 u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
1491 ret = write_sr_cr(nor, sr_cr);
1495 /* read back and check it */
1497 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1498 dev_err(nor->dev, "Spansion Quad bit not set\n");
1506 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1507 * @nor: pointer to a 'struct spi_nor'
1509 * Set the Quad Enable (QE) bit in the Configuration Register.
1510 * This function should be used with QSPI memories not supporting the Read
1511 * Configuration Register (35h) instruction.
1513 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1516 * Return: 0 on success, -errno otherwise.
1518 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1523 /* Keep the current value of the Status Register. */
1526 dev_err(nor->dev, "error while reading status register\n");
1530 sr_cr[1] = CR_QUAD_EN_SPAN;
1532 return write_sr_cr(nor, sr_cr);
1536 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1537 * @nor: pointer to a 'struct spi_nor'
1539 * Set the Quad Enable (QE) bit in the Configuration Register.
1540 * This function should be used with QSPI memories supporting the Read
1541 * Configuration Register (35h) instruction.
1543 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1546 * Return: 0 on success, -errno otherwise.
1548 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1550 struct device *dev = nor->dev;
1554 /* Check current Quad Enable bit value. */
1557 dev_err(dev, "error while reading configuration register\n");
1561 if (ret & CR_QUAD_EN_SPAN)
1564 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1566 /* Keep the current value of the Status Register. */
1569 dev_err(dev, "error while reading status register\n");
1574 ret = write_sr_cr(nor, sr_cr);
1578 /* Read back and check it. */
1580 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1581 dev_err(nor->dev, "Spansion Quad bit not set\n");
1589 * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1590 * @nor: pointer to a 'struct spi_nor'
1592 * Set the Quad Enable (QE) bit in the Status Register 2.
1594 * This is one of the procedures to set the QE bit described in the SFDP
1595 * (JESD216 rev B) specification but no manufacturer using this procedure has
1596 * been identified yet, hence the name of the function.
1598 * Return: 0 on success, -errno otherwise.
1600 static int sr2_bit7_quad_enable(struct spi_nor *nor)
1605 /* Check current Quad Enable bit value. */
1606 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1609 if (sr2 & SR2_QUAD_EN_BIT7)
1612 /* Update the Quad Enable bit. */
1613 sr2 |= SR2_QUAD_EN_BIT7;
1617 ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
1619 dev_err(nor->dev, "error while writing status register 2\n");
1623 ret = spi_nor_wait_till_ready(nor);
1625 dev_err(nor->dev, "timeout while writing status register 2\n");
1629 /* Read back and check it. */
1630 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1631 if (!(ret > 0 && (sr2 & SR2_QUAD_EN_BIT7))) {
1632 dev_err(nor->dev, "SR2 Quad bit not set\n");
1640 * spi_nor_clear_sr_bp() - clear the Status Register Block Protection bits.
1641 * @nor: pointer to a 'struct spi_nor'
1643 * Read-modify-write function that clears the Block Protection bits from the
1644 * Status Register without affecting other bits.
1646 * Return: 0 on success, -errno otherwise.
1648 static int spi_nor_clear_sr_bp(struct spi_nor *nor)
1651 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1655 dev_err(nor->dev, "error while reading status register\n");
1661 ret = write_sr(nor, ret & ~mask);
1663 dev_err(nor->dev, "write to status register failed\n");
1667 ret = spi_nor_wait_till_ready(nor);
1669 dev_err(nor->dev, "timeout while writing status register\n");
1674 * spi_nor_spansion_clear_sr_bp() - clear the Status Register Block Protection
1675 * bits on spansion flashes.
1676 * @nor: pointer to a 'struct spi_nor'
1678 * Read-modify-write function that clears the Block Protection bits from the
1679 * Status Register without affecting other bits. The function is tightly
1680 * coupled with the spansion_quad_enable() function. Both assume that the Write
1681 * Register with 16 bits, together with the Read Configuration Register (35h)
1682 * instructions are supported.
1684 * Return: 0 on success, -errno otherwise.
1686 static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
1689 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1692 /* Check current Quad Enable bit value. */
1696 "error while reading configuration register\n");
1701 * When the configuration register Quad Enable bit is one, only the
1702 * Write Status (01h) command with two data bytes may be used.
1704 if (ret & CR_QUAD_EN_SPAN) {
1710 "error while reading status register\n");
1713 sr_cr[0] = ret & ~mask;
1715 ret = write_sr_cr(nor, sr_cr);
1717 dev_err(nor->dev, "16-bit write register failed\n");
1722 * If the Quad Enable bit is zero, use the Write Status (01h) command
1723 * with one data byte.
1725 return spi_nor_clear_sr_bp(nor);
1728 /* Used when the "_ext_id" is two bytes at most */
1729 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
1731 ((_jedec_id) >> 16) & 0xff, \
1732 ((_jedec_id) >> 8) & 0xff, \
1733 (_jedec_id) & 0xff, \
1734 ((_ext_id) >> 8) & 0xff, \
1737 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
1738 .sector_size = (_sector_size), \
1739 .n_sectors = (_n_sectors), \
1743 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
1745 ((_jedec_id) >> 16) & 0xff, \
1746 ((_jedec_id) >> 8) & 0xff, \
1747 (_jedec_id) & 0xff, \
1748 ((_ext_id) >> 16) & 0xff, \
1749 ((_ext_id) >> 8) & 0xff, \
1753 .sector_size = (_sector_size), \
1754 .n_sectors = (_n_sectors), \
1758 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
1759 .sector_size = (_sector_size), \
1760 .n_sectors = (_n_sectors), \
1761 .page_size = (_page_size), \
1762 .addr_width = (_addr_width), \
1765 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
1767 ((_jedec_id) >> 16) & 0xff, \
1768 ((_jedec_id) >> 8) & 0xff, \
1769 (_jedec_id) & 0xff \
1772 .sector_size = (8*_page_size), \
1773 .n_sectors = (_n_sectors), \
1774 .page_size = _page_size, \
1776 .flags = SPI_NOR_NO_FR | SPI_S3AN,
1779 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
1780 const struct sfdp_parameter_header *bfpt_header,
1781 const struct sfdp_bfpt *bfpt,
1782 struct spi_nor_flash_parameter *params)
1785 * MX25L25635F supports 4B opcodes but MX25L25635E does not.
1786 * Unfortunately, Macronix has re-used the same JEDEC ID for both
1787 * variants which prevents us from defining a new entry in the parts
1789 * We need a way to differentiate MX25L25635E and MX25L25635F, and it
1790 * seems that the F version advertises support for Fast Read 4-4-4 in
1793 if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
1794 nor->flags |= SNOR_F_4B_OPCODES;
1799 static struct spi_nor_fixups mx25l25635_fixups = {
1800 .post_bfpt = mx25l25635_post_bfpt_fixups,
1803 /* NOTE: double check command sets and memory organization when you add
1804 * more nor chips. This current list focusses on newer chips, which
1805 * have been converging on command sets which including JEDEC ID.
1807 * All newly added entries should describe *hardware* and should use SECT_4K
1808 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
1809 * scenarios excluding small sectors there is config option that can be
1810 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
1811 * For historical (and compatibility) reasons (before we got above config) some
1812 * old entries may be missing 4K flag.
1814 static const struct flash_info spi_nor_ids[] = {
1815 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
1816 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
1817 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
1819 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
1820 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
1821 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
1822 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
1824 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
1825 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
1826 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
1827 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
1829 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
1831 /* EON -- en25xxx */
1832 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
1833 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
1834 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
1835 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
1836 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
1837 { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16,
1838 SECT_4K | SPI_NOR_DUAL_READ) },
1839 { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
1840 { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128,
1841 SECT_4K | SPI_NOR_DUAL_READ) },
1842 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
1843 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
1844 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
1847 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
1848 { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
1849 { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
1852 { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1853 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1854 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1855 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1858 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
1862 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
1863 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1864 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1867 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
1868 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1869 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1872 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
1873 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1874 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1877 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
1878 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1879 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1882 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
1883 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1884 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1887 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
1888 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1889 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1892 "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
1893 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1894 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1895 .quad_enable = macronix_quad_enable,
1898 /* Intel/Numonyx -- xxxs33b */
1899 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
1900 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
1901 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
1904 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
1905 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
1906 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1907 { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
1908 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1909 { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
1910 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1911 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
1912 SECT_4K | SPI_NOR_DUAL_READ) },
1913 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128,
1914 SECT_4K | SPI_NOR_DUAL_READ) },
1915 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
1916 SECT_4K | SPI_NOR_DUAL_READ) },
1917 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
1918 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1919 SPI_NOR_4B_OPCODES) },
1920 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
1921 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1922 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
1923 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1924 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
1925 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1928 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
1929 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
1930 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
1931 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
1932 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
1933 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
1934 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
1935 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
1936 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
1937 { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
1938 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1939 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
1940 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
1941 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
1942 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1943 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1944 { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
1945 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1946 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
1947 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
1948 .fixups = &mx25l25635_fixups },
1949 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
1950 { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
1951 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1952 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1953 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1954 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1955 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1956 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
1958 /* Micron <--> ST Micro */
1959 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
1960 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1961 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1962 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1963 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1964 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1965 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1966 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1967 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
1968 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1969 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1970 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1971 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1972 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1976 "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
1977 SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
1982 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
1983 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
1984 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
1986 /* Spansion/Cypress -- single (large) sector size only, at least
1987 * for the chips listed here (without boot sectors).
1989 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1990 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1991 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
1992 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1993 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
1994 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1995 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
1996 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1997 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
1998 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1999 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | USE_CLSR) },
2000 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2001 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
2002 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
2003 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
2004 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2005 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2006 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
2007 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
2008 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
2009 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
2010 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
2011 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2012 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2013 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2014 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
2015 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2016 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
2017 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
2018 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
2019 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
2020 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2021 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2022 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2024 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
2025 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
2026 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
2027 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
2028 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
2029 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
2030 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
2031 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
2032 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
2033 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
2034 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
2035 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
2036 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
2037 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2039 /* ST Microelectronics -- newer production may have feature updates */
2040 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
2041 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
2042 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
2043 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
2044 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
2045 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
2046 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
2047 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
2048 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
2050 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
2051 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
2052 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
2053 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
2054 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
2055 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
2056 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
2057 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
2058 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
2060 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
2061 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
2062 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
2064 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
2065 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
2066 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
2068 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
2069 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
2070 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
2071 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
2072 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
2073 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
2075 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
2076 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
2077 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
2078 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
2079 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
2080 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
2081 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
2083 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
2084 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2085 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2087 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
2088 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
2089 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
2090 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
2091 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
2093 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
2094 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2095 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2098 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
2099 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2100 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2102 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
2103 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
2105 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
2106 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2107 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2110 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
2111 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2112 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2115 "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
2116 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2117 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2119 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
2120 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
2121 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
2122 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2123 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
2124 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
2126 /* Catalyst / On Semiconductor -- non-JEDEC */
2127 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2128 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2129 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2130 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2131 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2133 /* Xilinx S3AN Internal Flash */
2134 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
2135 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
2136 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
2137 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
2138 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
2140 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
2141 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2142 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2146 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
2149 u8 id[SPI_NOR_MAX_ID_LEN];
2150 const struct flash_info *info;
2152 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
2154 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
2155 return ERR_PTR(tmp);
2158 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
2159 info = &spi_nor_ids[tmp];
2161 if (!memcmp(info->id, id, info->id_len))
2162 return &spi_nor_ids[tmp];
2165 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
2166 SPI_NOR_MAX_ID_LEN, id);
2167 return ERR_PTR(-ENODEV);
2170 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2171 size_t *retlen, u_char *buf)
2173 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2176 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2178 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
2185 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
2186 addr = spi_nor_s3an_addr_convert(nor, addr);
2188 ret = nor->read(nor, addr, len, buf);
2190 /* We shouldn't see 0-length reads */
2206 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
2210 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
2211 size_t *retlen, const u_char *buf)
2213 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2217 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2219 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
2225 nor->sst_write_second = false;
2228 /* Start write from odd address. */
2230 nor->program_opcode = SPINOR_OP_BP;
2232 /* write one byte. */
2233 ret = nor->write(nor, to, 1, buf);
2236 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
2238 ret = spi_nor_wait_till_ready(nor);
2244 /* Write out most of the data here. */
2245 for (; actual < len - 1; actual += 2) {
2246 nor->program_opcode = SPINOR_OP_AAI_WP;
2248 /* write two bytes. */
2249 ret = nor->write(nor, to, 2, buf + actual);
2252 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
2254 ret = spi_nor_wait_till_ready(nor);
2258 nor->sst_write_second = true;
2260 nor->sst_write_second = false;
2263 ret = spi_nor_wait_till_ready(nor);
2267 /* Write out trailing byte if it exists. */
2268 if (actual != len) {
2271 nor->program_opcode = SPINOR_OP_BP;
2272 ret = nor->write(nor, to, 1, buf + actual);
2275 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
2277 ret = spi_nor_wait_till_ready(nor);
2285 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
2290 * Write an address range to the nor chip. Data must be written in
2291 * FLASH_PAGESIZE chunks. The address range may be any size provided
2292 * it is within the physical boundaries.
2294 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2295 size_t *retlen, const u_char *buf)
2297 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2298 size_t page_offset, page_remain, i;
2301 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2303 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
2307 for (i = 0; i < len; ) {
2309 loff_t addr = to + i;
2312 * If page_size is a power of two, the offset can be quickly
2313 * calculated with an AND operation. On the other cases we
2314 * need to do a modulus operation (more expensive).
2315 * Power of two numbers have only one bit set and we can use
2316 * the instruction hweight32 to detect if we need to do a
2317 * modulus (do_div()) or not.
2319 if (hweight32(nor->page_size) == 1) {
2320 page_offset = addr & (nor->page_size - 1);
2322 uint64_t aux = addr;
2324 page_offset = do_div(aux, nor->page_size);
2326 /* the size of data remaining on the first page */
2327 page_remain = min_t(size_t,
2328 nor->page_size - page_offset, len - i);
2330 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
2331 addr = spi_nor_s3an_addr_convert(nor, addr);
2334 ret = nor->write(nor, addr, page_remain, buf + i);
2339 ret = spi_nor_wait_till_ready(nor);
2347 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
2351 static int spi_nor_check(struct spi_nor *nor)
2353 if (!nor->dev || !nor->read || !nor->write ||
2354 !nor->read_reg || !nor->write_reg) {
2355 pr_err("spi-nor: please fill all the necessary fields!\n");
2362 static int s3an_nor_scan(struct spi_nor *nor)
2367 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
2369 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
2373 nor->erase_opcode = SPINOR_OP_XSE;
2374 nor->program_opcode = SPINOR_OP_XPP;
2375 nor->read_opcode = SPINOR_OP_READ;
2376 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2379 * This flashes have a page size of 264 or 528 bytes (known as
2380 * Default addressing mode). It can be changed to a more standard
2381 * Power of two mode where the page size is 256/512. This comes
2382 * with a price: there is 3% less of space, the data is corrupted
2383 * and the page size cannot be changed back to default addressing
2386 * The current addressing mode can be read from the XRDSR register
2387 * and should not be changed, because is a destructive operation.
2389 if (val & XSR_PAGESIZE) {
2390 /* Flash in Power of 2 mode */
2391 nor->page_size = (nor->page_size == 264) ? 256 : 512;
2392 nor->mtd.writebufsize = nor->page_size;
2393 nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors;
2394 nor->mtd.erasesize = 8 * nor->page_size;
2396 /* Flash in Default addressing mode */
2397 nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
2404 spi_nor_set_read_settings(struct spi_nor_read_command *read,
2408 enum spi_nor_protocol proto)
2410 read->num_mode_clocks = num_mode_clocks;
2411 read->num_wait_states = num_wait_states;
2412 read->opcode = opcode;
2413 read->proto = proto;
2417 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
2419 enum spi_nor_protocol proto)
2421 pp->opcode = opcode;
2425 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2429 for (i = 0; i < size; i++)
2430 if (table[i][0] == (int)hwcaps)
2436 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2438 static const int hwcaps_read2cmd[][2] = {
2439 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2440 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2441 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2442 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2443 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2444 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2445 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2446 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2447 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2448 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2449 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2450 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2451 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2452 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2453 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2456 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2457 ARRAY_SIZE(hwcaps_read2cmd));
2460 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2462 static const int hwcaps_pp2cmd[][2] = {
2463 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2464 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2465 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2466 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2467 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2468 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2469 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2472 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2473 ARRAY_SIZE(hwcaps_pp2cmd));
2477 * Serial Flash Discoverable Parameters (SFDP) parsing.
2481 * spi_nor_read_raw() - raw read of serial flash memory. read_opcode,
2482 * addr_width and read_dummy members of the struct spi_nor
2483 * should be previously
2485 * @nor: pointer to a 'struct spi_nor'
2486 * @addr: offset in the serial flash memory
2487 * @len: number of bytes to read
2488 * @buf: buffer where the data is copied into (dma-safe memory)
2490 * Return: 0 on success, -errno otherwise.
2492 static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf)
2497 ret = nor->read(nor, addr, len, buf);
2498 if (!ret || ret > len)
2511 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
2512 * @nor: pointer to a 'struct spi_nor'
2513 * @addr: offset in the SFDP area to start reading data from
2514 * @len: number of bytes to read
2515 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
2517 * Whatever the actual numbers of bytes for address and dummy cycles are
2518 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
2519 * followed by a 3-byte address and 8 dummy clock cycles.
2521 * Return: 0 on success, -errno otherwise.
2523 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
2524 size_t len, void *buf)
2526 u8 addr_width, read_opcode, read_dummy;
2529 read_opcode = nor->read_opcode;
2530 addr_width = nor->addr_width;
2531 read_dummy = nor->read_dummy;
2533 nor->read_opcode = SPINOR_OP_RDSFDP;
2534 nor->addr_width = 3;
2535 nor->read_dummy = 8;
2537 ret = spi_nor_read_raw(nor, addr, len, buf);
2539 nor->read_opcode = read_opcode;
2540 nor->addr_width = addr_width;
2541 nor->read_dummy = read_dummy;
2547 * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
2548 * @nor: pointer to a 'struct spi_nor'
2549 * @addr: offset in the SFDP area to start reading data from
2550 * @len: number of bytes to read
2551 * @buf: buffer where the SFDP data are copied into
2553 * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
2554 * guaranteed to be dma-safe.
2556 * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
2559 static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
2560 size_t len, void *buf)
2565 dma_safe_buf = kmalloc(len, GFP_KERNEL);
2569 ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
2570 memcpy(buf, dma_safe_buf, len);
2571 kfree(dma_safe_buf);
2576 /* Fast Read settings. */
2579 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
2581 enum spi_nor_protocol proto)
2583 read->num_mode_clocks = (half >> 5) & 0x07;
2584 read->num_wait_states = (half >> 0) & 0x1f;
2585 read->opcode = (half >> 8) & 0xff;
2586 read->proto = proto;
2589 struct sfdp_bfpt_read {
2590 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
2594 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
2595 * whether the Fast Read x-y-z command is supported.
2597 u32 supported_dword;
2601 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
2602 * encodes the op code, the number of mode clocks and the number of wait
2603 * states to be used by Fast Read x-y-z command.
2608 /* The SPI protocol for this Fast Read x-y-z command. */
2609 enum spi_nor_protocol proto;
2612 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
2613 /* Fast Read 1-1-2 */
2615 SNOR_HWCAPS_READ_1_1_2,
2616 BFPT_DWORD(1), BIT(16), /* Supported bit */
2617 BFPT_DWORD(4), 0, /* Settings */
2621 /* Fast Read 1-2-2 */
2623 SNOR_HWCAPS_READ_1_2_2,
2624 BFPT_DWORD(1), BIT(20), /* Supported bit */
2625 BFPT_DWORD(4), 16, /* Settings */
2629 /* Fast Read 2-2-2 */
2631 SNOR_HWCAPS_READ_2_2_2,
2632 BFPT_DWORD(5), BIT(0), /* Supported bit */
2633 BFPT_DWORD(6), 16, /* Settings */
2637 /* Fast Read 1-1-4 */
2639 SNOR_HWCAPS_READ_1_1_4,
2640 BFPT_DWORD(1), BIT(22), /* Supported bit */
2641 BFPT_DWORD(3), 16, /* Settings */
2645 /* Fast Read 1-4-4 */
2647 SNOR_HWCAPS_READ_1_4_4,
2648 BFPT_DWORD(1), BIT(21), /* Supported bit */
2649 BFPT_DWORD(3), 0, /* Settings */
2653 /* Fast Read 4-4-4 */
2655 SNOR_HWCAPS_READ_4_4_4,
2656 BFPT_DWORD(5), BIT(4), /* Supported bit */
2657 BFPT_DWORD(7), 16, /* Settings */
2662 struct sfdp_bfpt_erase {
2664 * The half-word at offset <shift> in DWORD <dwoard> encodes the
2665 * op code and erase sector size to be used by Sector Erase commands.
2671 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
2672 /* Erase Type 1 in DWORD8 bits[15:0] */
2675 /* Erase Type 2 in DWORD8 bits[31:16] */
2676 {BFPT_DWORD(8), 16},
2678 /* Erase Type 3 in DWORD9 bits[15:0] */
2681 /* Erase Type 4 in DWORD9 bits[31:16] */
2682 {BFPT_DWORD(9), 16},
2686 * spi_nor_set_erase_type() - set a SPI NOR erase type
2687 * @erase: pointer to a structure that describes a SPI NOR erase type
2688 * @size: the size of the sector/block erased by the erase type
2689 * @opcode: the SPI command op code to erase the sector/block
2691 static void spi_nor_set_erase_type(struct spi_nor_erase_type *erase,
2692 u32 size, u8 opcode)
2695 erase->opcode = opcode;
2696 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2697 erase->size_shift = ffs(erase->size) - 1;
2698 erase->size_mask = (1 << erase->size_shift) - 1;
2702 * spi_nor_set_erase_settings_from_bfpt() - set erase type settings from BFPT
2703 * @erase: pointer to a structure that describes a SPI NOR erase type
2704 * @size: the size of the sector/block erased by the erase type
2705 * @opcode: the SPI command op code to erase the sector/block
2706 * @i: erase type index as sorted in the Basic Flash Parameter Table
2708 * The supported Erase Types will be sorted at init in ascending order, with
2709 * the smallest Erase Type size being the first member in the erase_type array
2710 * of the spi_nor_erase_map structure. Save the Erase Type index as sorted in
2711 * the Basic Flash Parameter Table since it will be used later on to
2712 * synchronize with the supported Erase Types defined in SFDP optional tables.
2715 spi_nor_set_erase_settings_from_bfpt(struct spi_nor_erase_type *erase,
2716 u32 size, u8 opcode, u8 i)
2719 spi_nor_set_erase_type(erase, size, opcode);
2723 * spi_nor_map_cmp_erase_type() - compare the map's erase types by size
2724 * @l: member in the left half of the map's erase_type array
2725 * @r: member in the right half of the map's erase_type array
2727 * Comparison function used in the sort() call to sort in ascending order the
2728 * map's erase types, the smallest erase type size being the first member in the
2729 * sorted erase_type array.
2731 * Return: the result of @l->size - @r->size
2733 static int spi_nor_map_cmp_erase_type(const void *l, const void *r)
2735 const struct spi_nor_erase_type *left = l, *right = r;
2737 return left->size - right->size;
2741 * spi_nor_sort_erase_mask() - sort erase mask
2742 * @map: the erase map of the SPI NOR
2743 * @erase_mask: the erase type mask to be sorted
2745 * Replicate the sort done for the map's erase types in BFPT: sort the erase
2746 * mask in ascending order with the smallest erase type size starting from
2747 * BIT(0) in the sorted erase mask.
2749 * Return: sorted erase mask.
2751 static u8 spi_nor_sort_erase_mask(struct spi_nor_erase_map *map, u8 erase_mask)
2753 struct spi_nor_erase_type *erase_type = map->erase_type;
2755 u8 sorted_erase_mask = 0;
2760 /* Replicate the sort done for the map's erase types. */
2761 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
2762 if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx))
2763 sorted_erase_mask |= BIT(i);
2765 return sorted_erase_mask;
2769 * spi_nor_regions_sort_erase_types() - sort erase types in each region
2770 * @map: the erase map of the SPI NOR
2772 * Function assumes that the erase types defined in the erase map are already
2773 * sorted in ascending order, with the smallest erase type size being the first
2774 * member in the erase_type array. It replicates the sort done for the map's
2775 * erase types. Each region's erase bitmask will indicate which erase types are
2776 * supported from the sorted erase types defined in the erase map.
2777 * Sort the all region's erase type at init in order to speed up the process of
2778 * finding the best erase command at runtime.
2780 static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map)
2782 struct spi_nor_erase_region *region = map->regions;
2783 u8 region_erase_mask, sorted_erase_mask;
2786 region_erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
2788 sorted_erase_mask = spi_nor_sort_erase_mask(map,
2791 /* Overwrite erase mask. */
2792 region->offset = (region->offset & ~SNOR_ERASE_TYPE_MASK) |
2795 region = spi_nor_region_next(region);
2800 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2801 * @map: the erase map of the SPI NOR
2802 * @erase_mask: bitmask encoding erase types that can erase the entire
2804 * @flash_size: the spi nor flash memory size
2806 static void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2807 u8 erase_mask, u64 flash_size)
2809 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2810 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2812 map->uniform_region.size = flash_size;
2813 map->regions = &map->uniform_region;
2814 map->uniform_erase_type = erase_mask;
2818 spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2819 const struct sfdp_parameter_header *bfpt_header,
2820 const struct sfdp_bfpt *bfpt,
2821 struct spi_nor_flash_parameter *params)
2823 if (nor->info->fixups && nor->info->fixups->post_bfpt)
2824 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
2831 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
2832 * @nor: pointer to a 'struct spi_nor'
2833 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
2834 * the Basic Flash Parameter Table length and version
2835 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2838 * The Basic Flash Parameter Table is the main and only mandatory table as
2839 * defined by the SFDP (JESD216) specification.
2840 * It provides us with the total size (memory density) of the data array and
2841 * the number of address bytes for Fast Read, Page Program and Sector Erase
2843 * For Fast READ commands, it also gives the number of mode clock cycles and
2844 * wait states (regrouped in the number of dummy clock cycles) for each
2845 * supported instruction op code.
2846 * For Page Program, the page size is now available since JESD216 rev A, however
2847 * the supported instruction op codes are still not provided.
2848 * For Sector Erase commands, this table stores the supported instruction op
2849 * codes and the associated sector sizes.
2850 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
2851 * rev A. The QER bits encode the manufacturer dependent procedure to be
2852 * executed to set the Quad Enable (QE) bit in some internal register of the
2853 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
2854 * sending any Quad SPI command to the memory. Actually, setting the QE bit
2855 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
2856 * and IO3 hence enabling 4 (Quad) I/O lines.
2858 * Return: 0 on success, -errno otherwise.
2860 static int spi_nor_parse_bfpt(struct spi_nor *nor,
2861 const struct sfdp_parameter_header *bfpt_header,
2862 struct spi_nor_flash_parameter *params)
2864 struct spi_nor_erase_map *map = &nor->erase_map;
2865 struct spi_nor_erase_type *erase_type = map->erase_type;
2866 struct sfdp_bfpt bfpt;
2873 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
2874 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
2877 /* Read the Basic Flash Parameter Table. */
2878 len = min_t(size_t, sizeof(bfpt),
2879 bfpt_header->length * sizeof(u32));
2880 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2881 memset(&bfpt, 0, sizeof(bfpt));
2882 err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
2886 /* Fix endianness of the BFPT DWORDs. */
2887 for (i = 0; i < BFPT_DWORD_MAX; i++)
2888 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
2890 /* Number of address bytes. */
2891 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
2892 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
2893 nor->addr_width = 3;
2896 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
2897 nor->addr_width = 4;
2904 /* Flash Memory Density (in bits). */
2905 params->size = bfpt.dwords[BFPT_DWORD(2)];
2906 if (params->size & BIT(31)) {
2907 params->size &= ~BIT(31);
2910 * Prevent overflows on params->size. Anyway, a NOR of 2^64
2911 * bits is unlikely to exist so this error probably means
2912 * the BFPT we are reading is corrupted/wrong.
2914 if (params->size > 63)
2917 params->size = 1ULL << params->size;
2921 params->size >>= 3; /* Convert to bytes. */
2923 /* Fast Read settings. */
2924 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
2925 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
2926 struct spi_nor_read_command *read;
2928 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
2929 params->hwcaps.mask &= ~rd->hwcaps;
2933 params->hwcaps.mask |= rd->hwcaps;
2934 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
2935 read = ¶ms->reads[cmd];
2936 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
2937 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
2941 * Sector Erase settings. Reinitialize the uniform erase map using the
2942 * Erase Types defined in the bfpt table.
2945 memset(&nor->erase_map, 0, sizeof(nor->erase_map));
2946 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
2947 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
2951 half = bfpt.dwords[er->dword] >> er->shift;
2952 erasesize = half & 0xff;
2954 /* erasesize == 0 means this Erase Type is not supported. */
2958 erasesize = 1U << erasesize;
2959 opcode = (half >> 8) & 0xff;
2960 erase_mask |= BIT(i);
2961 spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
2964 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2966 * Sort all the map's Erase Types in ascending order with the smallest
2967 * erase size being the first member in the erase_type array.
2969 sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]),
2970 spi_nor_map_cmp_erase_type, NULL);
2972 * Sort the erase types in the uniform region in order to update the
2973 * uniform_erase_type bitmask. The bitmask will be used later on when
2974 * selecting the uniform erase.
2976 spi_nor_regions_sort_erase_types(map);
2977 map->uniform_erase_type = map->uniform_region.offset &
2978 SNOR_ERASE_TYPE_MASK;
2980 /* Stop here if not JESD216 rev A or later. */
2981 if (bfpt_header->length < BFPT_DWORD_MAX)
2982 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2985 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2986 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2987 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2988 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2989 params->page_size = 1U << params->page_size;
2991 /* Quad Enable Requirements. */
2992 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2993 case BFPT_DWORD15_QER_NONE:
2994 params->quad_enable = NULL;
2997 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2998 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2999 params->quad_enable = spansion_no_read_cr_quad_enable;
3002 case BFPT_DWORD15_QER_SR1_BIT6:
3003 params->quad_enable = macronix_quad_enable;
3006 case BFPT_DWORD15_QER_SR2_BIT7:
3007 params->quad_enable = sr2_bit7_quad_enable;
3010 case BFPT_DWORD15_QER_SR2_BIT1:
3011 params->quad_enable = spansion_read_cr_quad_enable;
3018 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
3021 #define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
3022 #define SMPT_CMD_ADDRESS_LEN_0 (0x0UL << 22)
3023 #define SMPT_CMD_ADDRESS_LEN_3 (0x1UL << 22)
3024 #define SMPT_CMD_ADDRESS_LEN_4 (0x2UL << 22)
3025 #define SMPT_CMD_ADDRESS_LEN_USE_CURRENT (0x3UL << 22)
3027 #define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16)
3028 #define SMPT_CMD_READ_DUMMY_SHIFT 16
3029 #define SMPT_CMD_READ_DUMMY(_cmd) \
3030 (((_cmd) & SMPT_CMD_READ_DUMMY_MASK) >> SMPT_CMD_READ_DUMMY_SHIFT)
3031 #define SMPT_CMD_READ_DUMMY_IS_VARIABLE 0xfUL
3033 #define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24)
3034 #define SMPT_CMD_READ_DATA_SHIFT 24
3035 #define SMPT_CMD_READ_DATA(_cmd) \
3036 (((_cmd) & SMPT_CMD_READ_DATA_MASK) >> SMPT_CMD_READ_DATA_SHIFT)
3038 #define SMPT_CMD_OPCODE_MASK GENMASK(15, 8)
3039 #define SMPT_CMD_OPCODE_SHIFT 8
3040 #define SMPT_CMD_OPCODE(_cmd) \
3041 (((_cmd) & SMPT_CMD_OPCODE_MASK) >> SMPT_CMD_OPCODE_SHIFT)
3043 #define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16)
3044 #define SMPT_MAP_REGION_COUNT_SHIFT 16
3045 #define SMPT_MAP_REGION_COUNT(_header) \
3046 ((((_header) & SMPT_MAP_REGION_COUNT_MASK) >> \
3047 SMPT_MAP_REGION_COUNT_SHIFT) + 1)
3049 #define SMPT_MAP_ID_MASK GENMASK(15, 8)
3050 #define SMPT_MAP_ID_SHIFT 8
3051 #define SMPT_MAP_ID(_header) \
3052 (((_header) & SMPT_MAP_ID_MASK) >> SMPT_MAP_ID_SHIFT)
3054 #define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8)
3055 #define SMPT_MAP_REGION_SIZE_SHIFT 8
3056 #define SMPT_MAP_REGION_SIZE(_region) \
3057 (((((_region) & SMPT_MAP_REGION_SIZE_MASK) >> \
3058 SMPT_MAP_REGION_SIZE_SHIFT) + 1) * 256)
3060 #define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0)
3061 #define SMPT_MAP_REGION_ERASE_TYPE(_region) \
3062 ((_region) & SMPT_MAP_REGION_ERASE_TYPE_MASK)
3064 #define SMPT_DESC_TYPE_MAP BIT(1)
3065 #define SMPT_DESC_END BIT(0)
3068 * spi_nor_smpt_addr_width() - return the address width used in the
3069 * configuration detection command.
3070 * @nor: pointer to a 'struct spi_nor'
3071 * @settings: configuration detection command descriptor, dword1
3073 static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings)
3075 switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) {
3076 case SMPT_CMD_ADDRESS_LEN_0:
3078 case SMPT_CMD_ADDRESS_LEN_3:
3080 case SMPT_CMD_ADDRESS_LEN_4:
3082 case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
3085 return nor->addr_width;
3090 * spi_nor_smpt_read_dummy() - return the configuration detection command read
3091 * latency, in clock cycles.
3092 * @nor: pointer to a 'struct spi_nor'
3093 * @settings: configuration detection command descriptor, dword1
3095 * Return: the number of dummy cycles for an SMPT read
3097 static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
3099 u8 read_dummy = SMPT_CMD_READ_DUMMY(settings);
3101 if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE)
3102 return nor->read_dummy;
3107 * spi_nor_get_map_in_use() - get the configuration map in use
3108 * @nor: pointer to a 'struct spi_nor'
3109 * @smpt: pointer to the sector map parameter table
3110 * @smpt_len: sector map parameter table length
3112 * Return: pointer to the map in use, ERR_PTR(-errno) otherwise.
3114 static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
3122 u8 addr_width, read_opcode, read_dummy;
3123 u8 read_data_mask, map_id;
3125 /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
3126 buf = kmalloc(sizeof(*buf), GFP_KERNEL);
3128 return ERR_PTR(-ENOMEM);
3130 addr_width = nor->addr_width;
3131 read_dummy = nor->read_dummy;
3132 read_opcode = nor->read_opcode;
3135 /* Determine if there are any optional Detection Command Descriptors */
3136 for (i = 0; i < smpt_len; i += 2) {
3137 if (smpt[i] & SMPT_DESC_TYPE_MAP)
3140 read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
3141 nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
3142 nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
3143 nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
3146 err = spi_nor_read_raw(nor, addr, 1, buf);
3153 * Build an index value that is used to select the Sector Map
3154 * Configuration that is currently in use.
3156 map_id = map_id << 1 | !!(*buf & read_data_mask);
3160 * If command descriptors are provided, they always precede map
3161 * descriptors in the table. There is no need to start the iteration
3162 * over smpt array all over again.
3164 * Find the matching configuration map.
3166 ret = ERR_PTR(-EINVAL);
3167 while (i < smpt_len) {
3168 if (SMPT_MAP_ID(smpt[i]) == map_id) {
3174 * If there are no more configuration map descriptors and no
3175 * configuration ID matched the configuration identifier, the
3176 * sector address map is unknown.
3178 if (smpt[i] & SMPT_DESC_END)
3181 /* increment the table index to the next map */
3182 i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1;
3188 nor->addr_width = addr_width;
3189 nor->read_dummy = read_dummy;
3190 nor->read_opcode = read_opcode;
3195 * spi_nor_region_check_overlay() - set overlay bit when the region is overlaid
3196 * @region: pointer to a structure that describes a SPI NOR erase region
3197 * @erase: pointer to a structure that describes a SPI NOR erase type
3198 * @erase_type: erase type bitmask
3201 spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
3202 const struct spi_nor_erase_type *erase,
3203 const u8 erase_type)
3207 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
3208 if (!(erase_type & BIT(i)))
3210 if (region->size & erase[i].size_mask) {
3211 spi_nor_region_mark_overlay(region);
3218 * spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map
3219 * @nor: pointer to a 'struct spi_nor'
3220 * @smpt: pointer to the sector map parameter table
3222 * Return: 0 on success, -errno otherwise.
3224 static int spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
3227 struct spi_nor_erase_map *map = &nor->erase_map;
3228 struct spi_nor_erase_type *erase = map->erase_type;
3229 struct spi_nor_erase_region *region;
3233 u8 uniform_erase_type, save_uniform_erase_type;
3234 u8 erase_type, regions_erase_type;
3236 region_count = SMPT_MAP_REGION_COUNT(*smpt);
3238 * The regions will be freed when the driver detaches from the
3241 region = devm_kcalloc(nor->dev, region_count, sizeof(*region),
3245 map->regions = region;
3247 uniform_erase_type = 0xff;
3248 regions_erase_type = 0;
3250 /* Populate regions. */
3251 for (i = 0; i < region_count; i++) {
3252 j = i + 1; /* index for the region dword */
3253 region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]);
3254 erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]);
3255 region[i].offset = offset | erase_type;
3257 spi_nor_region_check_overlay(®ion[i], erase, erase_type);
3260 * Save the erase types that are supported in all regions and
3261 * can erase the entire flash memory.
3263 uniform_erase_type &= erase_type;
3266 * regions_erase_type mask will indicate all the erase types
3267 * supported in this configuration map.
3269 regions_erase_type |= erase_type;
3271 offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) +
3275 save_uniform_erase_type = map->uniform_erase_type;
3276 map->uniform_erase_type = spi_nor_sort_erase_mask(map,
3277 uniform_erase_type);
3279 if (!regions_erase_type) {
3281 * Roll back to the previous uniform_erase_type mask, SMPT is
3284 map->uniform_erase_type = save_uniform_erase_type;
3289 * BFPT advertises all the erase types supported by all the possible
3290 * map configurations. Mask out the erase types that are not supported
3291 * by the current map configuration.
3293 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
3294 if (!(regions_erase_type & BIT(erase[i].idx)))
3295 spi_nor_set_erase_type(&erase[i], 0, 0xFF);
3297 spi_nor_region_mark_end(®ion[i - 1]);
3303 * spi_nor_parse_smpt() - parse Sector Map Parameter Table
3304 * @nor: pointer to a 'struct spi_nor'
3305 * @smpt_header: sector map parameter table header
3307 * This table is optional, but when available, we parse it to identify the
3308 * location and size of sectors within the main data array of the flash memory
3309 * device and to identify which Erase Types are supported by each sector.
3311 * Return: 0 on success, -errno otherwise.
3313 static int spi_nor_parse_smpt(struct spi_nor *nor,
3314 const struct sfdp_parameter_header *smpt_header)
3316 const u32 *sector_map;
3322 /* Read the Sector Map Parameter Table. */
3323 len = smpt_header->length * sizeof(*smpt);
3324 smpt = kmalloc(len, GFP_KERNEL);
3328 addr = SFDP_PARAM_HEADER_PTP(smpt_header);
3329 ret = spi_nor_read_sfdp(nor, addr, len, smpt);
3333 /* Fix endianness of the SMPT DWORDs. */
3334 for (i = 0; i < smpt_header->length; i++)
3335 smpt[i] = le32_to_cpu(smpt[i]);
3337 sector_map = spi_nor_get_map_in_use(nor, smpt, smpt_header->length);
3338 if (IS_ERR(sector_map)) {
3339 ret = PTR_ERR(sector_map);
3343 ret = spi_nor_init_non_uniform_erase_map(nor, sector_map);
3347 spi_nor_regions_sort_erase_types(&nor->erase_map);
3354 #define SFDP_4BAIT_DWORD_MAX 2
3357 /* The hardware capability. */
3361 * The <supported_bit> bit in DWORD1 of the 4BAIT tells us whether
3362 * the associated 4-byte address op code is supported.
3368 * spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table
3369 * @nor: pointer to a 'struct spi_nor'.
3370 * @param_header: pointer to the 'struct sfdp_parameter_header' describing
3371 * the 4-Byte Address Instruction Table length and version.
3372 * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
3374 * Return: 0 on success, -errno otherwise.
3376 static int spi_nor_parse_4bait(struct spi_nor *nor,
3377 const struct sfdp_parameter_header *param_header,
3378 struct spi_nor_flash_parameter *params)
3380 static const struct sfdp_4bait reads[] = {
3381 { SNOR_HWCAPS_READ, BIT(0) },
3382 { SNOR_HWCAPS_READ_FAST, BIT(1) },
3383 { SNOR_HWCAPS_READ_1_1_2, BIT(2) },
3384 { SNOR_HWCAPS_READ_1_2_2, BIT(3) },
3385 { SNOR_HWCAPS_READ_1_1_4, BIT(4) },
3386 { SNOR_HWCAPS_READ_1_4_4, BIT(5) },
3387 { SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) },
3388 { SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) },
3389 { SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) },
3391 static const struct sfdp_4bait programs[] = {
3392 { SNOR_HWCAPS_PP, BIT(6) },
3393 { SNOR_HWCAPS_PP_1_1_4, BIT(7) },
3394 { SNOR_HWCAPS_PP_1_4_4, BIT(8) },
3396 static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = {
3397 { 0u /* not used */, BIT(9) },
3398 { 0u /* not used */, BIT(10) },
3399 { 0u /* not used */, BIT(11) },
3400 { 0u /* not used */, BIT(12) },
3402 struct spi_nor_pp_command *params_pp = params->page_programs;
3403 struct spi_nor_erase_map *map = &nor->erase_map;
3404 struct spi_nor_erase_type *erase_type = map->erase_type;
3407 u32 addr, discard_hwcaps, read_hwcaps, pp_hwcaps, erase_mask;
3410 if (param_header->major != SFDP_JESD216_MAJOR ||
3411 param_header->length < SFDP_4BAIT_DWORD_MAX)
3414 /* Read the 4-byte Address Instruction Table. */
3415 len = sizeof(*dwords) * SFDP_4BAIT_DWORD_MAX;
3417 /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
3418 dwords = kmalloc(len, GFP_KERNEL);
3422 addr = SFDP_PARAM_HEADER_PTP(param_header);
3423 ret = spi_nor_read_sfdp(nor, addr, len, dwords);
3427 /* Fix endianness of the 4BAIT DWORDs. */
3428 for (i = 0; i < SFDP_4BAIT_DWORD_MAX; i++)
3429 dwords[i] = le32_to_cpu(dwords[i]);
3432 * Compute the subset of (Fast) Read commands for which the 4-byte
3433 * version is supported.
3437 for (i = 0; i < ARRAY_SIZE(reads); i++) {
3438 const struct sfdp_4bait *read = &reads[i];
3440 discard_hwcaps |= read->hwcaps;
3441 if ((params->hwcaps.mask & read->hwcaps) &&
3442 (dwords[0] & read->supported_bit))
3443 read_hwcaps |= read->hwcaps;
3447 * Compute the subset of Page Program commands for which the 4-byte
3448 * version is supported.
3451 for (i = 0; i < ARRAY_SIZE(programs); i++) {
3452 const struct sfdp_4bait *program = &programs[i];
3455 * The 4 Byte Address Instruction (Optional) Table is the only
3456 * SFDP table that indicates support for Page Program Commands.
3457 * Bypass the params->hwcaps.mask and consider 4BAIT the biggest
3458 * authority for specifying Page Program support.
3460 discard_hwcaps |= program->hwcaps;
3461 if (dwords[0] & program->supported_bit)
3462 pp_hwcaps |= program->hwcaps;
3466 * Compute the subset of Sector Erase commands for which the 4-byte
3467 * version is supported.
3470 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
3471 const struct sfdp_4bait *erase = &erases[i];
3473 if (dwords[0] & erase->supported_bit)
3474 erase_mask |= BIT(i);
3477 /* Replicate the sort done for the map's erase types in BFPT. */
3478 erase_mask = spi_nor_sort_erase_mask(map, erase_mask);
3481 * We need at least one 4-byte op code per read, program and erase
3482 * operation; the .read(), .write() and .erase() hooks share the
3483 * nor->addr_width value.
3485 if (!read_hwcaps || !pp_hwcaps || !erase_mask)
3489 * Discard all operations from the 4-byte instruction set which are
3490 * not supported by this memory.
3492 params->hwcaps.mask &= ~discard_hwcaps;
3493 params->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
3495 /* Use the 4-byte address instruction set. */
3496 for (i = 0; i < SNOR_CMD_READ_MAX; i++) {
3497 struct spi_nor_read_command *read_cmd = ¶ms->reads[i];
3499 read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode);
3502 /* 4BAIT is the only SFDP table that indicates page program support. */
3503 if (pp_hwcaps & SNOR_HWCAPS_PP)
3504 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP],
3505 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
3506 if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4)
3507 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_4],
3508 SPINOR_OP_PP_1_1_4_4B,
3510 if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4)
3511 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_4_4],
3512 SPINOR_OP_PP_1_4_4_4B,
3515 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
3516 if (erase_mask & BIT(i))
3517 erase_type[i].opcode = (dwords[1] >>
3518 erase_type[i].idx * 8) & 0xFF;
3520 spi_nor_set_erase_type(&erase_type[i], 0u, 0xFF);
3524 * We set SNOR_F_HAS_4BAIT in order to skip spi_nor_set_4byte_opcodes()
3525 * later because we already did the conversion to 4byte opcodes. Also,
3526 * this latest function implements a legacy quirk for the erase size of
3527 * Spansion memory. However this quirk is no longer needed with new
3528 * SFDP compliant memories.
3530 nor->addr_width = 4;
3531 nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT;
3540 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
3541 * @nor: pointer to a 'struct spi_nor'
3542 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
3545 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
3546 * specification. This is a standard which tends to supported by almost all
3547 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
3548 * runtime the main parameters needed to perform basic SPI flash operations such
3549 * as Fast Read, Page Program or Sector Erase commands.
3551 * Return: 0 on success, -errno otherwise.
3553 static int spi_nor_parse_sfdp(struct spi_nor *nor,
3554 struct spi_nor_flash_parameter *params)
3556 const struct sfdp_parameter_header *param_header, *bfpt_header;
3557 struct sfdp_parameter_header *param_headers = NULL;
3558 struct sfdp_header header;
3559 struct device *dev = nor->dev;
3563 /* Get the SFDP header. */
3564 err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
3568 /* Check the SFDP header version. */
3569 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
3570 header.major != SFDP_JESD216_MAJOR)
3574 * Verify that the first and only mandatory parameter header is a
3575 * Basic Flash Parameter Table header as specified in JESD216.
3577 bfpt_header = &header.bfpt_header;
3578 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
3579 bfpt_header->major != SFDP_JESD216_MAJOR)
3583 * Allocate memory then read all parameter headers with a single
3584 * Read SFDP command. These parameter headers will actually be parsed
3585 * twice: a first time to get the latest revision of the basic flash
3586 * parameter table, then a second time to handle the supported optional
3588 * Hence we read the parameter headers once for all to reduce the
3589 * processing time. Also we use kmalloc() instead of devm_kmalloc()
3590 * because we don't need to keep these parameter headers: the allocated
3591 * memory is always released with kfree() before exiting this function.
3594 psize = header.nph * sizeof(*param_headers);
3596 param_headers = kmalloc(psize, GFP_KERNEL);
3600 err = spi_nor_read_sfdp(nor, sizeof(header),
3601 psize, param_headers);
3603 dev_err(dev, "failed to read SFDP parameter headers\n");
3609 * Check other parameter headers to get the latest revision of
3610 * the basic flash parameter table.
3612 for (i = 0; i < header.nph; i++) {
3613 param_header = ¶m_headers[i];
3615 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
3616 param_header->major == SFDP_JESD216_MAJOR &&
3617 (param_header->minor > bfpt_header->minor ||
3618 (param_header->minor == bfpt_header->minor &&
3619 param_header->length > bfpt_header->length)))
3620 bfpt_header = param_header;
3623 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
3627 /* Parse optional parameter tables. */
3628 for (i = 0; i < header.nph; i++) {
3629 param_header = ¶m_headers[i];
3631 switch (SFDP_PARAM_HEADER_ID(param_header)) {
3632 case SFDP_SECTOR_MAP_ID:
3633 err = spi_nor_parse_smpt(nor, param_header);
3637 err = spi_nor_parse_4bait(nor, param_header, params);
3645 dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
3646 SFDP_PARAM_HEADER_ID(param_header));
3648 * Let's not drop all information we extracted so far
3649 * if optional table parsers fail. In case of failing,
3650 * each optional parser is responsible to roll back to
3651 * the previously known spi_nor data.
3658 kfree(param_headers);
3662 static int spi_nor_init_params(struct spi_nor *nor,
3663 struct spi_nor_flash_parameter *params)
3665 struct spi_nor_erase_map *map = &nor->erase_map;
3666 const struct flash_info *info = nor->info;
3669 /* Set legacy flash parameters as default. */
3670 memset(params, 0, sizeof(*params));
3672 /* Set SPI NOR sizes. */
3673 params->size = (u64)info->sector_size * info->n_sectors;
3674 params->page_size = info->page_size;
3676 /* (Fast) Read settings. */
3677 params->hwcaps.mask |= SNOR_HWCAPS_READ;
3678 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
3679 0, 0, SPINOR_OP_READ,
3682 if (!(info->flags & SPI_NOR_NO_FR)) {
3683 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
3684 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
3685 0, 8, SPINOR_OP_READ_FAST,
3689 if (info->flags & SPI_NOR_DUAL_READ) {
3690 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
3691 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
3692 0, 8, SPINOR_OP_READ_1_1_2,
3696 if (info->flags & SPI_NOR_QUAD_READ) {
3697 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
3698 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
3699 0, 8, SPINOR_OP_READ_1_1_4,
3703 if (info->flags & SPI_NOR_OCTAL_READ) {
3704 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
3705 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
3706 0, 8, SPINOR_OP_READ_1_1_8,
3710 /* Page Program settings. */
3711 params->hwcaps.mask |= SNOR_HWCAPS_PP;
3712 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
3713 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
3716 * Sector Erase settings. Sort Erase Types in ascending order, with the
3717 * smallest erase size starting at BIT(0).
3721 if (info->flags & SECT_4K_PMC) {
3722 erase_mask |= BIT(i);
3723 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
3724 SPINOR_OP_BE_4K_PMC);
3726 } else if (info->flags & SECT_4K) {
3727 erase_mask |= BIT(i);
3728 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
3732 erase_mask |= BIT(i);
3733 spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
3735 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
3737 /* Select the procedure to set the Quad Enable bit. */
3738 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
3739 SNOR_HWCAPS_PP_QUAD)) {
3740 switch (JEDEC_MFR(info)) {
3741 case SNOR_MFR_MACRONIX:
3742 params->quad_enable = macronix_quad_enable;
3746 case SNOR_MFR_MICRON:
3750 /* Kept only for backward compatibility purpose. */
3751 params->quad_enable = spansion_quad_enable;
3752 if (nor->clear_sr_bp)
3753 nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
3758 * Some manufacturer like GigaDevice may use different
3759 * bit to set QE on different memories, so the MFR can't
3760 * indicate the quad_enable method for this case, we need
3761 * set it in flash info list.
3763 if (info->quad_enable)
3764 params->quad_enable = info->quad_enable;
3767 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
3768 !(info->flags & SPI_NOR_SKIP_SFDP)) {
3769 struct spi_nor_flash_parameter sfdp_params;
3770 struct spi_nor_erase_map prev_map;
3772 memcpy(&sfdp_params, params, sizeof(sfdp_params));
3773 memcpy(&prev_map, &nor->erase_map, sizeof(prev_map));
3775 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
3776 nor->addr_width = 0;
3777 nor->flags &= ~SNOR_F_4B_OPCODES;
3778 /* restore previous erase map */
3779 memcpy(&nor->erase_map, &prev_map,
3780 sizeof(nor->erase_map));
3782 memcpy(params, &sfdp_params, sizeof(*params));
3789 static int spi_nor_select_read(struct spi_nor *nor,
3790 const struct spi_nor_flash_parameter *params,
3793 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
3794 const struct spi_nor_read_command *read;
3799 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
3803 read = ¶ms->reads[cmd];
3804 nor->read_opcode = read->opcode;
3805 nor->read_proto = read->proto;
3808 * In the spi-nor framework, we don't need to make the difference
3809 * between mode clock cycles and wait state clock cycles.
3810 * Indeed, the value of the mode clock cycles is used by a QSPI
3811 * flash memory to know whether it should enter or leave its 0-4-4
3812 * (Continuous Read / XIP) mode.
3813 * eXecution In Place is out of the scope of the mtd sub-system.
3814 * Hence we choose to merge both mode and wait state clock cycles
3815 * into the so called dummy clock cycles.
3817 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
3821 static int spi_nor_select_pp(struct spi_nor *nor,
3822 const struct spi_nor_flash_parameter *params,
3825 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
3826 const struct spi_nor_pp_command *pp;
3831 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
3835 pp = ¶ms->page_programs[cmd];
3836 nor->program_opcode = pp->opcode;
3837 nor->write_proto = pp->proto;
3842 * spi_nor_select_uniform_erase() - select optimum uniform erase type
3843 * @map: the erase map of the SPI NOR
3844 * @wanted_size: the erase type size to search for. Contains the value of
3845 * info->sector_size or of the "small sector" size in case
3846 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
3848 * Once the optimum uniform sector erase command is found, disable all the
3851 * Return: pointer to erase type on success, NULL otherwise.
3853 static const struct spi_nor_erase_type *
3854 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
3855 const u32 wanted_size)
3857 const struct spi_nor_erase_type *tested_erase, *erase = NULL;
3859 u8 uniform_erase_type = map->uniform_erase_type;
3861 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
3862 if (!(uniform_erase_type & BIT(i)))
3865 tested_erase = &map->erase_type[i];
3868 * If the current erase size is the one, stop here:
3869 * we have found the right uniform Sector Erase command.
3871 if (tested_erase->size == wanted_size) {
3872 erase = tested_erase;
3877 * Otherwise, the current erase size is still a valid canditate.
3878 * Select the biggest valid candidate.
3880 if (!erase && tested_erase->size)
3881 erase = tested_erase;
3882 /* keep iterating to find the wanted_size */
3888 /* Disable all other Sector Erase commands. */
3889 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
3890 map->uniform_erase_type |= BIT(erase - map->erase_type);
3894 static int spi_nor_select_erase(struct spi_nor *nor, u32 wanted_size)
3896 struct spi_nor_erase_map *map = &nor->erase_map;
3897 const struct spi_nor_erase_type *erase = NULL;
3898 struct mtd_info *mtd = &nor->mtd;
3902 * The previous implementation handling Sector Erase commands assumed
3903 * that the SPI flash memory has an uniform layout then used only one
3904 * of the supported erase sizes for all Sector Erase commands.
3905 * So to be backward compatible, the new implementation also tries to
3906 * manage the SPI flash memory as uniform with a single erase sector
3907 * size, when possible.
3909 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
3910 /* prefer "small sector" erase if possible */
3911 wanted_size = 4096u;
3914 if (spi_nor_has_uniform_erase(nor)) {
3915 erase = spi_nor_select_uniform_erase(map, wanted_size);
3918 nor->erase_opcode = erase->opcode;
3919 mtd->erasesize = erase->size;
3924 * For non-uniform SPI flash memory, set mtd->erasesize to the
3925 * maximum erase sector size. No need to set nor->erase_opcode.
3927 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
3928 if (map->erase_type[i].size) {
3929 erase = &map->erase_type[i];
3937 mtd->erasesize = erase->size;
3941 static int spi_nor_setup(struct spi_nor *nor,
3942 const struct spi_nor_flash_parameter *params,
3943 const struct spi_nor_hwcaps *hwcaps)
3945 u32 ignored_mask, shared_mask;
3946 bool enable_quad_io;
3950 * Keep only the hardware capabilities supported by both the SPI
3951 * controller and the SPI flash memory.
3953 shared_mask = hwcaps->mask & params->hwcaps.mask;
3955 /* SPI n-n-n protocols are not supported yet. */
3956 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
3957 SNOR_HWCAPS_READ_4_4_4 |
3958 SNOR_HWCAPS_READ_8_8_8 |
3959 SNOR_HWCAPS_PP_4_4_4 |
3960 SNOR_HWCAPS_PP_8_8_8);
3961 if (shared_mask & ignored_mask) {
3963 "SPI n-n-n protocols are not supported yet.\n");
3964 shared_mask &= ~ignored_mask;
3967 /* Select the (Fast) Read command. */
3968 err = spi_nor_select_read(nor, params, shared_mask);
3971 "can't select read settings supported by both the SPI controller and memory.\n");
3975 /* Select the Page Program command. */
3976 err = spi_nor_select_pp(nor, params, shared_mask);
3979 "can't select write settings supported by both the SPI controller and memory.\n");
3983 /* Select the Sector Erase command. */
3984 err = spi_nor_select_erase(nor, nor->info->sector_size);
3987 "can't select erase settings supported by both the SPI controller and memory.\n");
3991 /* Enable Quad I/O if needed. */
3992 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
3993 spi_nor_get_protocol_width(nor->write_proto) == 4);
3994 if (enable_quad_io && params->quad_enable)
3995 nor->quad_enable = params->quad_enable;
3997 nor->quad_enable = NULL;
4002 static int spi_nor_init(struct spi_nor *nor)
4006 if (nor->clear_sr_bp) {
4007 err = nor->clear_sr_bp(nor);
4010 "fail to clear block protection bits\n");
4015 if (nor->quad_enable) {
4016 err = nor->quad_enable(nor);
4018 dev_err(nor->dev, "quad mode not supported\n");
4023 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES)) {
4025 * If the RESET# pin isn't hooked up properly, or the system
4026 * otherwise doesn't perform a reset command in the boot
4027 * sequence, it's impossible to 100% protect against unexpected
4028 * reboots (e.g., crashes). Warn the user (or hopefully, system
4029 * designer) that this is bad.
4031 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
4032 "enabling reset hack; may not recover from unexpected reboots\n");
4033 set_4byte(nor, true);
4039 /* mtd resume handler */
4040 static void spi_nor_resume(struct mtd_info *mtd)
4042 struct spi_nor *nor = mtd_to_spi_nor(mtd);
4043 struct device *dev = nor->dev;
4046 /* re-initialize the nor chip */
4047 ret = spi_nor_init(nor);
4049 dev_err(dev, "resume() failed\n");
4052 void spi_nor_restore(struct spi_nor *nor)
4054 /* restore the addressing mode */
4055 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
4056 nor->flags & SNOR_F_BROKEN_RESET)
4057 set_4byte(nor, false);
4059 EXPORT_SYMBOL_GPL(spi_nor_restore);
4061 static const struct flash_info *spi_nor_match_id(const char *name)
4063 const struct flash_info *id = spi_nor_ids;
4066 if (!strcmp(name, id->name))
4073 int spi_nor_scan(struct spi_nor *nor, const char *name,
4074 const struct spi_nor_hwcaps *hwcaps)
4076 struct spi_nor_flash_parameter params;
4077 const struct flash_info *info = NULL;
4078 struct device *dev = nor->dev;
4079 struct mtd_info *mtd = &nor->mtd;
4080 struct device_node *np = spi_nor_get_flash_node(nor);
4084 ret = spi_nor_check(nor);
4088 /* Reset SPI protocol for all commands. */
4089 nor->reg_proto = SNOR_PROTO_1_1_1;
4090 nor->read_proto = SNOR_PROTO_1_1_1;
4091 nor->write_proto = SNOR_PROTO_1_1_1;
4094 info = spi_nor_match_id(name);
4095 /* Try to auto-detect if chip name wasn't specified or not found */
4097 info = spi_nor_read_id(nor);
4098 if (IS_ERR_OR_NULL(info))
4102 * If caller has specified name of flash model that can normally be
4103 * detected using JEDEC, let's verify it.
4105 if (name && info->id_len) {
4106 const struct flash_info *jinfo;
4108 jinfo = spi_nor_read_id(nor);
4109 if (IS_ERR(jinfo)) {
4110 return PTR_ERR(jinfo);
4111 } else if (jinfo != info) {
4113 * JEDEC knows better, so overwrite platform ID. We
4114 * can't trust partitions any longer, but we'll let
4115 * mtd apply them anyway, since some partitions may be
4116 * marked read-only, and we don't want to lose that
4117 * information, even if it's not 100% accurate.
4119 dev_warn(dev, "found %s, expected %s\n",
4120 jinfo->name, info->name);
4127 mutex_init(&nor->lock);
4130 * Make sure the XSR_RDY flag is set before calling
4131 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
4132 * with Atmel spi-nor
4134 if (info->flags & SPI_S3AN)
4135 nor->flags |= SNOR_F_READY_XSR_RDY;
4138 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
4139 * with the software protection bits set.
4141 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
4142 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
4143 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
4144 nor->info->flags & SPI_NOR_HAS_LOCK)
4145 nor->clear_sr_bp = spi_nor_clear_sr_bp;
4147 /* Parse the Serial Flash Discoverable Parameters table. */
4148 ret = spi_nor_init_params(nor, ¶ms);
4153 mtd->name = dev_name(dev);
4155 mtd->type = MTD_NORFLASH;
4157 mtd->flags = MTD_CAP_NORFLASH;
4158 mtd->size = params.size;
4159 mtd->_erase = spi_nor_erase;
4160 mtd->_read = spi_nor_read;
4161 mtd->_resume = spi_nor_resume;
4163 /* NOR protection support for STmicro/Micron chips and similar */
4164 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
4165 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
4166 info->flags & SPI_NOR_HAS_LOCK) {
4167 nor->flash_lock = stm_lock;
4168 nor->flash_unlock = stm_unlock;
4169 nor->flash_is_locked = stm_is_locked;
4172 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
4173 mtd->_lock = spi_nor_lock;
4174 mtd->_unlock = spi_nor_unlock;
4175 mtd->_is_locked = spi_nor_is_locked;
4178 /* sst nor chips use AAI word program */
4179 if (info->flags & SST_WRITE)
4180 mtd->_write = sst_write;
4182 mtd->_write = spi_nor_write;
4184 if (info->flags & USE_FSR)
4185 nor->flags |= SNOR_F_USE_FSR;
4186 if (info->flags & SPI_NOR_HAS_TB)
4187 nor->flags |= SNOR_F_HAS_SR_TB;
4188 if (info->flags & NO_CHIP_ERASE)
4189 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
4190 if (info->flags & USE_CLSR)
4191 nor->flags |= SNOR_F_USE_CLSR;
4193 if (info->flags & SPI_NOR_NO_ERASE)
4194 mtd->flags |= MTD_NO_ERASE;
4196 mtd->dev.parent = dev;
4197 nor->page_size = params.page_size;
4198 mtd->writebufsize = nor->page_size;
4201 /* If we were instantiated by DT, use it */
4202 if (of_property_read_bool(np, "m25p,fast-read"))
4203 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
4205 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
4207 /* If we weren't instantiated by DT, default to fast-read */
4208 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
4211 if (of_property_read_bool(np, "broken-flash-reset"))
4212 nor->flags |= SNOR_F_BROKEN_RESET;
4214 /* Some devices cannot do fast-read, no matter what DT tells us */
4215 if (info->flags & SPI_NOR_NO_FR)
4216 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
4219 * Configure the SPI memory:
4220 * - select op codes for (Fast) Read, Page Program and Sector Erase.
4221 * - set the number of dummy cycles (mode cycles + wait states).
4222 * - set the SPI protocols for register and memory accesses.
4223 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
4225 ret = spi_nor_setup(nor, ¶ms, hwcaps);
4229 if (nor->addr_width) {
4230 /* already configured from SFDP */
4231 } else if (info->addr_width) {
4232 nor->addr_width = info->addr_width;
4233 } else if (mtd->size > 0x1000000) {
4234 /* enable 4-byte addressing if the device exceeds 16MiB */
4235 nor->addr_width = 4;
4237 nor->addr_width = 3;
4240 if (info->flags & SPI_NOR_4B_OPCODES ||
4241 (JEDEC_MFR(info) == SNOR_MFR_SPANSION && mtd->size > SZ_16M))
4242 nor->flags |= SNOR_F_4B_OPCODES;
4244 if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
4245 !(nor->flags & SNOR_F_HAS_4BAIT))
4246 spi_nor_set_4byte_opcodes(nor);
4248 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
4249 dev_err(dev, "address width is too large: %u\n",
4254 if (info->flags & SPI_S3AN) {
4255 ret = s3an_nor_scan(nor);
4260 /* Send all the required SPI flash commands to initialize device */
4261 ret = spi_nor_init(nor);
4265 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
4266 (long long)mtd->size >> 10);
4269 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
4270 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
4271 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
4272 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
4274 if (mtd->numeraseregions)
4275 for (i = 0; i < mtd->numeraseregions; i++)
4277 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
4278 ".erasesize = 0x%.8x (%uKiB), "
4279 ".numblocks = %d }\n",
4280 i, (long long)mtd->eraseregions[i].offset,
4281 mtd->eraseregions[i].erasesize,
4282 mtd->eraseregions[i].erasesize / 1024,
4283 mtd->eraseregions[i].numblocks);
4286 EXPORT_SYMBOL_GPL(spi_nor_scan);
4288 MODULE_LICENSE("GPL v2");
4289 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
4290 MODULE_AUTHOR("Mike Lavender");
4291 MODULE_DESCRIPTION("framework for SPI NOR");