1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/mutex.h>
15 #include <linux/math64.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/of_platform.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/spi/flash.h>
23 #include <linux/mtd/spi-nor.h>
27 /* Define max times to check status register before we give up. */
30 * For everything but full-chip erase; probably could be much smaller, but kept
31 * around for safety for now
33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
41 #define SPI_NOR_MAX_ADDR_WIDTH 4
43 #define SPI_NOR_SRST_SLEEP_MIN 200
44 #define SPI_NOR_SRST_SLEEP_MAX 400
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
49 * @nor: pointer to a 'struct spi_nor'
50 * @op: pointer to the 'struct spi_mem_op' whose properties
51 * need to be initialized.
53 * Right now, only "repeat" and "invert" are supported.
55 * Return: The opcode extension.
57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
58 const struct spi_mem_op *op)
60 switch (nor->cmd_ext_type) {
61 case SPI_NOR_EXT_INVERT:
62 return ~op->cmd.opcode;
64 case SPI_NOR_EXT_REPEAT:
65 return op->cmd.opcode;
68 dev_err(nor->dev, "Unknown command extension type\n");
74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
75 * @nor: pointer to a 'struct spi_nor'
76 * @op: pointer to the 'struct spi_mem_op' whose properties
77 * need to be initialized.
78 * @proto: the protocol from which the properties need to be set.
80 void spi_nor_spimem_setup_op(const struct spi_nor *nor,
81 struct spi_mem_op *op,
82 const enum spi_nor_protocol proto)
86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
97 if (spi_nor_protocol_is_dtr(proto)) {
99 * SPIMEM supports mixed DTR modes, but right now we can only
100 * have all phases either DTR or STR. IOW, SPIMEM can have
101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4
102 * phases to either DTR or STR.
106 op->dummy.dtr = true;
109 /* 2 bytes per clock cycle in DTR mode. */
110 op->dummy.nbytes *= 2;
112 ext = spi_nor_get_cmd_ext(nor, op);
113 op->cmd.opcode = (op->cmd.opcode << 8) | ext;
119 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
121 * @nor: pointer to 'struct spi_nor'
122 * @op: pointer to 'struct spi_mem_op' template for transfer
124 * If we have to use the bounce buffer, the data field in @op will be updated.
126 * Return: true if the bounce buffer is needed, false if not
128 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)
130 /* op->data.buf.in occupies the same memory as op->data.buf.out */
131 if (object_is_on_stack(op->data.buf.in) ||
132 !virt_addr_valid(op->data.buf.in)) {
133 if (op->data.nbytes > nor->bouncebuf_size)
134 op->data.nbytes = nor->bouncebuf_size;
135 op->data.buf.in = nor->bouncebuf;
143 * spi_nor_spimem_exec_op() - execute a memory operation
144 * @nor: pointer to 'struct spi_nor'
145 * @op: pointer to 'struct spi_mem_op' template for transfer
147 * Return: 0 on success, -error otherwise.
149 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
153 error = spi_mem_adjust_op_size(nor->spimem, op);
157 return spi_mem_exec_op(nor->spimem, op);
160 int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
163 if (spi_nor_protocol_is_dtr(nor->reg_proto))
166 return nor->controller_ops->read_reg(nor, opcode, buf, len);
169 int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
170 const u8 *buf, size_t len)
172 if (spi_nor_protocol_is_dtr(nor->reg_proto))
175 return nor->controller_ops->write_reg(nor, opcode, buf, len);
178 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs)
180 if (spi_nor_protocol_is_dtr(nor->write_proto))
183 return nor->controller_ops->erase(nor, offs);
187 * spi_nor_spimem_read_data() - read data from flash's memory region via
189 * @nor: pointer to 'struct spi_nor'
190 * @from: offset to read from
191 * @len: number of bytes to read
192 * @buf: pointer to dst buffer
194 * Return: number of bytes read successfully, -errno otherwise
196 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
199 struct spi_mem_op op =
200 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
201 SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
202 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
203 SPI_MEM_OP_DATA_IN(len, buf, 0));
208 spi_nor_spimem_setup_op(nor, &op, nor->read_proto);
210 /* convert the dummy cycles to the number of bytes */
211 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
212 if (spi_nor_protocol_is_dtr(nor->read_proto))
213 op.dummy.nbytes *= 2;
215 usebouncebuf = spi_nor_spimem_bounce(nor, &op);
217 if (nor->dirmap.rdesc) {
218 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,
219 op.data.nbytes, op.data.buf.in);
221 error = spi_nor_spimem_exec_op(nor, &op);
224 nbytes = op.data.nbytes;
227 if (usebouncebuf && nbytes > 0)
228 memcpy(buf, op.data.buf.in, nbytes);
234 * spi_nor_read_data() - read data from flash memory
235 * @nor: pointer to 'struct spi_nor'
236 * @from: offset to read from
237 * @len: number of bytes to read
238 * @buf: pointer to dst buffer
240 * Return: number of bytes read successfully, -errno otherwise
242 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
245 return spi_nor_spimem_read_data(nor, from, len, buf);
247 return nor->controller_ops->read(nor, from, len, buf);
251 * spi_nor_spimem_write_data() - write data to flash memory via
253 * @nor: pointer to 'struct spi_nor'
254 * @to: offset to write to
255 * @len: number of bytes to write
256 * @buf: pointer to src buffer
258 * Return: number of bytes written successfully, -errno otherwise
260 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
261 size_t len, const u8 *buf)
263 struct spi_mem_op op =
264 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
265 SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
267 SPI_MEM_OP_DATA_OUT(len, buf, 0));
271 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
274 spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
276 if (spi_nor_spimem_bounce(nor, &op))
277 memcpy(nor->bouncebuf, buf, op.data.nbytes);
279 if (nor->dirmap.wdesc) {
280 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,
281 op.data.nbytes, op.data.buf.out);
283 error = spi_nor_spimem_exec_op(nor, &op);
286 nbytes = op.data.nbytes;
293 * spi_nor_write_data() - write data to flash memory
294 * @nor: pointer to 'struct spi_nor'
295 * @to: offset to write to
296 * @len: number of bytes to write
297 * @buf: pointer to src buffer
299 * Return: number of bytes written successfully, -errno otherwise
301 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
305 return spi_nor_spimem_write_data(nor, to, len, buf);
307 return nor->controller_ops->write(nor, to, len, buf);
311 * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or
313 * @nor: pointer to 'struct spi_nor'.
314 * @op: SPI memory operation. op->data.buf must be DMA-able.
315 * @proto: SPI protocol to use for the register operation.
317 * Return: zero on success, -errno otherwise
319 int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op,
320 enum spi_nor_protocol proto)
325 spi_nor_spimem_setup_op(nor, op, proto);
326 return spi_nor_spimem_exec_op(nor, op);
330 * spi_nor_write_any_volatile_reg() - write any volatile register to flash
332 * @nor: pointer to 'struct spi_nor'
333 * @op: SPI memory operation. op->data.buf must be DMA-able.
334 * @proto: SPI protocol to use for the register operation.
336 * Writing volatile registers are instant according to some manufacturers
337 * (Cypress, Micron) and do not need any status polling.
339 * Return: zero on success, -errno otherwise
341 int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op,
342 enum spi_nor_protocol proto)
349 ret = spi_nor_write_enable(nor);
352 spi_nor_spimem_setup_op(nor, op, proto);
353 return spi_nor_spimem_exec_op(nor, op);
357 * spi_nor_write_enable() - Set write enable latch with Write Enable command.
358 * @nor: pointer to 'struct spi_nor'.
360 * Return: 0 on success, -errno otherwise.
362 int spi_nor_write_enable(struct spi_nor *nor)
367 struct spi_mem_op op = SPI_NOR_WREN_OP;
369 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
371 ret = spi_mem_exec_op(nor->spimem, &op);
373 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN,
378 dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
384 * spi_nor_write_disable() - Send Write Disable instruction to the chip.
385 * @nor: pointer to 'struct spi_nor'.
387 * Return: 0 on success, -errno otherwise.
389 int spi_nor_write_disable(struct spi_nor *nor)
394 struct spi_mem_op op = SPI_NOR_WRDI_OP;
396 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
398 ret = spi_mem_exec_op(nor->spimem, &op);
400 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI,
405 dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
411 * spi_nor_read_id() - Read the JEDEC ID.
412 * @nor: pointer to 'struct spi_nor'.
413 * @naddr: number of address bytes to send. Can be zero if the operation
414 * does not need to send an address.
415 * @ndummy: number of dummy bytes to send after an opcode or address. Can
416 * be zero if the operation does not require dummy bytes.
417 * @id: pointer to a DMA-able buffer where the value of the JEDEC ID
419 * @proto: the SPI protocol for register operation.
421 * Return: 0 on success, -errno otherwise.
423 int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
424 enum spi_nor_protocol proto)
429 struct spi_mem_op op =
430 SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN);
432 spi_nor_spimem_setup_op(nor, &op, proto);
433 ret = spi_mem_exec_op(nor->spimem, &op);
435 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
442 * spi_nor_read_sr() - Read the Status Register.
443 * @nor: pointer to 'struct spi_nor'.
444 * @sr: pointer to a DMA-able buffer where the value of the
445 * Status Register will be written. Should be at least 2 bytes.
447 * Return: 0 on success, -errno otherwise.
449 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
454 struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
456 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
457 op.addr.nbytes = nor->params->rdsr_addr_nbytes;
458 op.dummy.nbytes = nor->params->rdsr_dummy;
460 * We don't want to read only one byte in DTR mode. So,
461 * read 2 and then discard the second byte.
466 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
468 ret = spi_mem_exec_op(nor->spimem, &op);
470 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
475 dev_dbg(nor->dev, "error %d reading SR\n", ret);
481 * spi_nor_read_cr() - Read the Configuration Register using the
482 * SPINOR_OP_RDCR (35h) command.
483 * @nor: pointer to 'struct spi_nor'
484 * @cr: pointer to a DMA-able buffer where the value of the
485 * Configuration Register will be written.
487 * Return: 0 on success, -errno otherwise.
489 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
494 struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
496 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
498 ret = spi_mem_exec_op(nor->spimem, &op);
500 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
505 dev_dbg(nor->dev, "error %d reading CR\n", ret);
511 * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode.
512 * @nor: pointer to 'struct spi_nor'.
513 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
516 * Return: 0 on success, -errno otherwise.
518 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
523 struct spi_mem_op op = SPI_NOR_EN4B_EX4B_OP(enable);
525 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
527 ret = spi_mem_exec_op(nor->spimem, &op);
529 ret = spi_nor_controller_ops_write_reg(nor,
530 enable ? SPINOR_OP_EN4B :
536 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
542 * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion
544 * @nor: pointer to 'struct spi_nor'.
545 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
548 * Return: 0 on success, -errno otherwise.
550 static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
554 nor->bouncebuf[0] = enable << 7;
557 struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf);
559 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
561 ret = spi_mem_exec_op(nor->spimem, &op);
563 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR,
568 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
574 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
576 * @nor: pointer to 'struct spi_nor'.
578 * Return: 1 if ready, 0 if not ready, -errno on errors.
580 int spi_nor_sr_ready(struct spi_nor *nor)
584 ret = spi_nor_read_sr(nor, nor->bouncebuf);
588 return !(nor->bouncebuf[0] & SR_WIP);
592 * spi_nor_ready() - Query the flash to see if it is ready for new commands.
593 * @nor: pointer to 'struct spi_nor'.
595 * Return: 1 if ready, 0 if not ready, -errno on errors.
597 static int spi_nor_ready(struct spi_nor *nor)
599 /* Flashes might override the standard routine. */
600 if (nor->params->ready)
601 return nor->params->ready(nor);
603 return spi_nor_sr_ready(nor);
607 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
608 * Status Register until ready, or timeout occurs.
609 * @nor: pointer to "struct spi_nor".
610 * @timeout_jiffies: jiffies to wait until timeout.
612 * Return: 0 on success, -errno otherwise.
614 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
615 unsigned long timeout_jiffies)
617 unsigned long deadline;
618 int timeout = 0, ret;
620 deadline = jiffies + timeout_jiffies;
623 if (time_after_eq(jiffies, deadline))
626 ret = spi_nor_ready(nor);
635 dev_dbg(nor->dev, "flash operation timed out\n");
641 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
642 * flash to be ready, or timeout occurs.
643 * @nor: pointer to "struct spi_nor".
645 * Return: 0 on success, -errno otherwise.
647 int spi_nor_wait_till_ready(struct spi_nor *nor)
649 return spi_nor_wait_till_ready_with_timeout(nor,
650 DEFAULT_READY_WAIT_JIFFIES);
654 * spi_nor_global_block_unlock() - Unlock Global Block Protection.
655 * @nor: pointer to 'struct spi_nor'.
657 * Return: 0 on success, -errno otherwise.
659 int spi_nor_global_block_unlock(struct spi_nor *nor)
663 ret = spi_nor_write_enable(nor);
668 struct spi_mem_op op = SPI_NOR_GBULK_OP;
670 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
672 ret = spi_mem_exec_op(nor->spimem, &op);
674 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK,
679 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret);
683 return spi_nor_wait_till_ready(nor);
687 * spi_nor_write_sr() - Write the Status Register.
688 * @nor: pointer to 'struct spi_nor'.
689 * @sr: pointer to DMA-able buffer to write to the Status Register.
690 * @len: number of bytes to write to the Status Register.
692 * Return: 0 on success, -errno otherwise.
694 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
698 ret = spi_nor_write_enable(nor);
703 struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
705 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
707 ret = spi_mem_exec_op(nor->spimem, &op);
709 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
714 dev_dbg(nor->dev, "error %d writing SR\n", ret);
718 return spi_nor_wait_till_ready(nor);
722 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
723 * ensure that the byte written match the received value.
724 * @nor: pointer to a 'struct spi_nor'.
725 * @sr1: byte value to be written to the Status Register.
727 * Return: 0 on success, -errno otherwise.
729 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
733 nor->bouncebuf[0] = sr1;
735 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
739 ret = spi_nor_read_sr(nor, nor->bouncebuf);
743 if (nor->bouncebuf[0] != sr1) {
744 dev_dbg(nor->dev, "SR1: read back test failed\n");
752 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
753 * Status Register 2 in one shot. Ensure that the byte written in the Status
754 * Register 1 match the received value, and that the 16-bit Write did not
755 * affect what was already in the Status Register 2.
756 * @nor: pointer to a 'struct spi_nor'.
757 * @sr1: byte value to be written to the Status Register 1.
759 * Return: 0 on success, -errno otherwise.
761 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
764 u8 *sr_cr = nor->bouncebuf;
767 /* Make sure we don't overwrite the contents of Status Register 2. */
768 if (!(nor->flags & SNOR_F_NO_READ_CR)) {
769 ret = spi_nor_read_cr(nor, &sr_cr[1]);
772 } else if (nor->params->quad_enable) {
774 * If the Status Register 2 Read command (35h) is not
775 * supported, we should at least be sure we don't
776 * change the value of the SR2 Quad Enable bit.
778 * We can safely assume that when the Quad Enable method is
779 * set, the value of the QE bit is one, as a consequence of the
780 * nor->params->quad_enable() call.
782 * We can safely assume that the Quad Enable bit is present in
783 * the Status Register 2 at BIT(1). According to the JESD216
784 * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
785 * Write Status (01h) command is available just for the cases
786 * in which the QE bit is described in SR2 at BIT(1).
788 sr_cr[1] = SR2_QUAD_EN_BIT1;
795 ret = spi_nor_write_sr(nor, sr_cr, 2);
799 ret = spi_nor_read_sr(nor, sr_cr);
803 if (sr1 != sr_cr[0]) {
804 dev_dbg(nor->dev, "SR: Read back test failed\n");
808 if (nor->flags & SNOR_F_NO_READ_CR)
811 cr_written = sr_cr[1];
813 ret = spi_nor_read_cr(nor, &sr_cr[1]);
817 if (cr_written != sr_cr[1]) {
818 dev_dbg(nor->dev, "CR: read back test failed\n");
826 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
827 * Configuration Register in one shot. Ensure that the byte written in the
828 * Configuration Register match the received value, and that the 16-bit Write
829 * did not affect what was already in the Status Register 1.
830 * @nor: pointer to a 'struct spi_nor'.
831 * @cr: byte value to be written to the Configuration Register.
833 * Return: 0 on success, -errno otherwise.
835 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
838 u8 *sr_cr = nor->bouncebuf;
841 /* Keep the current value of the Status Register 1. */
842 ret = spi_nor_read_sr(nor, sr_cr);
848 ret = spi_nor_write_sr(nor, sr_cr, 2);
852 sr_written = sr_cr[0];
854 ret = spi_nor_read_sr(nor, sr_cr);
858 if (sr_written != sr_cr[0]) {
859 dev_dbg(nor->dev, "SR: Read back test failed\n");
863 if (nor->flags & SNOR_F_NO_READ_CR)
866 ret = spi_nor_read_cr(nor, &sr_cr[1]);
870 if (cr != sr_cr[1]) {
871 dev_dbg(nor->dev, "CR: read back test failed\n");
879 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
880 * the byte written match the received value without affecting other bits in the
881 * Status Register 1 and 2.
882 * @nor: pointer to a 'struct spi_nor'.
883 * @sr1: byte value to be written to the Status Register.
885 * Return: 0 on success, -errno otherwise.
887 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
889 if (nor->flags & SNOR_F_HAS_16BIT_SR)
890 return spi_nor_write_16bit_sr_and_check(nor, sr1);
892 return spi_nor_write_sr1_and_check(nor, sr1);
896 * spi_nor_write_sr2() - Write the Status Register 2 using the
897 * SPINOR_OP_WRSR2 (3eh) command.
898 * @nor: pointer to 'struct spi_nor'.
899 * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
901 * Return: 0 on success, -errno otherwise.
903 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
907 ret = spi_nor_write_enable(nor);
912 struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
914 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
916 ret = spi_mem_exec_op(nor->spimem, &op);
918 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
923 dev_dbg(nor->dev, "error %d writing SR2\n", ret);
927 return spi_nor_wait_till_ready(nor);
931 * spi_nor_read_sr2() - Read the Status Register 2 using the
932 * SPINOR_OP_RDSR2 (3fh) command.
933 * @nor: pointer to 'struct spi_nor'.
934 * @sr2: pointer to DMA-able buffer where the value of the
935 * Status Register 2 will be written.
937 * Return: 0 on success, -errno otherwise.
939 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
944 struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
946 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
948 ret = spi_mem_exec_op(nor->spimem, &op);
950 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
955 dev_dbg(nor->dev, "error %d reading SR2\n", ret);
961 * spi_nor_erase_chip() - Erase the entire flash memory.
962 * @nor: pointer to 'struct spi_nor'.
964 * Return: 0 on success, -errno otherwise.
966 static int spi_nor_erase_chip(struct spi_nor *nor)
970 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
973 struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP;
975 spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
977 ret = spi_mem_exec_op(nor->spimem, &op);
979 ret = spi_nor_controller_ops_write_reg(nor,
980 SPINOR_OP_CHIP_ERASE,
985 dev_dbg(nor->dev, "error %d erasing chip\n", ret);
990 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
994 for (i = 0; i < size; i++)
995 if (table[i][0] == opcode)
998 /* No conversion found, keep input op code. */
1002 u8 spi_nor_convert_3to4_read(u8 opcode)
1004 static const u8 spi_nor_3to4_read[][2] = {
1005 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
1006 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
1007 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
1008 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
1009 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
1010 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
1011 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
1012 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
1014 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
1015 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
1016 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
1019 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1020 ARRAY_SIZE(spi_nor_3to4_read));
1023 static u8 spi_nor_convert_3to4_program(u8 opcode)
1025 static const u8 spi_nor_3to4_program[][2] = {
1026 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
1027 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
1028 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
1029 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
1030 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
1033 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1034 ARRAY_SIZE(spi_nor_3to4_program));
1037 static u8 spi_nor_convert_3to4_erase(u8 opcode)
1039 static const u8 spi_nor_3to4_erase[][2] = {
1040 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
1041 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
1042 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
1045 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1046 ARRAY_SIZE(spi_nor_3to4_erase));
1049 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
1051 return !!nor->params->erase_map.uniform_erase_type;
1054 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1056 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1057 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1058 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1060 if (!spi_nor_has_uniform_erase(nor)) {
1061 struct spi_nor_erase_map *map = &nor->params->erase_map;
1062 struct spi_nor_erase_type *erase;
1065 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1066 erase = &map->erase_type[i];
1068 spi_nor_convert_3to4_erase(erase->opcode);
1073 int spi_nor_lock_and_prep(struct spi_nor *nor)
1077 mutex_lock(&nor->lock);
1079 if (nor->controller_ops && nor->controller_ops->prepare) {
1080 ret = nor->controller_ops->prepare(nor);
1082 mutex_unlock(&nor->lock);
1089 void spi_nor_unlock_and_unprep(struct spi_nor *nor)
1091 if (nor->controller_ops && nor->controller_ops->unprepare)
1092 nor->controller_ops->unprepare(nor);
1093 mutex_unlock(&nor->lock);
1096 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1098 if (!nor->params->convert_addr)
1101 return nor->params->convert_addr(nor, addr);
1105 * Initiate the erasure of a single sector
1107 int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1111 addr = spi_nor_convert_addr(nor, addr);
1114 struct spi_mem_op op =
1115 SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode,
1116 nor->addr_width, addr);
1118 spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
1120 return spi_mem_exec_op(nor->spimem, &op);
1121 } else if (nor->controller_ops->erase) {
1122 return spi_nor_controller_ops_erase(nor, addr);
1126 * Default implementation, if driver doesn't have a specialized HW
1129 for (i = nor->addr_width - 1; i >= 0; i--) {
1130 nor->bouncebuf[i] = addr & 0xff;
1134 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode,
1135 nor->bouncebuf, nor->addr_width);
1139 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1140 * @erase: pointer to a structure that describes a SPI NOR erase type
1141 * @dividend: dividend value
1142 * @remainder: pointer to u32 remainder (will be updated)
1144 * Return: the result of the division
1146 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1147 u64 dividend, u32 *remainder)
1149 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1150 *remainder = (u32)dividend & erase->size_mask;
1151 return dividend >> erase->size_shift;
1155 * spi_nor_find_best_erase_type() - find the best erase type for the given
1156 * offset in the serial flash memory and the
1157 * number of bytes to erase. The region in
1158 * which the address fits is expected to be
1160 * @map: the erase map of the SPI NOR
1161 * @region: pointer to a structure that describes a SPI NOR erase region
1162 * @addr: offset in the serial flash memory
1163 * @len: number of bytes to erase
1165 * Return: a pointer to the best fitted erase type, NULL otherwise.
1167 static const struct spi_nor_erase_type *
1168 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1169 const struct spi_nor_erase_region *region,
1172 const struct spi_nor_erase_type *erase;
1175 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
1178 * Erase types are ordered by size, with the smallest erase type at
1181 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1182 /* Does the erase region support the tested erase type? */
1183 if (!(erase_mask & BIT(i)))
1186 erase = &map->erase_type[i];
1188 /* Alignment is not mandatory for overlaid regions */
1189 if (region->offset & SNOR_OVERLAID_REGION &&
1190 region->size <= len)
1193 /* Don't erase more than what the user has asked for. */
1194 if (erase->size > len)
1197 spi_nor_div_by_erase_size(erase, addr, &rem);
1205 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
1207 return region->offset & SNOR_LAST_REGION;
1210 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region)
1212 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
1216 * spi_nor_region_next() - get the next spi nor region
1217 * @region: pointer to a structure that describes a SPI NOR erase region
1219 * Return: the next spi nor region or NULL if last region.
1221 struct spi_nor_erase_region *
1222 spi_nor_region_next(struct spi_nor_erase_region *region)
1224 if (spi_nor_region_is_last(region))
1231 * spi_nor_find_erase_region() - find the region of the serial flash memory in
1232 * which the offset fits
1233 * @map: the erase map of the SPI NOR
1234 * @addr: offset in the serial flash memory
1236 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
1239 static struct spi_nor_erase_region *
1240 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
1242 struct spi_nor_erase_region *region = map->regions;
1243 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1244 u64 region_end = region_start + region->size;
1246 while (addr < region_start || addr >= region_end) {
1247 region = spi_nor_region_next(region);
1249 return ERR_PTR(-EINVAL);
1251 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1252 region_end = region_start + region->size;
1259 * spi_nor_init_erase_cmd() - initialize an erase command
1260 * @region: pointer to a structure that describes a SPI NOR erase region
1261 * @erase: pointer to a structure that describes a SPI NOR erase type
1263 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1266 static struct spi_nor_erase_command *
1267 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1268 const struct spi_nor_erase_type *erase)
1270 struct spi_nor_erase_command *cmd;
1272 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1274 return ERR_PTR(-ENOMEM);
1276 INIT_LIST_HEAD(&cmd->list);
1277 cmd->opcode = erase->opcode;
1280 if (region->offset & SNOR_OVERLAID_REGION)
1281 cmd->size = region->size;
1283 cmd->size = erase->size;
1289 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1290 * @erase_list: list of erase commands
1292 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1294 struct spi_nor_erase_command *cmd, *next;
1296 list_for_each_entry_safe(cmd, next, erase_list, list) {
1297 list_del(&cmd->list);
1303 * spi_nor_init_erase_cmd_list() - initialize erase command list
1304 * @nor: pointer to a 'struct spi_nor'
1305 * @erase_list: list of erase commands to be executed once we validate that the
1306 * erase can be performed
1307 * @addr: offset in the serial flash memory
1308 * @len: number of bytes to erase
1310 * Builds the list of best fitted erase commands and verifies if the erase can
1313 * Return: 0 on success, -errno otherwise.
1315 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1316 struct list_head *erase_list,
1319 const struct spi_nor_erase_map *map = &nor->params->erase_map;
1320 const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1321 struct spi_nor_erase_region *region;
1322 struct spi_nor_erase_command *cmd = NULL;
1326 region = spi_nor_find_erase_region(map, addr);
1328 return PTR_ERR(region);
1330 region_end = spi_nor_region_end(region);
1333 erase = spi_nor_find_best_erase_type(map, region, addr, len);
1335 goto destroy_erase_cmd_list;
1337 if (prev_erase != erase ||
1338 erase->size != cmd->size ||
1339 region->offset & SNOR_OVERLAID_REGION) {
1340 cmd = spi_nor_init_erase_cmd(region, erase);
1343 goto destroy_erase_cmd_list;
1346 list_add_tail(&cmd->list, erase_list);
1354 if (len && addr >= region_end) {
1355 region = spi_nor_region_next(region);
1357 goto destroy_erase_cmd_list;
1358 region_end = spi_nor_region_end(region);
1366 destroy_erase_cmd_list:
1367 spi_nor_destroy_erase_cmd_list(erase_list);
1372 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1373 * @nor: pointer to a 'struct spi_nor'
1374 * @addr: offset in the serial flash memory
1375 * @len: number of bytes to erase
1377 * Build a list of best fitted erase commands and execute it once we validate
1378 * that the erase can be performed.
1380 * Return: 0 on success, -errno otherwise.
1382 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1384 LIST_HEAD(erase_list);
1385 struct spi_nor_erase_command *cmd, *next;
1388 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1392 list_for_each_entry_safe(cmd, next, &erase_list, list) {
1393 nor->erase_opcode = cmd->opcode;
1394 while (cmd->count) {
1395 dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n",
1396 cmd->size, cmd->opcode, cmd->count);
1398 ret = spi_nor_write_enable(nor);
1400 goto destroy_erase_cmd_list;
1402 ret = spi_nor_erase_sector(nor, addr);
1404 goto destroy_erase_cmd_list;
1406 ret = spi_nor_wait_till_ready(nor);
1408 goto destroy_erase_cmd_list;
1413 list_del(&cmd->list);
1419 destroy_erase_cmd_list:
1420 spi_nor_destroy_erase_cmd_list(&erase_list);
1425 * Erase an address range on the nor chip. The address range may extend
1426 * one or more erase sectors. Return an error if there is a problem erasing.
1428 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1430 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1435 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1436 (long long)instr->len);
1438 if (spi_nor_has_uniform_erase(nor)) {
1439 div_u64_rem(instr->len, mtd->erasesize, &rem);
1447 ret = spi_nor_lock_and_prep(nor);
1451 /* whole-chip erase? */
1452 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1453 unsigned long timeout;
1455 ret = spi_nor_write_enable(nor);
1459 ret = spi_nor_erase_chip(nor);
1464 * Scale the timeout linearly with the size of the flash, with
1465 * a minimum calibrated to an old 2MB flash. We could try to
1466 * pull these from CFI/SFDP, but these values should be good
1469 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1470 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1471 (unsigned long)(mtd->size / SZ_2M));
1472 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1476 /* REVISIT in some cases we could speed up erasing large regions
1477 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1478 * to use "small sector erase", but that's not always optimal.
1481 /* "sector"-at-a-time erase */
1482 } else if (spi_nor_has_uniform_erase(nor)) {
1484 ret = spi_nor_write_enable(nor);
1488 ret = spi_nor_erase_sector(nor, addr);
1492 ret = spi_nor_wait_till_ready(nor);
1496 addr += mtd->erasesize;
1497 len -= mtd->erasesize;
1500 /* erase multiple sectors */
1502 ret = spi_nor_erase_multi_sectors(nor, addr, len);
1507 ret = spi_nor_write_disable(nor);
1510 spi_nor_unlock_and_unprep(nor);
1516 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1518 * @nor: pointer to a 'struct spi_nor'
1520 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
1522 * Return: 0 on success, -errno otherwise.
1524 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
1528 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1532 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
1535 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
1537 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
1541 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1543 * @nor: pointer to a 'struct spi_nor'.
1545 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
1547 * Return: 0 on success, -errno otherwise.
1549 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
1553 if (nor->flags & SNOR_F_NO_READ_CR)
1554 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
1556 ret = spi_nor_read_cr(nor, nor->bouncebuf);
1560 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
1563 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
1565 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
1569 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1570 * @nor: pointer to a 'struct spi_nor'
1572 * Set the Quad Enable (QE) bit in the Status Register 2.
1574 * This is one of the procedures to set the QE bit described in the SFDP
1575 * (JESD216 rev B) specification but no manufacturer using this procedure has
1576 * been identified yet, hence the name of the function.
1578 * Return: 0 on success, -errno otherwise.
1580 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
1582 u8 *sr2 = nor->bouncebuf;
1586 /* Check current Quad Enable bit value. */
1587 ret = spi_nor_read_sr2(nor, sr2);
1590 if (*sr2 & SR2_QUAD_EN_BIT7)
1593 /* Update the Quad Enable bit. */
1594 *sr2 |= SR2_QUAD_EN_BIT7;
1596 ret = spi_nor_write_sr2(nor, sr2);
1602 /* Read back and check it. */
1603 ret = spi_nor_read_sr2(nor, sr2);
1607 if (*sr2 != sr2_written) {
1608 dev_dbg(nor->dev, "SR2: Read back test failed\n");
1615 static const struct spi_nor_manufacturer *manufacturers[] = {
1622 &spi_nor_gigadevice,
1635 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
1638 const struct flash_info *part;
1641 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
1642 for (j = 0; j < manufacturers[i]->nparts; j++) {
1643 part = &manufacturers[i]->parts[j];
1645 !memcmp(part->id, id, part->id_len)) {
1646 nor->manufacturer = manufacturers[i];
1655 static const struct flash_info *spi_nor_detect(struct spi_nor *nor)
1657 const struct flash_info *info;
1658 u8 *id = nor->bouncebuf;
1661 ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto);
1663 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);
1664 return ERR_PTR(ret);
1667 info = spi_nor_match_id(nor, id);
1669 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
1670 SPI_NOR_MAX_ID_LEN, id);
1671 return ERR_PTR(-ENODEV);
1676 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1677 size_t *retlen, u_char *buf)
1679 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1682 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1684 ret = spi_nor_lock_and_prep(nor);
1691 addr = spi_nor_convert_addr(nor, addr);
1693 ret = spi_nor_read_data(nor, addr, len, buf);
1695 /* We shouldn't see 0-length reads */
1711 spi_nor_unlock_and_unprep(nor);
1716 * Write an address range to the nor chip. Data must be written in
1717 * FLASH_PAGESIZE chunks. The address range may be any size provided
1718 * it is within the physical boundaries.
1720 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1721 size_t *retlen, const u_char *buf)
1723 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1724 size_t page_offset, page_remain, i;
1726 u32 page_size = nor->params->page_size;
1728 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1730 ret = spi_nor_lock_and_prep(nor);
1734 for (i = 0; i < len; ) {
1736 loff_t addr = to + i;
1739 * If page_size is a power of two, the offset can be quickly
1740 * calculated with an AND operation. On the other cases we
1741 * need to do a modulus operation (more expensive).
1743 if (is_power_of_2(page_size)) {
1744 page_offset = addr & (page_size - 1);
1746 uint64_t aux = addr;
1748 page_offset = do_div(aux, page_size);
1750 /* the size of data remaining on the first page */
1751 page_remain = min_t(size_t, page_size - page_offset, len - i);
1753 addr = spi_nor_convert_addr(nor, addr);
1755 ret = spi_nor_write_enable(nor);
1759 ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
1764 ret = spi_nor_wait_till_ready(nor);
1772 spi_nor_unlock_and_unprep(nor);
1776 static int spi_nor_check(struct spi_nor *nor)
1779 (!nor->spimem && !nor->controller_ops) ||
1780 (!nor->spimem && nor->controller_ops &&
1781 (!nor->controller_ops->read ||
1782 !nor->controller_ops->write ||
1783 !nor->controller_ops->read_reg ||
1784 !nor->controller_ops->write_reg))) {
1785 pr_err("spi-nor: please fill all the necessary fields!\n");
1789 if (nor->spimem && nor->controller_ops) {
1790 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
1798 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1802 enum spi_nor_protocol proto)
1804 read->num_mode_clocks = num_mode_clocks;
1805 read->num_wait_states = num_wait_states;
1806 read->opcode = opcode;
1807 read->proto = proto;
1810 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
1811 enum spi_nor_protocol proto)
1813 pp->opcode = opcode;
1817 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
1821 for (i = 0; i < size; i++)
1822 if (table[i][0] == (int)hwcaps)
1828 int spi_nor_hwcaps_read2cmd(u32 hwcaps)
1830 static const int hwcaps_read2cmd[][2] = {
1831 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
1832 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
1833 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
1834 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
1835 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
1836 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
1837 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
1838 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
1839 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
1840 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
1841 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
1842 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
1843 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
1844 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
1845 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
1846 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },
1849 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
1850 ARRAY_SIZE(hwcaps_read2cmd));
1853 int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
1855 static const int hwcaps_pp2cmd[][2] = {
1856 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
1857 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
1858 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
1859 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
1860 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
1861 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
1862 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
1863 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },
1866 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
1867 ARRAY_SIZE(hwcaps_pp2cmd));
1871 * spi_nor_spimem_check_op - check if the operation is supported
1873 *@nor: pointer to a 'struct spi_nor'
1874 *@op: pointer to op template to be checked
1876 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
1878 static int spi_nor_spimem_check_op(struct spi_nor *nor,
1879 struct spi_mem_op *op)
1882 * First test with 4 address bytes. The opcode itself might
1883 * be a 3B addressing opcode but we don't care, because
1884 * SPI controller implementation should not check the opcode,
1885 * but just the sequence.
1887 op->addr.nbytes = 4;
1888 if (!spi_mem_supports_op(nor->spimem, op)) {
1889 if (nor->params->size > SZ_16M)
1892 /* If flash size <= 16MB, 3 address bytes are sufficient */
1893 op->addr.nbytes = 3;
1894 if (!spi_mem_supports_op(nor->spimem, op))
1902 * spi_nor_spimem_check_readop - check if the read op is supported
1904 *@nor: pointer to a 'struct spi_nor'
1905 *@read: pointer to op template to be checked
1907 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
1909 static int spi_nor_spimem_check_readop(struct spi_nor *nor,
1910 const struct spi_nor_read_command *read)
1912 struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode);
1914 spi_nor_spimem_setup_op(nor, &op, read->proto);
1916 /* convert the dummy cycles to the number of bytes */
1917 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
1918 if (spi_nor_protocol_is_dtr(nor->read_proto))
1919 op.dummy.nbytes *= 2;
1921 return spi_nor_spimem_check_op(nor, &op);
1925 * spi_nor_spimem_check_pp - check if the page program op is supported
1927 *@nor: pointer to a 'struct spi_nor'
1928 *@pp: pointer to op template to be checked
1930 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
1932 static int spi_nor_spimem_check_pp(struct spi_nor *nor,
1933 const struct spi_nor_pp_command *pp)
1935 struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode);
1937 spi_nor_spimem_setup_op(nor, &op, pp->proto);
1939 return spi_nor_spimem_check_op(nor, &op);
1943 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
1944 * based on SPI controller capabilities
1945 * @nor: pointer to a 'struct spi_nor'
1946 * @hwcaps: pointer to resulting capabilities after adjusting
1947 * according to controller and flash's capability
1950 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
1952 struct spi_nor_flash_parameter *params = nor->params;
1955 /* X-X-X modes are not supported yet, mask them all. */
1956 *hwcaps &= ~SNOR_HWCAPS_X_X_X;
1959 * If the reset line is broken, we do not want to enter a stateful
1962 if (nor->flags & SNOR_F_BROKEN_RESET)
1963 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
1965 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
1968 if (!(*hwcaps & BIT(cap)))
1971 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
1973 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx]))
1974 *hwcaps &= ~BIT(cap);
1976 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
1980 if (spi_nor_spimem_check_pp(nor,
1981 ¶ms->page_programs[ppidx]))
1982 *hwcaps &= ~BIT(cap);
1987 * spi_nor_set_erase_type() - set a SPI NOR erase type
1988 * @erase: pointer to a structure that describes a SPI NOR erase type
1989 * @size: the size of the sector/block erased by the erase type
1990 * @opcode: the SPI command op code to erase the sector/block
1992 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
1996 erase->opcode = opcode;
1997 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1998 erase->size_shift = ffs(erase->size) - 1;
1999 erase->size_mask = (1 << erase->size_shift) - 1;
2003 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2004 * @map: the erase map of the SPI NOR
2005 * @erase_mask: bitmask encoding erase types that can erase the entire
2007 * @flash_size: the spi nor flash memory size
2009 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2010 u8 erase_mask, u64 flash_size)
2012 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2013 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2015 map->uniform_region.size = flash_size;
2016 map->regions = &map->uniform_region;
2017 map->uniform_erase_type = erase_mask;
2020 int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2021 const struct sfdp_parameter_header *bfpt_header,
2022 const struct sfdp_bfpt *bfpt)
2026 if (nor->manufacturer && nor->manufacturer->fixups &&
2027 nor->manufacturer->fixups->post_bfpt) {
2028 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
2034 if (nor->info->fixups && nor->info->fixups->post_bfpt)
2035 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
2040 static int spi_nor_select_read(struct spi_nor *nor,
2043 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2044 const struct spi_nor_read_command *read;
2049 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2053 read = &nor->params->reads[cmd];
2054 nor->read_opcode = read->opcode;
2055 nor->read_proto = read->proto;
2058 * In the SPI NOR framework, we don't need to make the difference
2059 * between mode clock cycles and wait state clock cycles.
2060 * Indeed, the value of the mode clock cycles is used by a QSPI
2061 * flash memory to know whether it should enter or leave its 0-4-4
2062 * (Continuous Read / XIP) mode.
2063 * eXecution In Place is out of the scope of the mtd sub-system.
2064 * Hence we choose to merge both mode and wait state clock cycles
2065 * into the so called dummy clock cycles.
2067 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2071 static int spi_nor_select_pp(struct spi_nor *nor,
2074 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2075 const struct spi_nor_pp_command *pp;
2080 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2084 pp = &nor->params->page_programs[cmd];
2085 nor->program_opcode = pp->opcode;
2086 nor->write_proto = pp->proto;
2091 * spi_nor_select_uniform_erase() - select optimum uniform erase type
2092 * @map: the erase map of the SPI NOR
2093 * @wanted_size: the erase type size to search for. Contains the value of
2094 * info->sector_size or of the "small sector" size in case
2095 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
2097 * Once the optimum uniform sector erase command is found, disable all the
2100 * Return: pointer to erase type on success, NULL otherwise.
2102 static const struct spi_nor_erase_type *
2103 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
2104 const u32 wanted_size)
2106 const struct spi_nor_erase_type *tested_erase, *erase = NULL;
2108 u8 uniform_erase_type = map->uniform_erase_type;
2110 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2111 if (!(uniform_erase_type & BIT(i)))
2114 tested_erase = &map->erase_type[i];
2117 * If the current erase size is the one, stop here:
2118 * we have found the right uniform Sector Erase command.
2120 if (tested_erase->size == wanted_size) {
2121 erase = tested_erase;
2126 * Otherwise, the current erase size is still a valid candidate.
2127 * Select the biggest valid candidate.
2129 if (!erase && tested_erase->size)
2130 erase = tested_erase;
2131 /* keep iterating to find the wanted_size */
2137 /* Disable all other Sector Erase commands. */
2138 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
2139 map->uniform_erase_type |= BIT(erase - map->erase_type);
2143 static int spi_nor_select_erase(struct spi_nor *nor)
2145 struct spi_nor_erase_map *map = &nor->params->erase_map;
2146 const struct spi_nor_erase_type *erase = NULL;
2147 struct mtd_info *mtd = &nor->mtd;
2148 u32 wanted_size = nor->info->sector_size;
2152 * The previous implementation handling Sector Erase commands assumed
2153 * that the SPI flash memory has an uniform layout then used only one
2154 * of the supported erase sizes for all Sector Erase commands.
2155 * So to be backward compatible, the new implementation also tries to
2156 * manage the SPI flash memory as uniform with a single erase sector
2157 * size, when possible.
2159 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2160 /* prefer "small sector" erase if possible */
2161 wanted_size = 4096u;
2164 if (spi_nor_has_uniform_erase(nor)) {
2165 erase = spi_nor_select_uniform_erase(map, wanted_size);
2168 nor->erase_opcode = erase->opcode;
2169 mtd->erasesize = erase->size;
2174 * For non-uniform SPI flash memory, set mtd->erasesize to the
2175 * maximum erase sector size. No need to set nor->erase_opcode.
2177 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2178 if (map->erase_type[i].size) {
2179 erase = &map->erase_type[i];
2187 mtd->erasesize = erase->size;
2191 static int spi_nor_default_setup(struct spi_nor *nor,
2192 const struct spi_nor_hwcaps *hwcaps)
2194 struct spi_nor_flash_parameter *params = nor->params;
2195 u32 ignored_mask, shared_mask;
2199 * Keep only the hardware capabilities supported by both the SPI
2200 * controller and the SPI flash memory.
2202 shared_mask = hwcaps->mask & params->hwcaps.mask;
2206 * When called from spi_nor_probe(), all caps are set and we
2207 * need to discard some of them based on what the SPI
2208 * controller actually supports (using spi_mem_supports_op()).
2210 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
2213 * SPI n-n-n protocols are not supported when the SPI
2214 * controller directly implements the spi_nor interface.
2215 * Yet another reason to switch to spi-mem.
2217 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR;
2218 if (shared_mask & ignored_mask) {
2220 "SPI n-n-n protocols are not supported.\n");
2221 shared_mask &= ~ignored_mask;
2225 /* Select the (Fast) Read command. */
2226 err = spi_nor_select_read(nor, shared_mask);
2229 "can't select read settings supported by both the SPI controller and memory.\n");
2233 /* Select the Page Program command. */
2234 err = spi_nor_select_pp(nor, shared_mask);
2237 "can't select write settings supported by both the SPI controller and memory.\n");
2241 /* Select the Sector Erase command. */
2242 err = spi_nor_select_erase(nor);
2245 "can't select erase settings supported by both the SPI controller and memory.\n");
2252 static int spi_nor_set_addr_width(struct spi_nor *nor)
2254 if (nor->addr_width) {
2255 /* already configured from SFDP */
2256 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
2258 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
2259 * in this protocol an odd address width cannot be used because
2260 * then the address phase would only span a cycle and a half.
2261 * Half a cycle would be left over. We would then have to start
2262 * the dummy phase in the middle of a cycle and so too the data
2263 * phase, and we will end the transaction with half a cycle left
2266 * Force all 8D-8D-8D flashes to use an address width of 4 to
2267 * avoid this situation.
2269 nor->addr_width = 4;
2270 } else if (nor->info->addr_width) {
2271 nor->addr_width = nor->info->addr_width;
2273 nor->addr_width = 3;
2276 if (nor->addr_width == 3 && nor->params->size > 0x1000000) {
2277 /* enable 4-byte addressing if the device exceeds 16MiB */
2278 nor->addr_width = 4;
2281 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2282 dev_dbg(nor->dev, "address width is too large: %u\n",
2287 /* Set 4byte opcodes when possible. */
2288 if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
2289 !(nor->flags & SNOR_F_HAS_4BAIT))
2290 spi_nor_set_4byte_opcodes(nor);
2295 static int spi_nor_setup(struct spi_nor *nor,
2296 const struct spi_nor_hwcaps *hwcaps)
2300 if (nor->params->setup)
2301 ret = nor->params->setup(nor, hwcaps);
2303 ret = spi_nor_default_setup(nor, hwcaps);
2307 return spi_nor_set_addr_width(nor);
2311 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
2312 * settings based on MFR register and ->default_init() hook.
2313 * @nor: pointer to a 'struct spi_nor'.
2315 static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
2317 if (nor->manufacturer && nor->manufacturer->fixups &&
2318 nor->manufacturer->fixups->default_init)
2319 nor->manufacturer->fixups->default_init(nor);
2321 if (nor->info->fixups && nor->info->fixups->default_init)
2322 nor->info->fixups->default_init(nor);
2326 * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and
2327 * settings based on nor->info->sfdp_flags. This method should be called only by
2328 * flashes that do not define SFDP tables. If the flash supports SFDP but the
2329 * information is wrong and the settings from this function can not be retrieved
2330 * by parsing SFDP, one should instead use the fixup hooks and update the wrong
2332 * @nor: pointer to a 'struct spi_nor'.
2334 static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
2336 struct spi_nor_flash_parameter *params = nor->params;
2337 struct spi_nor_erase_map *map = ¶ms->erase_map;
2338 const u8 no_sfdp_flags = nor->info->no_sfdp_flags;
2341 if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
2342 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2343 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2344 0, 8, SPINOR_OP_READ_1_1_2,
2348 if (no_sfdp_flags & SPI_NOR_QUAD_READ) {
2349 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2350 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2351 0, 8, SPINOR_OP_READ_1_1_4,
2355 if (no_sfdp_flags & SPI_NOR_OCTAL_READ) {
2356 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2357 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
2358 0, 8, SPINOR_OP_READ_1_1_8,
2362 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
2363 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2364 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
2365 0, 20, SPINOR_OP_READ_FAST,
2366 SNOR_PROTO_8_8_8_DTR);
2369 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) {
2370 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
2372 * Since xSPI Page Program opcode is backward compatible with
2373 * Legacy SPI, use Legacy SPI opcode there as well.
2375 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2376 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2380 * Sector Erase settings. Sort Erase Types in ascending order, with the
2381 * smallest erase size starting at BIT(0).
2385 if (no_sfdp_flags & SECT_4K_PMC) {
2386 erase_mask |= BIT(i);
2387 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2388 SPINOR_OP_BE_4K_PMC);
2390 } else if (no_sfdp_flags & SECT_4K) {
2391 erase_mask |= BIT(i);
2392 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2396 erase_mask |= BIT(i);
2397 spi_nor_set_erase_type(&map->erase_type[i], nor->info->sector_size,
2399 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2403 * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined
2404 * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP.
2405 * @nor: pointer to a 'struct spi_nor'
2407 static void spi_nor_init_flags(struct spi_nor *nor)
2409 struct device_node *np = spi_nor_get_flash_node(nor);
2410 const u16 flags = nor->info->flags;
2412 if (of_property_read_bool(np, "broken-flash-reset"))
2413 nor->flags |= SNOR_F_BROKEN_RESET;
2415 if (flags & SPI_NOR_SWP_IS_VOLATILE)
2416 nor->flags |= SNOR_F_SWP_IS_VOLATILE;
2418 if (flags & SPI_NOR_HAS_LOCK)
2419 nor->flags |= SNOR_F_HAS_LOCK;
2421 if (flags & SPI_NOR_HAS_TB) {
2422 nor->flags |= SNOR_F_HAS_SR_TB;
2423 if (flags & SPI_NOR_TB_SR_BIT6)
2424 nor->flags |= SNOR_F_HAS_SR_TB_BIT6;
2427 if (flags & SPI_NOR_4BIT_BP) {
2428 nor->flags |= SNOR_F_HAS_4BIT_BP;
2429 if (flags & SPI_NOR_BP3_SR_BIT6)
2430 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
2433 if (flags & NO_CHIP_ERASE)
2434 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2438 * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not
2439 * be discovered by SFDP for this particular flash because the SFDP table that
2440 * indicates this support is not defined in the flash. In case the table for
2441 * this support is defined but has wrong values, one should instead use a
2442 * post_sfdp() hook to set the SNOR_F equivalent flag.
2443 * @nor: pointer to a 'struct spi_nor'
2445 static void spi_nor_init_fixup_flags(struct spi_nor *nor)
2447 const u8 fixup_flags = nor->info->fixup_flags;
2449 if (fixup_flags & SPI_NOR_4B_OPCODES)
2450 nor->flags |= SNOR_F_4B_OPCODES;
2452 if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE)
2453 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
2457 * spi_nor_late_init_params() - Late initialization of default flash parameters.
2458 * @nor: pointer to a 'struct spi_nor'
2460 * Used to initialize flash parameters that are not declared in the JESD216
2461 * SFDP standard, or where SFDP tables are not defined at all.
2462 * Will replace the spi_nor_manufacturer_init_params() method.
2464 static void spi_nor_late_init_params(struct spi_nor *nor)
2466 if (nor->manufacturer && nor->manufacturer->fixups &&
2467 nor->manufacturer->fixups->late_init)
2468 nor->manufacturer->fixups->late_init(nor);
2470 if (nor->info->fixups && nor->info->fixups->late_init)
2471 nor->info->fixups->late_init(nor);
2473 spi_nor_init_flags(nor);
2474 spi_nor_init_fixup_flags(nor);
2477 * NOR protection support. When locking_ops are not provided, we pick
2480 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
2481 spi_nor_init_default_locking_ops(nor);
2485 * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash
2486 * parameters and settings based on JESD216 SFDP standard.
2487 * @nor: pointer to a 'struct spi_nor'.
2489 * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2490 * legacy flash parameters and settings will be restored.
2492 static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
2494 struct spi_nor_flash_parameter sfdp_params;
2496 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2498 if (spi_nor_parse_sfdp(nor)) {
2499 memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2500 nor->addr_width = 0;
2501 nor->flags &= ~SNOR_F_4B_OPCODES;
2506 * spi_nor_init_params_deprecated() - Deprecated way of initializing flash
2507 * parameters and settings.
2508 * @nor: pointer to a 'struct spi_nor'.
2510 * The method assumes that flash doesn't support SFDP so it initializes flash
2511 * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten
2512 * when parsing SFDP, if supported.
2514 static void spi_nor_init_params_deprecated(struct spi_nor *nor)
2516 spi_nor_no_sfdp_init_params(nor);
2518 spi_nor_manufacturer_init_params(nor);
2520 if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ |
2522 SPI_NOR_OCTAL_READ |
2523 SPI_NOR_OCTAL_DTR_READ))
2524 spi_nor_sfdp_init_params_deprecated(nor);
2528 * spi_nor_init_default_params() - Default initialization of flash parameters
2529 * and settings. Done for all flashes, regardless is they define SFDP tables
2531 * @nor: pointer to a 'struct spi_nor'.
2533 static void spi_nor_init_default_params(struct spi_nor *nor)
2535 struct spi_nor_flash_parameter *params = nor->params;
2536 const struct flash_info *info = nor->info;
2537 struct device_node *np = spi_nor_get_flash_node(nor);
2539 params->quad_enable = spi_nor_sr2_bit1_quad_enable;
2540 params->set_4byte_addr_mode = spansion_set_4byte_addr_mode;
2541 params->otp.org = &info->otp_org;
2543 /* Default to 16-bit Write Status (01h) Command */
2544 nor->flags |= SNOR_F_HAS_16BIT_SR;
2546 /* Set SPI NOR sizes. */
2547 params->writesize = 1;
2548 params->size = (u64)info->sector_size * info->n_sectors;
2549 params->page_size = info->page_size;
2551 if (!(info->flags & SPI_NOR_NO_FR)) {
2552 /* Default to Fast Read for DT and non-DT platform devices. */
2553 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2555 /* Mask out Fast Read if not requested at DT instantiation. */
2556 if (np && !of_property_read_bool(np, "m25p,fast-read"))
2557 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2560 /* (Fast) Read settings. */
2561 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2562 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2563 0, 0, SPINOR_OP_READ,
2566 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
2567 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2568 0, 8, SPINOR_OP_READ_FAST,
2570 /* Page Program settings. */
2571 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2572 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2573 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2577 * spi_nor_init_params() - Initialize the flash's parameters and settings.
2578 * @nor: pointer to a 'struct spi_nor'.
2580 * The flash parameters and settings are initialized based on a sequence of
2581 * calls that are ordered by priority:
2583 * 1/ Default flash parameters initialization. The initializations are done
2584 * based on nor->info data:
2585 * spi_nor_info_init_params()
2587 * which can be overwritten by:
2588 * 2/ Manufacturer flash parameters initialization. The initializations are
2589 * done based on MFR register, or when the decisions can not be done solely
2590 * based on MFR, by using specific flash_info tweeks, ->default_init():
2591 * spi_nor_manufacturer_init_params()
2593 * which can be overwritten by:
2594 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
2595 * should be more accurate that the above.
2596 * spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params()
2598 * Please note that there is a ->post_bfpt() fixup hook that can overwrite
2599 * the flash parameters and settings immediately after parsing the Basic
2600 * Flash Parameter Table.
2601 * spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed.
2602 * It is used to tweak various flash parameters when information provided
2603 * by the SFDP tables are wrong.
2605 * which can be overwritten by:
2606 * 4/ Late flash parameters initialization, used to initialize flash
2607 * parameters that are not declared in the JESD216 SFDP standard, or where SFDP
2608 * tables are not defined at all.
2609 * spi_nor_late_init_params()
2611 * Return: 0 on success, -errno otherwise.
2613 static int spi_nor_init_params(struct spi_nor *nor)
2617 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
2621 spi_nor_init_default_params(nor);
2623 if (nor->info->parse_sfdp) {
2624 ret = spi_nor_parse_sfdp(nor);
2626 dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n");
2629 } else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) {
2630 spi_nor_no_sfdp_init_params(nor);
2632 spi_nor_init_params_deprecated(nor);
2635 spi_nor_late_init_params(nor);
2640 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
2641 * @nor: pointer to a 'struct spi_nor'
2642 * @enable: whether to enable or disable Octal DTR
2644 * Return: 0 on success, -errno otherwise.
2646 static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
2650 if (!nor->params->octal_dtr_enable)
2653 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
2654 nor->write_proto == SNOR_PROTO_8_8_8_DTR))
2657 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
2660 ret = nor->params->octal_dtr_enable(nor, enable);
2665 nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
2667 nor->reg_proto = SNOR_PROTO_1_1_1;
2673 * spi_nor_quad_enable() - enable Quad I/O if needed.
2674 * @nor: pointer to a 'struct spi_nor'
2676 * Return: 0 on success, -errno otherwise.
2678 static int spi_nor_quad_enable(struct spi_nor *nor)
2680 if (!nor->params->quad_enable)
2683 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2684 spi_nor_get_protocol_width(nor->write_proto) == 4))
2687 return nor->params->quad_enable(nor);
2690 static int spi_nor_init(struct spi_nor *nor)
2694 err = spi_nor_octal_dtr_enable(nor, true);
2696 dev_dbg(nor->dev, "octal mode not supported\n");
2700 err = spi_nor_quad_enable(nor);
2702 dev_dbg(nor->dev, "quad mode not supported\n");
2707 * Some SPI NOR flashes are write protected by default after a power-on
2708 * reset cycle, in order to avoid inadvertent writes during power-up.
2709 * Backward compatibility imposes to unlock the entire flash memory
2710 * array at power-up by default. Depending on the kernel configuration
2711 * (1) do nothing, (2) always unlock the entire flash array or (3)
2712 * unlock the entire flash array only when the software write
2713 * protection bits are volatile. The latter is indicated by
2714 * SNOR_F_SWP_IS_VOLATILE.
2716 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) ||
2717 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) &&
2718 nor->flags & SNOR_F_SWP_IS_VOLATILE))
2719 spi_nor_try_unlock_all(nor);
2721 if (nor->addr_width == 4 &&
2722 nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
2723 !(nor->flags & SNOR_F_4B_OPCODES)) {
2725 * If the RESET# pin isn't hooked up properly, or the system
2726 * otherwise doesn't perform a reset command in the boot
2727 * sequence, it's impossible to 100% protect against unexpected
2728 * reboots (e.g., crashes). Warn the user (or hopefully, system
2729 * designer) that this is bad.
2731 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
2732 "enabling reset hack; may not recover from unexpected reboots\n");
2733 nor->params->set_4byte_addr_mode(nor, true);
2740 * spi_nor_soft_reset() - Perform a software reset
2741 * @nor: pointer to 'struct spi_nor'
2743 * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets
2744 * the device to its power-on-reset state. This is useful when the software has
2745 * made some changes to device (volatile) registers and needs to reset it before
2746 * shutting down, for example.
2748 * Not every flash supports this sequence. The same set of opcodes might be used
2749 * for some other operation on a flash that does not support this. Support for
2750 * this sequence can be discovered via SFDP in the BFPT table.
2752 * Return: 0 on success, -errno otherwise.
2754 static void spi_nor_soft_reset(struct spi_nor *nor)
2756 struct spi_mem_op op;
2759 op = (struct spi_mem_op)SPINOR_SRSTEN_OP;
2761 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
2763 ret = spi_mem_exec_op(nor->spimem, &op);
2765 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
2769 op = (struct spi_mem_op)SPINOR_SRST_OP;
2771 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
2773 ret = spi_mem_exec_op(nor->spimem, &op);
2775 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
2780 * Software Reset is not instant, and the delay varies from flash to
2781 * flash. Looking at a few flashes, most range somewhere below 100
2782 * microseconds. So, sleep for a range of 200-400 us.
2784 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);
2787 /* mtd suspend handler */
2788 static int spi_nor_suspend(struct mtd_info *mtd)
2790 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2793 /* Disable octal DTR mode if we enabled it. */
2794 ret = spi_nor_octal_dtr_enable(nor, false);
2796 dev_err(nor->dev, "suspend() failed\n");
2801 /* mtd resume handler */
2802 static void spi_nor_resume(struct mtd_info *mtd)
2804 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2805 struct device *dev = nor->dev;
2808 /* re-initialize the nor chip */
2809 ret = spi_nor_init(nor);
2811 dev_err(dev, "resume() failed\n");
2814 static int spi_nor_get_device(struct mtd_info *mtd)
2816 struct mtd_info *master = mtd_get_master(mtd);
2817 struct spi_nor *nor = mtd_to_spi_nor(master);
2821 dev = nor->spimem->spi->controller->dev.parent;
2825 if (!try_module_get(dev->driver->owner))
2831 static void spi_nor_put_device(struct mtd_info *mtd)
2833 struct mtd_info *master = mtd_get_master(mtd);
2834 struct spi_nor *nor = mtd_to_spi_nor(master);
2838 dev = nor->spimem->spi->controller->dev.parent;
2842 module_put(dev->driver->owner);
2845 void spi_nor_restore(struct spi_nor *nor)
2847 /* restore the addressing mode */
2848 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
2849 nor->flags & SNOR_F_BROKEN_RESET)
2850 nor->params->set_4byte_addr_mode(nor, false);
2852 if (nor->flags & SNOR_F_SOFT_RESET)
2853 spi_nor_soft_reset(nor);
2855 EXPORT_SYMBOL_GPL(spi_nor_restore);
2857 static const struct flash_info *spi_nor_match_name(struct spi_nor *nor,
2862 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
2863 for (j = 0; j < manufacturers[i]->nparts; j++) {
2864 if (!strcmp(name, manufacturers[i]->parts[j].name)) {
2865 nor->manufacturer = manufacturers[i];
2866 return &manufacturers[i]->parts[j];
2874 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
2877 const struct flash_info *info = NULL;
2880 info = spi_nor_match_name(nor, name);
2881 /* Try to auto-detect if chip name wasn't specified or not found */
2883 return spi_nor_detect(nor);
2886 * If caller has specified name of flash model that can normally be
2887 * detected using JEDEC, let's verify it.
2889 if (name && info->id_len) {
2890 const struct flash_info *jinfo;
2892 jinfo = spi_nor_detect(nor);
2893 if (IS_ERR(jinfo)) {
2895 } else if (jinfo != info) {
2897 * JEDEC knows better, so overwrite platform ID. We
2898 * can't trust partitions any longer, but we'll let
2899 * mtd apply them anyway, since some partitions may be
2900 * marked read-only, and we don't want to lose that
2901 * information, even if it's not 100% accurate.
2903 dev_warn(nor->dev, "found %s, expected %s\n",
2904 jinfo->name, info->name);
2912 static void spi_nor_set_mtd_info(struct spi_nor *nor)
2914 struct mtd_info *mtd = &nor->mtd;
2915 struct device *dev = nor->dev;
2917 spi_nor_set_mtd_locking_ops(nor);
2918 spi_nor_set_mtd_otp_ops(nor);
2920 mtd->dev.parent = dev;
2922 mtd->name = dev_name(dev);
2923 mtd->type = MTD_NORFLASH;
2924 mtd->flags = MTD_CAP_NORFLASH;
2925 if (nor->info->flags & SPI_NOR_NO_ERASE)
2926 mtd->flags |= MTD_NO_ERASE;
2928 mtd->_erase = spi_nor_erase;
2929 mtd->writesize = nor->params->writesize;
2930 mtd->writebufsize = nor->params->page_size;
2931 mtd->size = nor->params->size;
2932 mtd->_read = spi_nor_read;
2933 /* Might be already set by some SST flashes. */
2935 mtd->_write = spi_nor_write;
2936 mtd->_suspend = spi_nor_suspend;
2937 mtd->_resume = spi_nor_resume;
2938 mtd->_get_device = spi_nor_get_device;
2939 mtd->_put_device = spi_nor_put_device;
2942 int spi_nor_scan(struct spi_nor *nor, const char *name,
2943 const struct spi_nor_hwcaps *hwcaps)
2945 const struct flash_info *info;
2946 struct device *dev = nor->dev;
2947 struct mtd_info *mtd = &nor->mtd;
2951 ret = spi_nor_check(nor);
2955 /* Reset SPI protocol for all commands. */
2956 nor->reg_proto = SNOR_PROTO_1_1_1;
2957 nor->read_proto = SNOR_PROTO_1_1_1;
2958 nor->write_proto = SNOR_PROTO_1_1_1;
2961 * We need the bounce buffer early to read/write registers when going
2962 * through the spi-mem layer (buffers have to be DMA-able).
2963 * For spi-mem drivers, we'll reallocate a new buffer if
2964 * nor->params->page_size turns out to be greater than PAGE_SIZE (which
2965 * shouldn't happen before long since NOR pages are usually less
2966 * than 1KB) after spi_nor_scan() returns.
2968 nor->bouncebuf_size = PAGE_SIZE;
2969 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
2971 if (!nor->bouncebuf)
2974 info = spi_nor_get_flash_info(nor, name);
2976 return PTR_ERR(info);
2980 mutex_init(&nor->lock);
2982 /* Init flash parameters based on flash_info struct and SFDP */
2983 ret = spi_nor_init_params(nor);
2988 * Configure the SPI memory:
2989 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2990 * - set the number of dummy cycles (mode cycles + wait states).
2991 * - set the SPI protocols for register and memory accesses.
2992 * - set the address width.
2994 ret = spi_nor_setup(nor, hwcaps);
2998 /* Send all the required SPI flash commands to initialize device */
2999 ret = spi_nor_init(nor);
3003 /* No mtd_info fields should be used up to this point. */
3004 spi_nor_set_mtd_info(nor);
3006 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
3007 (long long)mtd->size >> 10);
3010 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
3011 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
3012 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
3013 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
3015 if (mtd->numeraseregions)
3016 for (i = 0; i < mtd->numeraseregions; i++)
3018 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
3019 ".erasesize = 0x%.8x (%uKiB), "
3020 ".numblocks = %d }\n",
3021 i, (long long)mtd->eraseregions[i].offset,
3022 mtd->eraseregions[i].erasesize,
3023 mtd->eraseregions[i].erasesize / 1024,
3024 mtd->eraseregions[i].numblocks);
3027 EXPORT_SYMBOL_GPL(spi_nor_scan);
3029 static int spi_nor_create_read_dirmap(struct spi_nor *nor)
3031 struct spi_mem_dirmap_info info = {
3032 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
3033 SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
3034 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
3035 SPI_MEM_OP_DATA_IN(0, NULL, 0)),
3037 .length = nor->params->size,
3039 struct spi_mem_op *op = &info.op_tmpl;
3041 spi_nor_spimem_setup_op(nor, op, nor->read_proto);
3043 /* convert the dummy cycles to the number of bytes */
3044 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
3045 if (spi_nor_protocol_is_dtr(nor->read_proto))
3046 op->dummy.nbytes *= 2;
3049 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3050 * of data bytes is non-zero, the data buswidth won't be set here. So,
3053 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
3055 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3057 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);
3060 static int spi_nor_create_write_dirmap(struct spi_nor *nor)
3062 struct spi_mem_dirmap_info info = {
3063 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
3064 SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
3065 SPI_MEM_OP_NO_DUMMY,
3066 SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
3068 .length = nor->params->size,
3070 struct spi_mem_op *op = &info.op_tmpl;
3072 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
3073 op->addr.nbytes = 0;
3075 spi_nor_spimem_setup_op(nor, op, nor->write_proto);
3078 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3079 * of data bytes is non-zero, the data buswidth won't be set here. So,
3082 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
3084 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3086 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
3089 static int spi_nor_probe(struct spi_mem *spimem)
3091 struct spi_device *spi = spimem->spi;
3092 struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3093 struct spi_nor *nor;
3095 * Enable all caps by default. The core will mask them after
3096 * checking what's really supported using spi_mem_supports_op().
3098 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
3102 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3106 nor->spimem = spimem;
3107 nor->dev = &spi->dev;
3108 spi_nor_set_flash_node(nor, spi->dev.of_node);
3110 spi_mem_set_drvdata(spimem, nor);
3112 if (data && data->name)
3113 nor->mtd.name = data->name;
3116 nor->mtd.name = spi_mem_get_name(spimem);
3119 * For some (historical?) reason many platforms provide two different
3120 * names in flash_platform_data: "name" and "type". Quite often name is
3121 * set to "m25p80" and then "type" provides a real chip name.
3122 * If that's the case, respect "type" and ignore a "name".
3124 if (data && data->type)
3125 flash_name = data->type;
3126 else if (!strcmp(spi->modalias, "spi-nor"))
3127 flash_name = NULL; /* auto-detect */
3129 flash_name = spi->modalias;
3131 ret = spi_nor_scan(nor, flash_name, &hwcaps);
3136 * None of the existing parts have > 512B pages, but let's play safe
3137 * and add this logic so that if anyone ever adds support for such
3138 * a NOR we don't end up with buffer overflows.
3140 if (nor->params->page_size > PAGE_SIZE) {
3141 nor->bouncebuf_size = nor->params->page_size;
3142 devm_kfree(nor->dev, nor->bouncebuf);
3143 nor->bouncebuf = devm_kmalloc(nor->dev,
3144 nor->bouncebuf_size,
3146 if (!nor->bouncebuf)
3150 ret = spi_nor_create_read_dirmap(nor);
3154 ret = spi_nor_create_write_dirmap(nor);
3158 return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
3159 data ? data->nr_parts : 0);
3162 static int spi_nor_remove(struct spi_mem *spimem)
3164 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3166 spi_nor_restore(nor);
3168 /* Clean up MTD stuff. */
3169 return mtd_device_unregister(&nor->mtd);
3172 static void spi_nor_shutdown(struct spi_mem *spimem)
3174 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3176 spi_nor_restore(nor);
3180 * Do NOT add to this array without reading the following:
3182 * Historically, many flash devices are bound to this driver by their name. But
3183 * since most of these flash are compatible to some extent, and their
3184 * differences can often be differentiated by the JEDEC read-ID command, we
3185 * encourage new users to add support to the spi-nor library, and simply bind
3186 * against a generic string here (e.g., "jedec,spi-nor").
3188 * Many flash names are kept here in this list to keep them available
3189 * as module aliases for existing platforms.
3191 static const struct spi_device_id spi_nor_dev_ids[] = {
3193 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3194 * hack around the fact that the SPI core does not provide uevent
3195 * matching for .of_match_table
3200 * Entries not used in DTs that should be safe to drop after replacing
3201 * them with "spi-nor" in platform data.
3203 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
3206 * Entries that were used in DTs without "jedec,spi-nor" fallback and
3207 * should be kept for backward compatibility.
3209 {"at25df321a"}, {"at25df641"}, {"at26df081a"},
3210 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
3211 {"mx25l25635e"},{"mx66l51235l"},
3212 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
3213 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
3215 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
3216 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
3217 {"m25p64"}, {"m25p128"},
3218 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
3219 {"w25q80bl"}, {"w25q128"}, {"w25q256"},
3221 /* Flashes that can't be detected using JEDEC */
3222 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
3223 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
3224 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
3226 /* Everspin MRAMs (non-JEDEC) */
3227 { "mr25h128" }, /* 128 Kib, 40 MHz */
3228 { "mr25h256" }, /* 256 Kib, 40 MHz */
3229 { "mr25h10" }, /* 1 Mib, 40 MHz */
3230 { "mr25h40" }, /* 4 Mib, 40 MHz */
3234 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
3236 static const struct of_device_id spi_nor_of_table[] = {
3238 * Generic compatibility for SPI NOR that can be identified by the
3239 * JEDEC READ ID opcode (0x9F). Use this, if possible.
3241 { .compatible = "jedec,spi-nor" },
3244 MODULE_DEVICE_TABLE(of, spi_nor_of_table);
3247 * REVISIT: many of these chips have deep power-down modes, which
3248 * should clearly be entered on suspend() to minimize power use.
3249 * And also when they're otherwise idle...
3251 static struct spi_mem_driver spi_nor_driver = {
3255 .of_match_table = spi_nor_of_table,
3256 .dev_groups = spi_nor_sysfs_groups,
3258 .id_table = spi_nor_dev_ids,
3260 .probe = spi_nor_probe,
3261 .remove = spi_nor_remove,
3262 .shutdown = spi_nor_shutdown,
3264 module_spi_mem_driver(spi_nor_driver);
3266 MODULE_LICENSE("GPL v2");
3267 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3268 MODULE_AUTHOR("Mike Lavender");
3269 MODULE_DESCRIPTION("framework for SPI NOR");