drivers/mtd/spi-nor/cadence-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Cadence QSPI Controller
   4  *
   5  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   6  */
   7 #include <linux/clk.h>
   8 #include <linux/completion.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/jiffies.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/spi-nor.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/sched.h>
  27 #include <linux/spi/spi.h>
  28 #include <linux/timer.h>
  29
  30 #define CQSPI_NAME                      "cadence-qspi"
  31 #define CQSPI_MAX_CHIPSELECT            16
  32
  33 /* Quirks */
  34 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  35
  36 /* Capabilities mask */
  37 #define CQSPI_BASE_HWCAPS_MASK                                  \
  38         (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |             \
  39         SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 |       \
  40         SNOR_HWCAPS_PP)
  41
  42 struct cqspi_st;
  43
  44 struct cqspi_flash_pdata {
  45         struct spi_nor  nor;
  46         struct cqspi_st *cqspi;
  47         u32             clk_rate;
  48         u32             read_delay;
  49         u32             tshsl_ns;
  50         u32             tsd2d_ns;
  51         u32             tchsh_ns;
  52         u32             tslch_ns;
  53         u8              inst_width;
  54         u8              addr_width;
  55         u8              data_width;
  56         u8              cs;
  57         bool            registered;
  58         bool            use_direct_mode;
  59 };
  60
  61 struct cqspi_st {
  62         struct platform_device  *pdev;
  63
  64         struct clk              *clk;
  65         unsigned int            sclk;
  66
  67         void __iomem            *iobase;
  68         void __iomem            *ahb_base;
  69         resource_size_t         ahb_size;
  70         struct completion       transfer_complete;
  71         struct mutex            bus_mutex;
  72
  73         struct dma_chan         *rx_chan;
  74         struct completion       rx_dma_complete;
  75         dma_addr_t              mmap_phys_base;
  76
  77         int                     current_cs;
  78         int                     current_page_size;
  79         int                     current_erase_size;
  80         int                     current_addr_width;
  81         unsigned long           master_ref_clk_hz;
  82         bool                    is_decoded_cs;
  83         u32                     fifo_depth;
  84         u32                     fifo_width;
  85         bool                    rclk_en;
  86         u32                     trigger_address;
  87         u32                     wr_delay;
  88         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  89 };
  90
  91 struct cqspi_driver_platdata {
  92         u32 hwcaps_mask;
  93         u8 quirks;
  94 };
  95
  96 /* Operation timeout value */
  97 #define CQSPI_TIMEOUT_MS                        500
  98 #define CQSPI_READ_TIMEOUT_MS                   10
  99
 100 /* Instruction type */
 101 #define CQSPI_INST_TYPE_SINGLE                  0
 102 #define CQSPI_INST_TYPE_DUAL                    1
 103 #define CQSPI_INST_TYPE_QUAD                    2
 104 #define CQSPI_INST_TYPE_OCTAL                   3
 105
 106 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 107 #define CQSPI_DUMMY_BYTES_MAX                   4
 108 #define CQSPI_DUMMY_CLKS_MAX                    31
 109
 110 #define CQSPI_STIG_DATA_LEN_MAX                 8
 111
 112 /* Register map */
 113 #define CQSPI_REG_CONFIG                        0x00
 114 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 115 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 116 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 117 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 118 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 119 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 120 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 121 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 122 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 123
 124 #define CQSPI_REG_RD_INSTR                      0x04
 125 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 126 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 127 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 128 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 129 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 130 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 131 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 132 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 133 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 134 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 135
 136 #define CQSPI_REG_WR_INSTR                      0x08
 137 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 138 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 139 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 140
 141 #define CQSPI_REG_DELAY                         0x0C
 142 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 143 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 144 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 145 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 146 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 147 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 148 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 149 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 150
 151 #define CQSPI_REG_READCAPTURE                   0x10
 152 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 153 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 154 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 155
 156 #define CQSPI_REG_SIZE                          0x14
 157 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 158 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 159 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 160 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 161 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 162 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 163
 164 #define CQSPI_REG_SRAMPARTITION                 0x18
 165 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 166
 167 #define CQSPI_REG_DMA                           0x20
 168 #define CQSPI_REG_DMA_SINGLE_LSB                0
 169 #define CQSPI_REG_DMA_BURST_LSB                 8
 170 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 171 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 172
 173 #define CQSPI_REG_REMAP                         0x24
 174 #define CQSPI_REG_MODE_BIT                      0x28
 175
 176 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 177 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 178 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 179 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 180 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 181
 182 #define CQSPI_REG_IRQSTATUS                     0x40
 183 #define CQSPI_REG_IRQMASK                       0x44
 184
 185 #define CQSPI_REG_INDIRECTRD                    0x60
 186 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 187 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 188 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 189
 190 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 191 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 192 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 193
 194 #define CQSPI_REG_CMDCTRL                       0x90
 195 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 196 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 197 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 198 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 199 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 200 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 201 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 202 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 203 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 204 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 205 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 206 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 207
 208 #define CQSPI_REG_INDIRECTWR                    0x70
 209 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 210 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 211 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 212
 213 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 214 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 215 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 216
 217 #define CQSPI_REG_CMDADDRESS                    0x94
 218 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 219 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 220 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 221 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 222
 223 /* Interrupt status bits */
 224 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 225 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 226 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 227 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 228 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 229 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 230 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 231 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 232
 233 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 234                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 235                                          CQSPI_REG_IRQ_IND_COMP)
 236
 237 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 238                                          CQSPI_REG_IRQ_WATERMARK        | \
 239                                          CQSPI_REG_IRQ_UNDERFLOW)
 240
 241 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 242
 243 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 244 {
 245         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 246         u32 val;
 247
 248         while (1) {
 249                 val = readl(reg);
 250                 if (clear)
 251                         val = ~val;
 252                 val &= mask;
 253
 254                 if (val == mask)
 255                         return 0;
 256
 257                 if (time_after(jiffies, end))
 258                         return -ETIMEDOUT;
 259         }
 260 }
 261
 262 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 263 {
 264         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 265
 266         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 267 }
 268
 269 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 270 {
 271         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 272
 273         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 274         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 275 }
 276
 277 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 278 {
 279         struct cqspi_st *cqspi = dev;
 280         unsigned int irq_status;
 281
 282         /* Read interrupt status */
 283         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 284
 285         /* Clear interrupt */
 286         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 287
 288         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 289
 290         if (irq_status)
 291                 complete(&cqspi->transfer_complete);
 292
 293         return IRQ_HANDLED;
 294 }
 295
 296 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 297 {
 298         struct cqspi_flash_pdata *f_pdata = nor->priv;
 299         u32 rdreg = 0;
 300
 301         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 302         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 303         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 304
 305         return rdreg;
 306 }
 307
 308 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 309 {
 310         const unsigned int poll_idle_retry = 3;
 311         unsigned int count = 0;
 312         unsigned long timeout;
 313
 314         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 315         while (1) {
 316                 /*
 317                  * Read few times in succession to ensure the controller
 318                  * is indeed idle, that is, the bit does not transition
 319                  * low again.
 320                  */
 321                 if (cqspi_is_idle(cqspi))
 322                         count++;
 323                 else
 324                         count = 0;
 325
 326                 if (count >= poll_idle_retry)
 327                         return 0;
 328
 329                 if (time_after(jiffies, timeout)) {
 330                         /* Timeout, in busy mode. */
 331                         dev_err(&cqspi->pdev->dev,
 332                                 "QSPI is still busy after %dms timeout.\n",
 333                                 CQSPI_TIMEOUT_MS);
 334                         return -ETIMEDOUT;
 335                 }
 336
 337                 cpu_relax();
 338         }
 339 }
 340
 341 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 342 {
 343         void __iomem *reg_base = cqspi->iobase;
 344         int ret;
 345
 346         /* Write the CMDCTRL without start execution. */
 347         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 348         /* Start execute */
 349         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 350         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 351
 352         /* Polling for completion. */
 353         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 354                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 355         if (ret) {
 356                 dev_err(&cqspi->pdev->dev,
 357                         "Flash command execution timed out.\n");
 358                 return ret;
 359         }
 360
 361         /* Polling QSPI idle status. */
 362         return cqspi_wait_idle(cqspi);
 363 }
 364
 365 static int cqspi_command_read(struct spi_nor *nor,
 366                               const u8 *txbuf, const unsigned n_tx,
 367                               u8 *rxbuf, const unsigned n_rx)
 368 {
 369         struct cqspi_flash_pdata *f_pdata = nor->priv;
 370         struct cqspi_st *cqspi = f_pdata->cqspi;
 371         void __iomem *reg_base = cqspi->iobase;
 372         unsigned int rdreg;
 373         unsigned int reg;
 374         unsigned int read_len;
 375         int status;
 376
 377         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 378                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 379                         n_rx, rxbuf);
 380                 return -EINVAL;
 381         }
 382
 383         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 384
 385         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 386         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 387
 388         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 389
 390         /* 0 means 1 byte. */
 391         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 392                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 393         status = cqspi_exec_flash_cmd(cqspi, reg);
 394         if (status)
 395                 return status;
 396
 397         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 398
 399         /* Put the read value into rx_buf */
 400         read_len = (n_rx > 4) ? 4 : n_rx;
 401         memcpy(rxbuf, &reg, read_len);
 402         rxbuf += read_len;
 403
 404         if (n_rx > 4) {
 405                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 406
 407                 read_len = n_rx - read_len;
 408                 memcpy(rxbuf, &reg, read_len);
 409         }
 410
 411         return 0;
 412 }
 413
 414 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 415                                const u8 *txbuf, const unsigned n_tx)
 416 {
 417         struct cqspi_flash_pdata *f_pdata = nor->priv;
 418         struct cqspi_st *cqspi = f_pdata->cqspi;
 419         void __iomem *reg_base = cqspi->iobase;
 420         unsigned int reg;
 421         unsigned int data;
 422         u32 write_len;
 423         int ret;
 424
 425         if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 426                 dev_err(nor->dev,
 427                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 428                         n_tx, txbuf);
 429                 return -EINVAL;
 430         }
 431
 432         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 433         if (n_tx) {
 434                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 435                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 436                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 437                 data = 0;
 438                 write_len = (n_tx > 4) ? 4 : n_tx;
 439                 memcpy(&data, txbuf, write_len);
 440                 txbuf += write_len;
 441                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 442
 443                 if (n_tx > 4) {
 444                         data = 0;
 445                         write_len = n_tx - 4;
 446                         memcpy(&data, txbuf, write_len);
 447                         writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 448                 }
 449         }
 450         ret = cqspi_exec_flash_cmd(cqspi, reg);
 451         return ret;
 452 }
 453
 454 static int cqspi_command_write_addr(struct spi_nor *nor,
 455                                     const u8 opcode, const unsigned int addr)
 456 {
 457         struct cqspi_flash_pdata *f_pdata = nor->priv;
 458         struct cqspi_st *cqspi = f_pdata->cqspi;
 459         void __iomem *reg_base = cqspi->iobase;
 460         unsigned int reg;
 461
 462         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 463         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 464         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 465                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 466
 467         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 468
 469         return cqspi_exec_flash_cmd(cqspi, reg);
 470 }
 471
 472 static int cqspi_read_setup(struct spi_nor *nor)
 473 {
 474         struct cqspi_flash_pdata *f_pdata = nor->priv;
 475         struct cqspi_st *cqspi = f_pdata->cqspi;
 476         void __iomem *reg_base = cqspi->iobase;
 477         unsigned int dummy_clk = 0;
 478         unsigned int reg;
 479
 480         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 481         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 482
 483         /* Setup dummy clock cycles */
 484         dummy_clk = nor->read_dummy;
 485         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 486                 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
 487
 488         if (dummy_clk / 8) {
 489                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 490                 /* Set mode bits high to ensure chip doesn't enter XIP */
 491                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 492
 493                 /* Need to subtract the mode byte (8 clocks). */
 494                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 495                         dummy_clk -= 8;
 496
 497                 if (dummy_clk)
 498                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 499                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 500         }
 501
 502         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 503
 504         /* Set address width */
 505         reg = readl(reg_base + CQSPI_REG_SIZE);
 506         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 507         reg |= (nor->addr_width - 1);
 508         writel(reg, reg_base + CQSPI_REG_SIZE);
 509         return 0;
 510 }
 511
 512 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
 513                                        loff_t from_addr, const size_t n_rx)
 514 {
 515         struct cqspi_flash_pdata *f_pdata = nor->priv;
 516         struct cqspi_st *cqspi = f_pdata->cqspi;
 517         void __iomem *reg_base = cqspi->iobase;
 518         void __iomem *ahb_base = cqspi->ahb_base;
 519         unsigned int remaining = n_rx;
 520         unsigned int mod_bytes = n_rx % 4;
 521         unsigned int bytes_to_read = 0;
 522         u8 *rxbuf_end = rxbuf + n_rx;
 523         int ret = 0;
 524
 525         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 526         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 527
 528         /* Clear all interrupts. */
 529         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 530
 531         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 532
 533         reinit_completion(&cqspi->transfer_complete);
 534         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 535                reg_base + CQSPI_REG_INDIRECTRD);
 536
 537         while (remaining > 0) {
 538                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 539                                 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 540                         ret = -ETIMEDOUT;
 541
 542                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 543
 544                 if (ret && bytes_to_read == 0) {
 545                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 546                         goto failrd;
 547                 }
 548
 549                 while (bytes_to_read != 0) {
 550                         unsigned int word_remain = round_down(remaining, 4);
 551
 552                         bytes_to_read *= cqspi->fifo_width;
 553                         bytes_to_read = bytes_to_read > remaining ?
 554                                         remaining : bytes_to_read;
 555                         bytes_to_read = round_down(bytes_to_read, 4);
 556                         /* Read 4 byte word chunks then single bytes */
 557                         if (bytes_to_read) {
 558                                 ioread32_rep(ahb_base, rxbuf,
 559                                              (bytes_to_read / 4));
 560                         } else if (!word_remain && mod_bytes) {
 561                                 unsigned int temp = ioread32(ahb_base);
 562
 563                                 bytes_to_read = mod_bytes;
 564                                 memcpy(rxbuf, &temp, min((unsigned int)
 565                                                          (rxbuf_end - rxbuf),
 566                                                          bytes_to_read));
 567                         }
 568                         rxbuf += bytes_to_read;
 569                         remaining -= bytes_to_read;
 570                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 571                 }
 572
 573                 if (remaining > 0)
 574                         reinit_completion(&cqspi->transfer_complete);
 575         }
 576
 577         /* Check indirect done status */
 578         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 579                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 580         if (ret) {
 581                 dev_err(nor->dev,
 582                         "Indirect read completion error (%i)\n", ret);
 583                 goto failrd;
 584         }
 585
 586         /* Disable interrupt */
 587         writel(0, reg_base + CQSPI_REG_IRQMASK);
 588
 589         /* Clear indirect completion status */
 590         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 591
 592         return 0;
 593
 594 failrd:
 595         /* Disable interrupt */
 596         writel(0, reg_base + CQSPI_REG_IRQMASK);
 597
 598         /* Cancel the indirect read */
 599         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 600                reg_base + CQSPI_REG_INDIRECTRD);
 601         return ret;
 602 }
 603
 604 static int cqspi_write_setup(struct spi_nor *nor)
 605 {
 606         unsigned int reg;
 607         struct cqspi_flash_pdata *f_pdata = nor->priv;
 608         struct cqspi_st *cqspi = f_pdata->cqspi;
 609         void __iomem *reg_base = cqspi->iobase;
 610
 611         /* Set opcode. */
 612         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 613         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 614         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 615         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 616
 617         reg = readl(reg_base + CQSPI_REG_SIZE);
 618         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 619         reg |= (nor->addr_width - 1);
 620         writel(reg, reg_base + CQSPI_REG_SIZE);
 621         return 0;
 622 }
 623
 624 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
 625                                         const u8 *txbuf, const size_t n_tx)
 626 {
 627         const unsigned int page_size = nor->page_size;
 628         struct cqspi_flash_pdata *f_pdata = nor->priv;
 629         struct cqspi_st *cqspi = f_pdata->cqspi;
 630         void __iomem *reg_base = cqspi->iobase;
 631         unsigned int remaining = n_tx;
 632         unsigned int write_bytes;
 633         int ret;
 634
 635         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 636         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 637
 638         /* Clear all interrupts. */
 639         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 640
 641         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 642
 643         reinit_completion(&cqspi->transfer_complete);
 644         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 645                reg_base + CQSPI_REG_INDIRECTWR);
 646         /*
 647          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 648          * Controller programming sequence, couple of cycles of
 649          * QSPI_REF_CLK delay is required for the above bit to
 650          * be internally synchronized by the QSPI module. Provide 5
 651          * cycles of delay.
 652          */
 653         if (cqspi->wr_delay)
 654                 ndelay(cqspi->wr_delay);
 655
 656         while (remaining > 0) {
 657                 size_t write_words, mod_bytes;
 658
 659                 write_bytes = remaining > page_size ? page_size : remaining;
 660                 write_words = write_bytes / 4;
 661                 mod_bytes = write_bytes % 4;
 662                 /* Write 4 bytes at a time then single bytes. */
 663                 if (write_words) {
 664                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
 665                         txbuf += (write_words * 4);
 666                 }
 667                 if (mod_bytes) {
 668                         unsigned int temp = 0xFFFFFFFF;
 669
 670                         memcpy(&temp, txbuf, mod_bytes);
 671                         iowrite32(temp, cqspi->ahb_base);
 672                         txbuf += mod_bytes;
 673                 }
 674
 675                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 676                                         msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
 677                         dev_err(nor->dev, "Indirect write timeout\n");
 678                         ret = -ETIMEDOUT;
 679                         goto failwr;
 680                 }
 681
 682                 remaining -= write_bytes;
 683
 684                 if (remaining > 0)
 685                         reinit_completion(&cqspi->transfer_complete);
 686         }
 687
 688         /* Check indirect done status */
 689         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 690                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 691         if (ret) {
 692                 dev_err(nor->dev,
 693                         "Indirect write completion error (%i)\n", ret);
 694                 goto failwr;
 695         }
 696
 697         /* Disable interrupt. */
 698         writel(0, reg_base + CQSPI_REG_IRQMASK);
 699
 700         /* Clear indirect completion status */
 701         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 702
 703         cqspi_wait_idle(cqspi);
 704
 705         return 0;
 706
 707 failwr:
 708         /* Disable interrupt. */
 709         writel(0, reg_base + CQSPI_REG_IRQMASK);
 710
 711         /* Cancel the indirect write */
 712         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 713                reg_base + CQSPI_REG_INDIRECTWR);
 714         return ret;
 715 }
 716
 717 static void cqspi_chipselect(struct spi_nor *nor)
 718 {
 719         struct cqspi_flash_pdata *f_pdata = nor->priv;
 720         struct cqspi_st *cqspi = f_pdata->cqspi;
 721         void __iomem *reg_base = cqspi->iobase;
 722         unsigned int chip_select = f_pdata->cs;
 723         unsigned int reg;
 724
 725         reg = readl(reg_base + CQSPI_REG_CONFIG);
 726         if (cqspi->is_decoded_cs) {
 727                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 728         } else {
 729                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 730
 731                 /* Convert CS if without decoder.
 732                  * CS0 to 4b'1110
 733                  * CS1 to 4b'1101
 734                  * CS2 to 4b'1011
 735                  * CS3 to 4b'0111
 736                  */
 737                 chip_select = 0xF & ~(1 << chip_select);
 738         }
 739
 740         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 741                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 742         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 743             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 744         writel(reg, reg_base + CQSPI_REG_CONFIG);
 745 }
 746
 747 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
 748 {
 749         struct cqspi_flash_pdata *f_pdata = nor->priv;
 750         struct cqspi_st *cqspi = f_pdata->cqspi;
 751         void __iomem *iobase = cqspi->iobase;
 752         unsigned int reg;
 753
 754         /* configure page size and block size. */
 755         reg = readl(iobase + CQSPI_REG_SIZE);
 756         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 757         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 758         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 759         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 760         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
 761         reg |= (nor->addr_width - 1);
 762         writel(reg, iobase + CQSPI_REG_SIZE);
 763
 764         /* configure the chip select */
 765         cqspi_chipselect(nor);
 766
 767         /* Store the new configuration of the controller */
 768         cqspi->current_page_size = nor->page_size;
 769         cqspi->current_erase_size = nor->mtd.erasesize;
 770         cqspi->current_addr_width = nor->addr_width;
 771 }
 772
 773 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 774                                            const unsigned int ns_val)
 775 {
 776         unsigned int ticks;
 777
 778         ticks = ref_clk_hz / 1000;      /* kHz */
 779         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 780
 781         return ticks;
 782 }
 783
 784 static void cqspi_delay(struct spi_nor *nor)
 785 {
 786         struct cqspi_flash_pdata *f_pdata = nor->priv;
 787         struct cqspi_st *cqspi = f_pdata->cqspi;
 788         void __iomem *iobase = cqspi->iobase;
 789         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 790         unsigned int tshsl, tchsh, tslch, tsd2d;
 791         unsigned int reg;
 792         unsigned int tsclk;
 793
 794         /* calculate the number of ref ticks for one sclk tick */
 795         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 796
 797         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 798         /* this particular value must be at least one sclk */
 799         if (tshsl < tsclk)
 800                 tshsl = tsclk;
 801
 802         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 803         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 804         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 805
 806         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 807                << CQSPI_REG_DELAY_TSHSL_LSB;
 808         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 809                 << CQSPI_REG_DELAY_TCHSH_LSB;
 810         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 811                 << CQSPI_REG_DELAY_TSLCH_LSB;
 812         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 813                 << CQSPI_REG_DELAY_TSD2D_LSB;
 814         writel(reg, iobase + CQSPI_REG_DELAY);
 815 }
 816
 817 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 818 {
 819         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 820         void __iomem *reg_base = cqspi->iobase;
 821         u32 reg, div;
 822
 823         /* Recalculate the baudrate divisor based on QSPI specification. */
 824         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 825
 826         reg = readl(reg_base + CQSPI_REG_CONFIG);
 827         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 828         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 829         writel(reg, reg_base + CQSPI_REG_CONFIG);
 830 }
 831
 832 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 833                                    const bool bypass,
 834                                    const unsigned int delay)
 835 {
 836         void __iomem *reg_base = cqspi->iobase;
 837         unsigned int reg;
 838
 839         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 840
 841         if (bypass)
 842                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 843         else
 844                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 845
 846         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 847                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 848
 849         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 850                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 851
 852         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 853 }
 854
 855 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 856 {
 857         void __iomem *reg_base = cqspi->iobase;
 858         unsigned int reg;
 859
 860         reg = readl(reg_base + CQSPI_REG_CONFIG);
 861
 862         if (enable)
 863                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 864         else
 865                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 866
 867         writel(reg, reg_base + CQSPI_REG_CONFIG);
 868 }
 869
 870 static void cqspi_configure(struct spi_nor *nor)
 871 {
 872         struct cqspi_flash_pdata *f_pdata = nor->priv;
 873         struct cqspi_st *cqspi = f_pdata->cqspi;
 874         const unsigned int sclk = f_pdata->clk_rate;
 875         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 876         int switch_ck = (cqspi->sclk != sclk);
 877
 878         if ((cqspi->current_page_size != nor->page_size) ||
 879             (cqspi->current_erase_size != nor->mtd.erasesize) ||
 880             (cqspi->current_addr_width != nor->addr_width))
 881                 switch_cs = 1;
 882
 883         if (switch_cs || switch_ck)
 884                 cqspi_controller_enable(cqspi, 0);
 885
 886         /* Switch chip select. */
 887         if (switch_cs) {
 888                 cqspi->current_cs = f_pdata->cs;
 889                 cqspi_configure_cs_and_sizes(nor);
 890         }
 891
 892         /* Setup baudrate divisor and delays */
 893         if (switch_ck) {
 894                 cqspi->sclk = sclk;
 895                 cqspi_config_baudrate_div(cqspi);
 896                 cqspi_delay(nor);
 897                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
 898                                        f_pdata->read_delay);
 899         }
 900
 901         if (switch_cs || switch_ck)
 902                 cqspi_controller_enable(cqspi, 1);
 903 }
 904
 905 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 906 {
 907         struct cqspi_flash_pdata *f_pdata = nor->priv;
 908
 909         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 910         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 911         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 912
 913         if (read) {
 914                 switch (nor->read_proto) {
 915                 case SNOR_PROTO_1_1_1:
 916                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 917                         break;
 918                 case SNOR_PROTO_1_1_2:
 919                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 920                         break;
 921                 case SNOR_PROTO_1_1_4:
 922                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 923                         break;
 924                 case SNOR_PROTO_1_1_8:
 925                         f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
 926                         break;
 927                 default:
 928                         return -EINVAL;
 929                 }
 930         }
 931
 932         cqspi_configure(nor);
 933
 934         return 0;
 935 }
 936
 937 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 938                            size_t len, const u_char *buf)
 939 {
 940         struct cqspi_flash_pdata *f_pdata = nor->priv;
 941         struct cqspi_st *cqspi = f_pdata->cqspi;
 942         int ret;
 943
 944         ret = cqspi_set_protocol(nor, 0);
 945         if (ret)
 946                 return ret;
 947
 948         ret = cqspi_write_setup(nor);
 949         if (ret)
 950                 return ret;
 951
 952         if (f_pdata->use_direct_mode) {
 953                 memcpy_toio(cqspi->ahb_base + to, buf, len);
 954                 ret = cqspi_wait_idle(cqspi);
 955         } else {
 956                 ret = cqspi_indirect_write_execute(nor, to, buf, len);
 957         }
 958         if (ret)
 959                 return ret;
 960
 961         return len;
 962 }
 963
 964 static void cqspi_rx_dma_callback(void *param)
 965 {
 966         struct cqspi_st *cqspi = param;
 967
 968         complete(&cqspi->rx_dma_complete);
 969 }
 970
 971 static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
 972                                      loff_t from, size_t len)
 973 {
 974         struct cqspi_flash_pdata *f_pdata = nor->priv;
 975         struct cqspi_st *cqspi = f_pdata->cqspi;
 976         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 977         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
 978         int ret = 0;
 979         struct dma_async_tx_descriptor *tx;
 980         dma_cookie_t cookie;
 981         dma_addr_t dma_dst;
 982
 983         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
 984                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
 985                 return 0;
 986         }
 987
 988         dma_dst = dma_map_single(nor->dev, buf, len, DMA_FROM_DEVICE);
 989         if (dma_mapping_error(nor->dev, dma_dst)) {
 990                 dev_err(nor->dev, "dma mapping failed\n");
 991                 return -ENOMEM;
 992         }
 993         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
 994                                        len, flags);
 995         if (!tx) {
 996                 dev_err(nor->dev, "device_prep_dma_memcpy error\n");
 997                 ret = -EIO;
 998                 goto err_unmap;
 999         }
1000
1001         tx->callback = cqspi_rx_dma_callback;
1002         tx->callback_param = cqspi;
1003         cookie = tx->tx_submit(tx);
1004         reinit_completion(&cqspi->rx_dma_complete);
1005
1006         ret = dma_submit_error(cookie);
1007         if (ret) {
1008                 dev_err(nor->dev, "dma_submit_error %d\n", cookie);
1009                 ret = -EIO;
1010                 goto err_unmap;
1011         }
1012
1013         dma_async_issue_pending(cqspi->rx_chan);
1014         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1015                                          msecs_to_jiffies(len))) {
1016                 dmaengine_terminate_sync(cqspi->rx_chan);
1017                 dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
1018                 ret = -ETIMEDOUT;
1019                 goto err_unmap;
1020         }
1021
1022 err_unmap:
1023         dma_unmap_single(nor->dev, dma_dst, len, DMA_FROM_DEVICE);
1024
1025         return ret;
1026 }
1027
1028 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
1029                           size_t len, u_char *buf)
1030 {
1031         struct cqspi_flash_pdata *f_pdata = nor->priv;
1032         int ret;
1033
1034         ret = cqspi_set_protocol(nor, 1);
1035         if (ret)
1036                 return ret;
1037
1038         ret = cqspi_read_setup(nor);
1039         if (ret)
1040                 return ret;
1041
1042         if (f_pdata->use_direct_mode)
1043                 ret = cqspi_direct_read_execute(nor, buf, from, len);
1044         else
1045                 ret = cqspi_indirect_read_execute(nor, buf, from, len);
1046         if (ret)
1047                 return ret;
1048
1049         return len;
1050 }
1051
1052 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
1053 {
1054         int ret;
1055
1056         ret = cqspi_set_protocol(nor, 0);
1057         if (ret)
1058                 return ret;
1059
1060         /* Send write enable, then erase commands. */
1061         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
1062         if (ret)
1063                 return ret;
1064
1065         /* Set up command buffer. */
1066         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
1067         if (ret)
1068                 return ret;
1069
1070         return 0;
1071 }
1072
1073 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1074 {
1075         struct cqspi_flash_pdata *f_pdata = nor->priv;
1076         struct cqspi_st *cqspi = f_pdata->cqspi;
1077
1078         mutex_lock(&cqspi->bus_mutex);
1079
1080         return 0;
1081 }
1082
1083 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1084 {
1085         struct cqspi_flash_pdata *f_pdata = nor->priv;
1086         struct cqspi_st *cqspi = f_pdata->cqspi;
1087
1088         mutex_unlock(&cqspi->bus_mutex);
1089 }
1090
1091 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1092 {
1093         int ret;
1094
1095         ret = cqspi_set_protocol(nor, 0);
1096         if (!ret)
1097                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1098
1099         return ret;
1100 }
1101
1102 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1103 {
1104         int ret;
1105
1106         ret = cqspi_set_protocol(nor, 0);
1107         if (!ret)
1108                 ret = cqspi_command_write(nor, opcode, buf, len);
1109
1110         return ret;
1111 }
1112
1113 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1114                                     struct cqspi_flash_pdata *f_pdata,
1115                                     struct device_node *np)
1116 {
1117         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1118                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1119                 return -ENXIO;
1120         }
1121
1122         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1123                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1124                 return -ENXIO;
1125         }
1126
1127         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1128                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1129                 return -ENXIO;
1130         }
1131
1132         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1133                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1134                 return -ENXIO;
1135         }
1136
1137         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1138                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1139                 return -ENXIO;
1140         }
1141
1142         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1143                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1144                 return -ENXIO;
1145         }
1146
1147         return 0;
1148 }
1149
1150 static int cqspi_of_get_pdata(struct platform_device *pdev)
1151 {
1152         struct device_node *np = pdev->dev.of_node;
1153         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1154
1155         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1156
1157         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1158                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1159                 return -ENXIO;
1160         }
1161
1162         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1163                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1164                 return -ENXIO;
1165         }
1166
1167         if (of_property_read_u32(np, "cdns,trigger-address",
1168                                  &cqspi->trigger_address)) {
1169                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1170                 return -ENXIO;
1171         }
1172
1173         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1174
1175         return 0;
1176 }
1177
1178 static void cqspi_controller_init(struct cqspi_st *cqspi)
1179 {
1180         u32 reg;
1181
1182         cqspi_controller_enable(cqspi, 0);
1183
1184         /* Configure the remap address register, no remap */
1185         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1186
1187         /* Disable all interrupts. */
1188         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1189
1190         /* Configure the SRAM split to 1:1 . */
1191         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1192
1193         /* Load indirect trigger address. */
1194         writel(cqspi->trigger_address,
1195                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1196
1197         /* Program read watermark -- 1/2 of the FIFO. */
1198         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1199                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1200         /* Program write watermark -- 1/8 of the FIFO. */
1201         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1202                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1203
1204         /* Enable Direct Access Controller */
1205         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1206         reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1207         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1208
1209         cqspi_controller_enable(cqspi, 1);
1210 }
1211
1212 static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1213 {
1214         dma_cap_mask_t mask;
1215
1216         dma_cap_zero(mask);
1217         dma_cap_set(DMA_MEMCPY, mask);
1218
1219         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1220         if (IS_ERR(cqspi->rx_chan)) {
1221                 dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
1222                 cqspi->rx_chan = NULL;
1223         }
1224         init_completion(&cqspi->rx_dma_complete);
1225 }
1226
1227 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1228 {
1229         struct platform_device *pdev = cqspi->pdev;
1230         struct device *dev = &pdev->dev;
1231         const struct cqspi_driver_platdata *ddata;
1232         struct spi_nor_hwcaps hwcaps;
1233         struct cqspi_flash_pdata *f_pdata;
1234         struct spi_nor *nor;
1235         struct mtd_info *mtd;
1236         unsigned int cs;
1237         int i, ret;
1238
1239         ddata = of_device_get_match_data(dev);
1240         if (!ddata) {
1241                 dev_err(dev, "Couldn't find driver data\n");
1242                 return -EINVAL;
1243         }
1244         hwcaps.mask = ddata->hwcaps_mask;
1245
1246         /* Get flash device data */
1247         for_each_available_child_of_node(dev->of_node, np) {
1248                 ret = of_property_read_u32(np, "reg", &cs);
1249                 if (ret) {
1250                         dev_err(dev, "Couldn't determine chip select.\n");
1251                         goto err;
1252                 }
1253
1254                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1255                         ret = -EINVAL;
1256                         dev_err(dev, "Chip select %d out of range.\n", cs);
1257                         goto err;
1258                 }
1259
1260                 f_pdata = &cqspi->f_pdata[cs];
1261                 f_pdata->cqspi = cqspi;
1262                 f_pdata->cs = cs;
1263
1264                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1265                 if (ret)
1266                         goto err;
1267
1268                 nor = &f_pdata->nor;
1269                 mtd = &nor->mtd;
1270
1271                 mtd->priv = nor;
1272
1273                 nor->dev = dev;
1274                 spi_nor_set_flash_node(nor, np);
1275                 nor->priv = f_pdata;
1276
1277                 nor->read_reg = cqspi_read_reg;
1278                 nor->write_reg = cqspi_write_reg;
1279                 nor->read = cqspi_read;
1280                 nor->write = cqspi_write;
1281                 nor->erase = cqspi_erase;
1282                 nor->prepare = cqspi_prep;
1283                 nor->unprepare = cqspi_unprep;
1284
1285                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1286                                            dev_name(dev), cs);
1287                 if (!mtd->name) {
1288                         ret = -ENOMEM;
1289                         goto err;
1290                 }
1291
1292                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1293                 if (ret)
1294                         goto err;
1295
1296                 ret = mtd_device_register(mtd, NULL, 0);
1297                 if (ret)
1298                         goto err;
1299
1300                 f_pdata->registered = true;
1301
1302                 if (mtd->size <= cqspi->ahb_size) {
1303                         f_pdata->use_direct_mode = true;
1304                         dev_dbg(nor->dev, "using direct mode for %s\n",
1305                                 mtd->name);
1306
1307                         if (!cqspi->rx_chan)
1308                                 cqspi_request_mmap_dma(cqspi);
1309                 }
1310         }
1311
1312         return 0;
1313
1314 err:
1315         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1316                 if (cqspi->f_pdata[i].registered)
1317                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1318         return ret;
1319 }
1320
1321 static int cqspi_probe(struct platform_device *pdev)
1322 {
1323         struct device_node *np = pdev->dev.of_node;
1324         struct device *dev = &pdev->dev;
1325         struct cqspi_st *cqspi;
1326         struct resource *res;
1327         struct resource *res_ahb;
1328         const struct cqspi_driver_platdata *ddata;
1329         int ret;
1330         int irq;
1331
1332         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1333         if (!cqspi)
1334                 return -ENOMEM;
1335
1336         mutex_init(&cqspi->bus_mutex);
1337         cqspi->pdev = pdev;
1338         platform_set_drvdata(pdev, cqspi);
1339
1340         /* Obtain configuration from OF. */
1341         ret = cqspi_of_get_pdata(pdev);
1342         if (ret) {
1343                 dev_err(dev, "Cannot get mandatory OF data.\n");
1344                 return -ENODEV;
1345         }
1346
1347         /* Obtain QSPI clock. */
1348         cqspi->clk = devm_clk_get(dev, NULL);
1349         if (IS_ERR(cqspi->clk)) {
1350                 dev_err(dev, "Cannot claim QSPI clock.\n");
1351                 return PTR_ERR(cqspi->clk);
1352         }
1353
1354         /* Obtain and remap controller address. */
1355         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356         cqspi->iobase = devm_ioremap_resource(dev, res);
1357         if (IS_ERR(cqspi->iobase)) {
1358                 dev_err(dev, "Cannot remap controller address.\n");
1359                 return PTR_ERR(cqspi->iobase);
1360         }
1361
1362         /* Obtain and remap AHB address. */
1363         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1364         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1365         if (IS_ERR(cqspi->ahb_base)) {
1366                 dev_err(dev, "Cannot remap AHB address.\n");
1367                 return PTR_ERR(cqspi->ahb_base);
1368         }
1369         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1370         cqspi->ahb_size = resource_size(res_ahb);
1371
1372         init_completion(&cqspi->transfer_complete);
1373
1374         /* Obtain IRQ line. */
1375         irq = platform_get_irq(pdev, 0);
1376         if (irq < 0) {
1377                 dev_err(dev, "Cannot obtain IRQ.\n");
1378                 return -ENXIO;
1379         }
1380
1381         pm_runtime_enable(dev);
1382         ret = pm_runtime_get_sync(dev);
1383         if (ret < 0) {
1384                 pm_runtime_put_noidle(dev);
1385                 return ret;
1386         }
1387
1388         ret = clk_prepare_enable(cqspi->clk);
1389         if (ret) {
1390                 dev_err(dev, "Cannot enable QSPI clock.\n");
1391                 goto probe_clk_failed;
1392         }
1393
1394         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1395         ddata  = of_device_get_match_data(dev);
1396         if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
1397                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1398                                                    cqspi->master_ref_clk_hz);
1399
1400         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1401                                pdev->name, cqspi);
1402         if (ret) {
1403                 dev_err(dev, "Cannot request IRQ.\n");
1404                 goto probe_irq_failed;
1405         }
1406
1407         cqspi_wait_idle(cqspi);
1408         cqspi_controller_init(cqspi);
1409         cqspi->current_cs = -1;
1410         cqspi->sclk = 0;
1411
1412         ret = cqspi_setup_flash(cqspi, np);
1413         if (ret) {
1414                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1415                 goto probe_setup_failed;
1416         }
1417
1418         return ret;
1419 probe_setup_failed:
1420         cqspi_controller_enable(cqspi, 0);
1421 probe_irq_failed:
1422         clk_disable_unprepare(cqspi->clk);
1423 probe_clk_failed:
1424         pm_runtime_put_sync(dev);
1425         pm_runtime_disable(dev);
1426         return ret;
1427 }
1428
1429 static int cqspi_remove(struct platform_device *pdev)
1430 {
1431         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1432         int i;
1433
1434         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1435                 if (cqspi->f_pdata[i].registered)
1436                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1437
1438         cqspi_controller_enable(cqspi, 0);
1439
1440         if (cqspi->rx_chan)
1441                 dma_release_channel(cqspi->rx_chan);
1442
1443         clk_disable_unprepare(cqspi->clk);
1444
1445         pm_runtime_put_sync(&pdev->dev);
1446         pm_runtime_disable(&pdev->dev);
1447
1448         return 0;
1449 }
1450
1451 #ifdef CONFIG_PM_SLEEP
1452 static int cqspi_suspend(struct device *dev)
1453 {
1454         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1455
1456         cqspi_controller_enable(cqspi, 0);
1457         return 0;
1458 }
1459
1460 static int cqspi_resume(struct device *dev)
1461 {
1462         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1463
1464         cqspi_controller_enable(cqspi, 1);
1465         return 0;
1466 }
1467
1468 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1469         .suspend = cqspi_suspend,
1470         .resume = cqspi_resume,
1471 };
1472
1473 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1474 #else
1475 #define CQSPI_DEV_PM_OPS        NULL
1476 #endif
1477
1478 static const struct cqspi_driver_platdata cdns_qspi = {
1479         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
1480 };
1481
1482 static const struct cqspi_driver_platdata k2g_qspi = {
1483         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
1484         .quirks = CQSPI_NEEDS_WR_DELAY,
1485 };
1486
1487 static const struct cqspi_driver_platdata am654_ospi = {
1488         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
1489         .quirks = CQSPI_NEEDS_WR_DELAY,
1490 };
1491
1492 static const struct of_device_id cqspi_dt_ids[] = {
1493         {
1494                 .compatible = "cdns,qspi-nor",
1495                 .data = &cdns_qspi,
1496         },
1497         {
1498                 .compatible = "ti,k2g-qspi",
1499                 .data = &k2g_qspi,
1500         },
1501         {
1502                 .compatible = "ti,am654-ospi",
1503                 .data = &am654_ospi,
1504         },
1505         { /* end of table */ }
1506 };
1507
1508 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1509
1510 static struct platform_driver cqspi_platform_driver = {
1511         .probe = cqspi_probe,
1512         .remove = cqspi_remove,
1513         .driver = {
1514                 .name = CQSPI_NAME,
1515                 .pm = CQSPI_DEV_PM_OPS,
1516                 .of_match_table = cqspi_dt_ids,
1517         },
1518 };
1519
1520 module_platform_driver(cqspi_platform_driver);
1521
1522 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1523 MODULE_LICENSE("GPL v2");
1524 MODULE_ALIAS("platform:" CQSPI_NAME);
1525 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1526 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");