drivers/mtd/spi-nor/cadence-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Cadence QSPI Controller
   4  *
   5  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   6  */
   7 #include <linux/clk.h>
   8 #include <linux/completion.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/jiffies.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/spi-nor.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/reset.h>
  27 #include <linux/sched.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/timer.h>
  30
  31 #define CQSPI_NAME                      "cadence-qspi"
  32 #define CQSPI_MAX_CHIPSELECT            16
  33
  34 /* Quirks */
  35 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  36
  37 /* Capabilities mask */
  38 #define CQSPI_BASE_HWCAPS_MASK                                  \
  39         (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |             \
  40         SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 |       \
  41         SNOR_HWCAPS_PP)
  42
  43 struct cqspi_st;
  44
  45 struct cqspi_flash_pdata {
  46         struct spi_nor  nor;
  47         struct cqspi_st *cqspi;
  48         u32             clk_rate;
  49         u32             read_delay;
  50         u32             tshsl_ns;
  51         u32             tsd2d_ns;
  52         u32             tchsh_ns;
  53         u32             tslch_ns;
  54         u8              inst_width;
  55         u8              addr_width;
  56         u8              data_width;
  57         u8              cs;
  58         bool            registered;
  59         bool            use_direct_mode;
  60 };
  61
  62 struct cqspi_st {
  63         struct platform_device  *pdev;
  64
  65         struct clk              *clk;
  66         unsigned int            sclk;
  67
  68         void __iomem            *iobase;
  69         void __iomem            *ahb_base;
  70         resource_size_t         ahb_size;
  71         struct completion       transfer_complete;
  72         struct mutex            bus_mutex;
  73
  74         struct dma_chan         *rx_chan;
  75         struct completion       rx_dma_complete;
  76         dma_addr_t              mmap_phys_base;
  77
  78         int                     current_cs;
  79         int                     current_page_size;
  80         int                     current_erase_size;
  81         int                     current_addr_width;
  82         unsigned long           master_ref_clk_hz;
  83         bool                    is_decoded_cs;
  84         u32                     fifo_depth;
  85         u32                     fifo_width;
  86         bool                    rclk_en;
  87         u32                     trigger_address;
  88         u32                     wr_delay;
  89         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  90 };
  91
  92 struct cqspi_driver_platdata {
  93         u32 hwcaps_mask;
  94         u8 quirks;
  95 };
  96
  97 /* Operation timeout value */
  98 #define CQSPI_TIMEOUT_MS                        500
  99 #define CQSPI_READ_TIMEOUT_MS                   10
 100
 101 /* Instruction type */
 102 #define CQSPI_INST_TYPE_SINGLE                  0
 103 #define CQSPI_INST_TYPE_DUAL                    1
 104 #define CQSPI_INST_TYPE_QUAD                    2
 105 #define CQSPI_INST_TYPE_OCTAL                   3
 106
 107 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 108 #define CQSPI_DUMMY_BYTES_MAX                   4
 109 #define CQSPI_DUMMY_CLKS_MAX                    31
 110
 111 #define CQSPI_STIG_DATA_LEN_MAX                 8
 112
 113 /* Register map */
 114 #define CQSPI_REG_CONFIG                        0x00
 115 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 116 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 117 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 118 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 119 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 120 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 121 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 122 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 123 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 124
 125 #define CQSPI_REG_RD_INSTR                      0x04
 126 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 127 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 128 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 129 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 130 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 131 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 132 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 133 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 134 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 135 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 136
 137 #define CQSPI_REG_WR_INSTR                      0x08
 138 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 139 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 140 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 141
 142 #define CQSPI_REG_DELAY                         0x0C
 143 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 144 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 145 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 146 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 147 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 148 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 149 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 150 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 151
 152 #define CQSPI_REG_READCAPTURE                   0x10
 153 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 154 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 155 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 156
 157 #define CQSPI_REG_SIZE                          0x14
 158 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 159 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 160 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 161 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 162 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 163 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 164
 165 #define CQSPI_REG_SRAMPARTITION                 0x18
 166 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 167
 168 #define CQSPI_REG_DMA                           0x20
 169 #define CQSPI_REG_DMA_SINGLE_LSB                0
 170 #define CQSPI_REG_DMA_BURST_LSB                 8
 171 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 172 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 173
 174 #define CQSPI_REG_REMAP                         0x24
 175 #define CQSPI_REG_MODE_BIT                      0x28
 176
 177 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 178 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 179 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 180 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 181 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 182
 183 #define CQSPI_REG_IRQSTATUS                     0x40
 184 #define CQSPI_REG_IRQMASK                       0x44
 185
 186 #define CQSPI_REG_INDIRECTRD                    0x60
 187 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 188 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 189 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 190
 191 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 192 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 193 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 194
 195 #define CQSPI_REG_CMDCTRL                       0x90
 196 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 197 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 198 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 199 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 200 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 201 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 202 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 203 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 204 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 205 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 206 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 207 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 208
 209 #define CQSPI_REG_INDIRECTWR                    0x70
 210 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 211 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 212 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 213
 214 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 215 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 216 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 217
 218 #define CQSPI_REG_CMDADDRESS                    0x94
 219 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 220 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 221 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 222 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 223
 224 /* Interrupt status bits */
 225 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 226 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 227 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 228 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 229 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 230 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 231 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 232 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 233
 234 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 235                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 236                                          CQSPI_REG_IRQ_IND_COMP)
 237
 238 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 239                                          CQSPI_REG_IRQ_WATERMARK        | \
 240                                          CQSPI_REG_IRQ_UNDERFLOW)
 241
 242 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 243
 244 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 245 {
 246         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 247         u32 val;
 248
 249         while (1) {
 250                 val = readl(reg);
 251                 if (clear)
 252                         val = ~val;
 253                 val &= mask;
 254
 255                 if (val == mask)
 256                         return 0;
 257
 258                 if (time_after(jiffies, end))
 259                         return -ETIMEDOUT;
 260         }
 261 }
 262
 263 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 264 {
 265         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 266
 267         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 268 }
 269
 270 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 271 {
 272         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 273
 274         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 275         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 276 }
 277
 278 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 279 {
 280         struct cqspi_st *cqspi = dev;
 281         unsigned int irq_status;
 282
 283         /* Read interrupt status */
 284         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 285
 286         /* Clear interrupt */
 287         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 288
 289         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 290
 291         if (irq_status)
 292                 complete(&cqspi->transfer_complete);
 293
 294         return IRQ_HANDLED;
 295 }
 296
 297 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 298 {
 299         struct cqspi_flash_pdata *f_pdata = nor->priv;
 300         u32 rdreg = 0;
 301
 302         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 303         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 304         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 305
 306         return rdreg;
 307 }
 308
 309 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 310 {
 311         const unsigned int poll_idle_retry = 3;
 312         unsigned int count = 0;
 313         unsigned long timeout;
 314
 315         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 316         while (1) {
 317                 /*
 318                  * Read few times in succession to ensure the controller
 319                  * is indeed idle, that is, the bit does not transition
 320                  * low again.
 321                  */
 322                 if (cqspi_is_idle(cqspi))
 323                         count++;
 324                 else
 325                         count = 0;
 326
 327                 if (count >= poll_idle_retry)
 328                         return 0;
 329
 330                 if (time_after(jiffies, timeout)) {
 331                         /* Timeout, in busy mode. */
 332                         dev_err(&cqspi->pdev->dev,
 333                                 "QSPI is still busy after %dms timeout.\n",
 334                                 CQSPI_TIMEOUT_MS);
 335                         return -ETIMEDOUT;
 336                 }
 337
 338                 cpu_relax();
 339         }
 340 }
 341
 342 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 343 {
 344         void __iomem *reg_base = cqspi->iobase;
 345         int ret;
 346
 347         /* Write the CMDCTRL without start execution. */
 348         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 349         /* Start execute */
 350         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 351         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 352
 353         /* Polling for completion. */
 354         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 355                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 356         if (ret) {
 357                 dev_err(&cqspi->pdev->dev,
 358                         "Flash command execution timed out.\n");
 359                 return ret;
 360         }
 361
 362         /* Polling QSPI idle status. */
 363         return cqspi_wait_idle(cqspi);
 364 }
 365
 366 static int cqspi_command_read(struct spi_nor *nor,
 367                               const u8 *txbuf, const unsigned n_tx,
 368                               u8 *rxbuf, const unsigned n_rx)
 369 {
 370         struct cqspi_flash_pdata *f_pdata = nor->priv;
 371         struct cqspi_st *cqspi = f_pdata->cqspi;
 372         void __iomem *reg_base = cqspi->iobase;
 373         unsigned int rdreg;
 374         unsigned int reg;
 375         unsigned int read_len;
 376         int status;
 377
 378         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 379                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 380                         n_rx, rxbuf);
 381                 return -EINVAL;
 382         }
 383
 384         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 385
 386         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 387         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 388
 389         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 390
 391         /* 0 means 1 byte. */
 392         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 393                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 394         status = cqspi_exec_flash_cmd(cqspi, reg);
 395         if (status)
 396                 return status;
 397
 398         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 399
 400         /* Put the read value into rx_buf */
 401         read_len = (n_rx > 4) ? 4 : n_rx;
 402         memcpy(rxbuf, &reg, read_len);
 403         rxbuf += read_len;
 404
 405         if (n_rx > 4) {
 406                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 407
 408                 read_len = n_rx - read_len;
 409                 memcpy(rxbuf, &reg, read_len);
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 416                                const u8 *txbuf, const unsigned n_tx)
 417 {
 418         struct cqspi_flash_pdata *f_pdata = nor->priv;
 419         struct cqspi_st *cqspi = f_pdata->cqspi;
 420         void __iomem *reg_base = cqspi->iobase;
 421         unsigned int reg;
 422         unsigned int data;
 423         u32 write_len;
 424         int ret;
 425
 426         if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 427                 dev_err(nor->dev,
 428                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 429                         n_tx, txbuf);
 430                 return -EINVAL;
 431         }
 432
 433         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 434         if (n_tx) {
 435                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 436                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 437                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 438                 data = 0;
 439                 write_len = (n_tx > 4) ? 4 : n_tx;
 440                 memcpy(&data, txbuf, write_len);
 441                 txbuf += write_len;
 442                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 443
 444                 if (n_tx > 4) {
 445                         data = 0;
 446                         write_len = n_tx - 4;
 447                         memcpy(&data, txbuf, write_len);
 448                         writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 449                 }
 450         }
 451         ret = cqspi_exec_flash_cmd(cqspi, reg);
 452         return ret;
 453 }
 454
 455 static int cqspi_command_write_addr(struct spi_nor *nor,
 456                                     const u8 opcode, const unsigned int addr)
 457 {
 458         struct cqspi_flash_pdata *f_pdata = nor->priv;
 459         struct cqspi_st *cqspi = f_pdata->cqspi;
 460         void __iomem *reg_base = cqspi->iobase;
 461         unsigned int reg;
 462
 463         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 464         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 465         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 466                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 467
 468         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 469
 470         return cqspi_exec_flash_cmd(cqspi, reg);
 471 }
 472
 473 static int cqspi_read_setup(struct spi_nor *nor)
 474 {
 475         struct cqspi_flash_pdata *f_pdata = nor->priv;
 476         struct cqspi_st *cqspi = f_pdata->cqspi;
 477         void __iomem *reg_base = cqspi->iobase;
 478         unsigned int dummy_clk = 0;
 479         unsigned int reg;
 480
 481         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 482         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 483
 484         /* Setup dummy clock cycles */
 485         dummy_clk = nor->read_dummy;
 486         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 487                 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
 488
 489         if (dummy_clk / 8) {
 490                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 491                 /* Set mode bits high to ensure chip doesn't enter XIP */
 492                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 493
 494                 /* Need to subtract the mode byte (8 clocks). */
 495                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 496                         dummy_clk -= 8;
 497
 498                 if (dummy_clk)
 499                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 500                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 501         }
 502
 503         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 504
 505         /* Set address width */
 506         reg = readl(reg_base + CQSPI_REG_SIZE);
 507         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 508         reg |= (nor->addr_width - 1);
 509         writel(reg, reg_base + CQSPI_REG_SIZE);
 510         return 0;
 511 }
 512
 513 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
 514                                        loff_t from_addr, const size_t n_rx)
 515 {
 516         struct cqspi_flash_pdata *f_pdata = nor->priv;
 517         struct cqspi_st *cqspi = f_pdata->cqspi;
 518         void __iomem *reg_base = cqspi->iobase;
 519         void __iomem *ahb_base = cqspi->ahb_base;
 520         unsigned int remaining = n_rx;
 521         unsigned int mod_bytes = n_rx % 4;
 522         unsigned int bytes_to_read = 0;
 523         u8 *rxbuf_end = rxbuf + n_rx;
 524         int ret = 0;
 525
 526         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 527         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 528
 529         /* Clear all interrupts. */
 530         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 531
 532         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 533
 534         reinit_completion(&cqspi->transfer_complete);
 535         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 536                reg_base + CQSPI_REG_INDIRECTRD);
 537
 538         while (remaining > 0) {
 539                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 540                                 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 541                         ret = -ETIMEDOUT;
 542
 543                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 544
 545                 if (ret && bytes_to_read == 0) {
 546                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 547                         goto failrd;
 548                 }
 549
 550                 while (bytes_to_read != 0) {
 551                         unsigned int word_remain = round_down(remaining, 4);
 552
 553                         bytes_to_read *= cqspi->fifo_width;
 554                         bytes_to_read = bytes_to_read > remaining ?
 555                                         remaining : bytes_to_read;
 556                         bytes_to_read = round_down(bytes_to_read, 4);
 557                         /* Read 4 byte word chunks then single bytes */
 558                         if (bytes_to_read) {
 559                                 ioread32_rep(ahb_base, rxbuf,
 560                                              (bytes_to_read / 4));
 561                         } else if (!word_remain && mod_bytes) {
 562                                 unsigned int temp = ioread32(ahb_base);
 563
 564                                 bytes_to_read = mod_bytes;
 565                                 memcpy(rxbuf, &temp, min((unsigned int)
 566                                                          (rxbuf_end - rxbuf),
 567                                                          bytes_to_read));
 568                         }
 569                         rxbuf += bytes_to_read;
 570                         remaining -= bytes_to_read;
 571                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 572                 }
 573
 574                 if (remaining > 0)
 575                         reinit_completion(&cqspi->transfer_complete);
 576         }
 577
 578         /* Check indirect done status */
 579         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 580                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 581         if (ret) {
 582                 dev_err(nor->dev,
 583                         "Indirect read completion error (%i)\n", ret);
 584                 goto failrd;
 585         }
 586
 587         /* Disable interrupt */
 588         writel(0, reg_base + CQSPI_REG_IRQMASK);
 589
 590         /* Clear indirect completion status */
 591         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 592
 593         return 0;
 594
 595 failrd:
 596         /* Disable interrupt */
 597         writel(0, reg_base + CQSPI_REG_IRQMASK);
 598
 599         /* Cancel the indirect read */
 600         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 601                reg_base + CQSPI_REG_INDIRECTRD);
 602         return ret;
 603 }
 604
 605 static int cqspi_write_setup(struct spi_nor *nor)
 606 {
 607         unsigned int reg;
 608         struct cqspi_flash_pdata *f_pdata = nor->priv;
 609         struct cqspi_st *cqspi = f_pdata->cqspi;
 610         void __iomem *reg_base = cqspi->iobase;
 611
 612         /* Set opcode. */
 613         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 614         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 615         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 616         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 617
 618         reg = readl(reg_base + CQSPI_REG_SIZE);
 619         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 620         reg |= (nor->addr_width - 1);
 621         writel(reg, reg_base + CQSPI_REG_SIZE);
 622         return 0;
 623 }
 624
 625 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
 626                                         const u8 *txbuf, const size_t n_tx)
 627 {
 628         const unsigned int page_size = nor->page_size;
 629         struct cqspi_flash_pdata *f_pdata = nor->priv;
 630         struct cqspi_st *cqspi = f_pdata->cqspi;
 631         void __iomem *reg_base = cqspi->iobase;
 632         unsigned int remaining = n_tx;
 633         unsigned int write_bytes;
 634         int ret;
 635
 636         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 637         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 638
 639         /* Clear all interrupts. */
 640         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 641
 642         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 643
 644         reinit_completion(&cqspi->transfer_complete);
 645         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 646                reg_base + CQSPI_REG_INDIRECTWR);
 647         /*
 648          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 649          * Controller programming sequence, couple of cycles of
 650          * QSPI_REF_CLK delay is required for the above bit to
 651          * be internally synchronized by the QSPI module. Provide 5
 652          * cycles of delay.
 653          */
 654         if (cqspi->wr_delay)
 655                 ndelay(cqspi->wr_delay);
 656
 657         while (remaining > 0) {
 658                 size_t write_words, mod_bytes;
 659
 660                 write_bytes = remaining > page_size ? page_size : remaining;
 661                 write_words = write_bytes / 4;
 662                 mod_bytes = write_bytes % 4;
 663                 /* Write 4 bytes at a time then single bytes. */
 664                 if (write_words) {
 665                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
 666                         txbuf += (write_words * 4);
 667                 }
 668                 if (mod_bytes) {
 669                         unsigned int temp = 0xFFFFFFFF;
 670
 671                         memcpy(&temp, txbuf, mod_bytes);
 672                         iowrite32(temp, cqspi->ahb_base);
 673                         txbuf += mod_bytes;
 674                 }
 675
 676                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 677                                         msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
 678                         dev_err(nor->dev, "Indirect write timeout\n");
 679                         ret = -ETIMEDOUT;
 680                         goto failwr;
 681                 }
 682
 683                 remaining -= write_bytes;
 684
 685                 if (remaining > 0)
 686                         reinit_completion(&cqspi->transfer_complete);
 687         }
 688
 689         /* Check indirect done status */
 690         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 691                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 692         if (ret) {
 693                 dev_err(nor->dev,
 694                         "Indirect write completion error (%i)\n", ret);
 695                 goto failwr;
 696         }
 697
 698         /* Disable interrupt. */
 699         writel(0, reg_base + CQSPI_REG_IRQMASK);
 700
 701         /* Clear indirect completion status */
 702         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 703
 704         cqspi_wait_idle(cqspi);
 705
 706         return 0;
 707
 708 failwr:
 709         /* Disable interrupt. */
 710         writel(0, reg_base + CQSPI_REG_IRQMASK);
 711
 712         /* Cancel the indirect write */
 713         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 714                reg_base + CQSPI_REG_INDIRECTWR);
 715         return ret;
 716 }
 717
 718 static void cqspi_chipselect(struct spi_nor *nor)
 719 {
 720         struct cqspi_flash_pdata *f_pdata = nor->priv;
 721         struct cqspi_st *cqspi = f_pdata->cqspi;
 722         void __iomem *reg_base = cqspi->iobase;
 723         unsigned int chip_select = f_pdata->cs;
 724         unsigned int reg;
 725
 726         reg = readl(reg_base + CQSPI_REG_CONFIG);
 727         if (cqspi->is_decoded_cs) {
 728                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 729         } else {
 730                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 731
 732                 /* Convert CS if without decoder.
 733                  * CS0 to 4b'1110
 734                  * CS1 to 4b'1101
 735                  * CS2 to 4b'1011
 736                  * CS3 to 4b'0111
 737                  */
 738                 chip_select = 0xF & ~(1 << chip_select);
 739         }
 740
 741         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 742                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 743         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 744             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 745         writel(reg, reg_base + CQSPI_REG_CONFIG);
 746 }
 747
 748 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
 749 {
 750         struct cqspi_flash_pdata *f_pdata = nor->priv;
 751         struct cqspi_st *cqspi = f_pdata->cqspi;
 752         void __iomem *iobase = cqspi->iobase;
 753         unsigned int reg;
 754
 755         /* configure page size and block size. */
 756         reg = readl(iobase + CQSPI_REG_SIZE);
 757         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 758         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 759         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 760         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 761         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
 762         reg |= (nor->addr_width - 1);
 763         writel(reg, iobase + CQSPI_REG_SIZE);
 764
 765         /* configure the chip select */
 766         cqspi_chipselect(nor);
 767
 768         /* Store the new configuration of the controller */
 769         cqspi->current_page_size = nor->page_size;
 770         cqspi->current_erase_size = nor->mtd.erasesize;
 771         cqspi->current_addr_width = nor->addr_width;
 772 }
 773
 774 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 775                                            const unsigned int ns_val)
 776 {
 777         unsigned int ticks;
 778
 779         ticks = ref_clk_hz / 1000;      /* kHz */
 780         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 781
 782         return ticks;
 783 }
 784
 785 static void cqspi_delay(struct spi_nor *nor)
 786 {
 787         struct cqspi_flash_pdata *f_pdata = nor->priv;
 788         struct cqspi_st *cqspi = f_pdata->cqspi;
 789         void __iomem *iobase = cqspi->iobase;
 790         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 791         unsigned int tshsl, tchsh, tslch, tsd2d;
 792         unsigned int reg;
 793         unsigned int tsclk;
 794
 795         /* calculate the number of ref ticks for one sclk tick */
 796         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 797
 798         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 799         /* this particular value must be at least one sclk */
 800         if (tshsl < tsclk)
 801                 tshsl = tsclk;
 802
 803         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 804         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 805         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 806
 807         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 808                << CQSPI_REG_DELAY_TSHSL_LSB;
 809         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 810                 << CQSPI_REG_DELAY_TCHSH_LSB;
 811         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 812                 << CQSPI_REG_DELAY_TSLCH_LSB;
 813         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 814                 << CQSPI_REG_DELAY_TSD2D_LSB;
 815         writel(reg, iobase + CQSPI_REG_DELAY);
 816 }
 817
 818 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 819 {
 820         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 821         void __iomem *reg_base = cqspi->iobase;
 822         u32 reg, div;
 823
 824         /* Recalculate the baudrate divisor based on QSPI specification. */
 825         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 826
 827         reg = readl(reg_base + CQSPI_REG_CONFIG);
 828         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 829         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 830         writel(reg, reg_base + CQSPI_REG_CONFIG);
 831 }
 832
 833 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 834                                    const bool bypass,
 835                                    const unsigned int delay)
 836 {
 837         void __iomem *reg_base = cqspi->iobase;
 838         unsigned int reg;
 839
 840         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 841
 842         if (bypass)
 843                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 844         else
 845                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 846
 847         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 848                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 849
 850         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 851                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 852
 853         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 854 }
 855
 856 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 857 {
 858         void __iomem *reg_base = cqspi->iobase;
 859         unsigned int reg;
 860
 861         reg = readl(reg_base + CQSPI_REG_CONFIG);
 862
 863         if (enable)
 864                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 865         else
 866                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 867
 868         writel(reg, reg_base + CQSPI_REG_CONFIG);
 869 }
 870
 871 static void cqspi_configure(struct spi_nor *nor)
 872 {
 873         struct cqspi_flash_pdata *f_pdata = nor->priv;
 874         struct cqspi_st *cqspi = f_pdata->cqspi;
 875         const unsigned int sclk = f_pdata->clk_rate;
 876         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 877         int switch_ck = (cqspi->sclk != sclk);
 878
 879         if ((cqspi->current_page_size != nor->page_size) ||
 880             (cqspi->current_erase_size != nor->mtd.erasesize) ||
 881             (cqspi->current_addr_width != nor->addr_width))
 882                 switch_cs = 1;
 883
 884         if (switch_cs || switch_ck)
 885                 cqspi_controller_enable(cqspi, 0);
 886
 887         /* Switch chip select. */
 888         if (switch_cs) {
 889                 cqspi->current_cs = f_pdata->cs;
 890                 cqspi_configure_cs_and_sizes(nor);
 891         }
 892
 893         /* Setup baudrate divisor and delays */
 894         if (switch_ck) {
 895                 cqspi->sclk = sclk;
 896                 cqspi_config_baudrate_div(cqspi);
 897                 cqspi_delay(nor);
 898                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
 899                                        f_pdata->read_delay);
 900         }
 901
 902         if (switch_cs || switch_ck)
 903                 cqspi_controller_enable(cqspi, 1);
 904 }
 905
 906 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 907 {
 908         struct cqspi_flash_pdata *f_pdata = nor->priv;
 909
 910         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 911         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 912         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 913
 914         if (read) {
 915                 switch (nor->read_proto) {
 916                 case SNOR_PROTO_1_1_1:
 917                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 918                         break;
 919                 case SNOR_PROTO_1_1_2:
 920                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 921                         break;
 922                 case SNOR_PROTO_1_1_4:
 923                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 924                         break;
 925                 case SNOR_PROTO_1_1_8:
 926                         f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
 927                         break;
 928                 default:
 929                         return -EINVAL;
 930                 }
 931         }
 932
 933         cqspi_configure(nor);
 934
 935         return 0;
 936 }
 937
 938 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 939                            size_t len, const u_char *buf)
 940 {
 941         struct cqspi_flash_pdata *f_pdata = nor->priv;
 942         struct cqspi_st *cqspi = f_pdata->cqspi;
 943         int ret;
 944
 945         ret = cqspi_set_protocol(nor, 0);
 946         if (ret)
 947                 return ret;
 948
 949         ret = cqspi_write_setup(nor);
 950         if (ret)
 951                 return ret;
 952
 953         if (f_pdata->use_direct_mode) {
 954                 memcpy_toio(cqspi->ahb_base + to, buf, len);
 955                 ret = cqspi_wait_idle(cqspi);
 956         } else {
 957                 ret = cqspi_indirect_write_execute(nor, to, buf, len);
 958         }
 959         if (ret)
 960                 return ret;
 961
 962         return len;
 963 }
 964
 965 static void cqspi_rx_dma_callback(void *param)
 966 {
 967         struct cqspi_st *cqspi = param;
 968
 969         complete(&cqspi->rx_dma_complete);
 970 }
 971
 972 static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
 973                                      loff_t from, size_t len)
 974 {
 975         struct cqspi_flash_pdata *f_pdata = nor->priv;
 976         struct cqspi_st *cqspi = f_pdata->cqspi;
 977         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 978         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
 979         int ret = 0;
 980         struct dma_async_tx_descriptor *tx;
 981         dma_cookie_t cookie;
 982         dma_addr_t dma_dst;
 983
 984         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
 985                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
 986                 return 0;
 987         }
 988
 989         dma_dst = dma_map_single(nor->dev, buf, len, DMA_FROM_DEVICE);
 990         if (dma_mapping_error(nor->dev, dma_dst)) {
 991                 dev_err(nor->dev, "dma mapping failed\n");
 992                 return -ENOMEM;
 993         }
 994         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
 995                                        len, flags);
 996         if (!tx) {
 997                 dev_err(nor->dev, "device_prep_dma_memcpy error\n");
 998                 ret = -EIO;
 999                 goto err_unmap;
1000         }
1001
1002         tx->callback = cqspi_rx_dma_callback;
1003         tx->callback_param = cqspi;
1004         cookie = tx->tx_submit(tx);
1005         reinit_completion(&cqspi->rx_dma_complete);
1006
1007         ret = dma_submit_error(cookie);
1008         if (ret) {
1009                 dev_err(nor->dev, "dma_submit_error %d\n", cookie);
1010                 ret = -EIO;
1011                 goto err_unmap;
1012         }
1013
1014         dma_async_issue_pending(cqspi->rx_chan);
1015         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1016                                          msecs_to_jiffies(len))) {
1017                 dmaengine_terminate_sync(cqspi->rx_chan);
1018                 dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
1019                 ret = -ETIMEDOUT;
1020                 goto err_unmap;
1021         }
1022
1023 err_unmap:
1024         dma_unmap_single(nor->dev, dma_dst, len, DMA_FROM_DEVICE);
1025
1026         return ret;
1027 }
1028
1029 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
1030                           size_t len, u_char *buf)
1031 {
1032         struct cqspi_flash_pdata *f_pdata = nor->priv;
1033         int ret;
1034
1035         ret = cqspi_set_protocol(nor, 1);
1036         if (ret)
1037                 return ret;
1038
1039         ret = cqspi_read_setup(nor);
1040         if (ret)
1041                 return ret;
1042
1043         if (f_pdata->use_direct_mode)
1044                 ret = cqspi_direct_read_execute(nor, buf, from, len);
1045         else
1046                 ret = cqspi_indirect_read_execute(nor, buf, from, len);
1047         if (ret)
1048                 return ret;
1049
1050         return len;
1051 }
1052
1053 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
1054 {
1055         int ret;
1056
1057         ret = cqspi_set_protocol(nor, 0);
1058         if (ret)
1059                 return ret;
1060
1061         /* Send write enable, then erase commands. */
1062         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
1063         if (ret)
1064                 return ret;
1065
1066         /* Set up command buffer. */
1067         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
1068         if (ret)
1069                 return ret;
1070
1071         return 0;
1072 }
1073
1074 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1075 {
1076         struct cqspi_flash_pdata *f_pdata = nor->priv;
1077         struct cqspi_st *cqspi = f_pdata->cqspi;
1078
1079         mutex_lock(&cqspi->bus_mutex);
1080
1081         return 0;
1082 }
1083
1084 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1085 {
1086         struct cqspi_flash_pdata *f_pdata = nor->priv;
1087         struct cqspi_st *cqspi = f_pdata->cqspi;
1088
1089         mutex_unlock(&cqspi->bus_mutex);
1090 }
1091
1092 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1093 {
1094         int ret;
1095
1096         ret = cqspi_set_protocol(nor, 0);
1097         if (!ret)
1098                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1099
1100         return ret;
1101 }
1102
1103 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1104 {
1105         int ret;
1106
1107         ret = cqspi_set_protocol(nor, 0);
1108         if (!ret)
1109                 ret = cqspi_command_write(nor, opcode, buf, len);
1110
1111         return ret;
1112 }
1113
1114 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1115                                     struct cqspi_flash_pdata *f_pdata,
1116                                     struct device_node *np)
1117 {
1118         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1119                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1120                 return -ENXIO;
1121         }
1122
1123         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1124                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1125                 return -ENXIO;
1126         }
1127
1128         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1129                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1130                 return -ENXIO;
1131         }
1132
1133         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1134                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1135                 return -ENXIO;
1136         }
1137
1138         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1139                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1140                 return -ENXIO;
1141         }
1142
1143         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1144                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1145                 return -ENXIO;
1146         }
1147
1148         return 0;
1149 }
1150
1151 static int cqspi_of_get_pdata(struct platform_device *pdev)
1152 {
1153         struct device_node *np = pdev->dev.of_node;
1154         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1155
1156         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1157
1158         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1159                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1160                 return -ENXIO;
1161         }
1162
1163         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1164                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1165                 return -ENXIO;
1166         }
1167
1168         if (of_property_read_u32(np, "cdns,trigger-address",
1169                                  &cqspi->trigger_address)) {
1170                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1171                 return -ENXIO;
1172         }
1173
1174         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1175
1176         return 0;
1177 }
1178
1179 static void cqspi_controller_init(struct cqspi_st *cqspi)
1180 {
1181         u32 reg;
1182
1183         cqspi_controller_enable(cqspi, 0);
1184
1185         /* Configure the remap address register, no remap */
1186         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1187
1188         /* Disable all interrupts. */
1189         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1190
1191         /* Configure the SRAM split to 1:1 . */
1192         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1193
1194         /* Load indirect trigger address. */
1195         writel(cqspi->trigger_address,
1196                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1197
1198         /* Program read watermark -- 1/2 of the FIFO. */
1199         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1200                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1201         /* Program write watermark -- 1/8 of the FIFO. */
1202         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1203                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1204
1205         /* Enable Direct Access Controller */
1206         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1207         reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1208         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1209
1210         cqspi_controller_enable(cqspi, 1);
1211 }
1212
1213 static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1214 {
1215         dma_cap_mask_t mask;
1216
1217         dma_cap_zero(mask);
1218         dma_cap_set(DMA_MEMCPY, mask);
1219
1220         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1221         if (IS_ERR(cqspi->rx_chan)) {
1222                 dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
1223                 cqspi->rx_chan = NULL;
1224         }
1225         init_completion(&cqspi->rx_dma_complete);
1226 }
1227
1228 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1229 {
1230         struct platform_device *pdev = cqspi->pdev;
1231         struct device *dev = &pdev->dev;
1232         const struct cqspi_driver_platdata *ddata;
1233         struct spi_nor_hwcaps hwcaps;
1234         struct cqspi_flash_pdata *f_pdata;
1235         struct spi_nor *nor;
1236         struct mtd_info *mtd;
1237         unsigned int cs;
1238         int i, ret;
1239
1240         ddata = of_device_get_match_data(dev);
1241         if (!ddata) {
1242                 dev_err(dev, "Couldn't find driver data\n");
1243                 return -EINVAL;
1244         }
1245         hwcaps.mask = ddata->hwcaps_mask;
1246
1247         /* Get flash device data */
1248         for_each_available_child_of_node(dev->of_node, np) {
1249                 ret = of_property_read_u32(np, "reg", &cs);
1250                 if (ret) {
1251                         dev_err(dev, "Couldn't determine chip select.\n");
1252                         goto err;
1253                 }
1254
1255                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1256                         ret = -EINVAL;
1257                         dev_err(dev, "Chip select %d out of range.\n", cs);
1258                         goto err;
1259                 }
1260
1261                 f_pdata = &cqspi->f_pdata[cs];
1262                 f_pdata->cqspi = cqspi;
1263                 f_pdata->cs = cs;
1264
1265                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1266                 if (ret)
1267                         goto err;
1268
1269                 nor = &f_pdata->nor;
1270                 mtd = &nor->mtd;
1271
1272                 mtd->priv = nor;
1273
1274                 nor->dev = dev;
1275                 spi_nor_set_flash_node(nor, np);
1276                 nor->priv = f_pdata;
1277
1278                 nor->read_reg = cqspi_read_reg;
1279                 nor->write_reg = cqspi_write_reg;
1280                 nor->read = cqspi_read;
1281                 nor->write = cqspi_write;
1282                 nor->erase = cqspi_erase;
1283                 nor->prepare = cqspi_prep;
1284                 nor->unprepare = cqspi_unprep;
1285
1286                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1287                                            dev_name(dev), cs);
1288                 if (!mtd->name) {
1289                         ret = -ENOMEM;
1290                         goto err;
1291                 }
1292
1293                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1294                 if (ret)
1295                         goto err;
1296
1297                 ret = mtd_device_register(mtd, NULL, 0);
1298                 if (ret)
1299                         goto err;
1300
1301                 f_pdata->registered = true;
1302
1303                 if (mtd->size <= cqspi->ahb_size) {
1304                         f_pdata->use_direct_mode = true;
1305                         dev_dbg(nor->dev, "using direct mode for %s\n",
1306                                 mtd->name);
1307
1308                         if (!cqspi->rx_chan)
1309                                 cqspi_request_mmap_dma(cqspi);
1310                 }
1311         }
1312
1313         return 0;
1314
1315 err:
1316         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1317                 if (cqspi->f_pdata[i].registered)
1318                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1319         return ret;
1320 }
1321
1322 static int cqspi_probe(struct platform_device *pdev)
1323 {
1324         struct device_node *np = pdev->dev.of_node;
1325         struct device *dev = &pdev->dev;
1326         struct cqspi_st *cqspi;
1327         struct resource *res;
1328         struct resource *res_ahb;
1329         struct reset_control *rstc, *rstc_ocp;
1330         const struct cqspi_driver_platdata *ddata;
1331         int ret;
1332         int irq;
1333
1334         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1335         if (!cqspi)
1336                 return -ENOMEM;
1337
1338         mutex_init(&cqspi->bus_mutex);
1339         cqspi->pdev = pdev;
1340         platform_set_drvdata(pdev, cqspi);
1341
1342         /* Obtain configuration from OF. */
1343         ret = cqspi_of_get_pdata(pdev);
1344         if (ret) {
1345                 dev_err(dev, "Cannot get mandatory OF data.\n");
1346                 return -ENODEV;
1347         }
1348
1349         /* Obtain QSPI clock. */
1350         cqspi->clk = devm_clk_get(dev, NULL);
1351         if (IS_ERR(cqspi->clk)) {
1352                 dev_err(dev, "Cannot claim QSPI clock.\n");
1353                 return PTR_ERR(cqspi->clk);
1354         }
1355
1356         /* Obtain and remap controller address. */
1357         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358         cqspi->iobase = devm_ioremap_resource(dev, res);
1359         if (IS_ERR(cqspi->iobase)) {
1360                 dev_err(dev, "Cannot remap controller address.\n");
1361                 return PTR_ERR(cqspi->iobase);
1362         }
1363
1364         /* Obtain and remap AHB address. */
1365         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1366         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1367         if (IS_ERR(cqspi->ahb_base)) {
1368                 dev_err(dev, "Cannot remap AHB address.\n");
1369                 return PTR_ERR(cqspi->ahb_base);
1370         }
1371         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1372         cqspi->ahb_size = resource_size(res_ahb);
1373
1374         init_completion(&cqspi->transfer_complete);
1375
1376         /* Obtain IRQ line. */
1377         irq = platform_get_irq(pdev, 0);
1378         if (irq < 0) {
1379                 dev_err(dev, "Cannot obtain IRQ.\n");
1380                 return -ENXIO;
1381         }
1382
1383         pm_runtime_enable(dev);
1384         ret = pm_runtime_get_sync(dev);
1385         if (ret < 0) {
1386                 pm_runtime_put_noidle(dev);
1387                 return ret;
1388         }
1389
1390         ret = clk_prepare_enable(cqspi->clk);
1391         if (ret) {
1392                 dev_err(dev, "Cannot enable QSPI clock.\n");
1393                 goto probe_clk_failed;
1394         }
1395
1396         /* Obtain QSPI reset control */
1397         rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1398         if (IS_ERR(rstc)) {
1399                 dev_err(dev, "Cannot get QSPI reset.\n");
1400                 return PTR_ERR(rstc);
1401         }
1402
1403         rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1404         if (IS_ERR(rstc_ocp)) {
1405                 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1406                 return PTR_ERR(rstc_ocp);
1407         }
1408
1409         reset_control_assert(rstc);
1410         reset_control_deassert(rstc);
1411
1412         reset_control_assert(rstc_ocp);
1413         reset_control_deassert(rstc_ocp);
1414
1415         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1416         ddata  = of_device_get_match_data(dev);
1417         if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
1418                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1419                                                    cqspi->master_ref_clk_hz);
1420
1421         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1422                                pdev->name, cqspi);
1423         if (ret) {
1424                 dev_err(dev, "Cannot request IRQ.\n");
1425                 goto probe_irq_failed;
1426         }
1427
1428         cqspi_wait_idle(cqspi);
1429         cqspi_controller_init(cqspi);
1430         cqspi->current_cs = -1;
1431         cqspi->sclk = 0;
1432
1433         ret = cqspi_setup_flash(cqspi, np);
1434         if (ret) {
1435                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1436                 goto probe_setup_failed;
1437         }
1438
1439         return ret;
1440 probe_setup_failed:
1441         cqspi_controller_enable(cqspi, 0);
1442 probe_irq_failed:
1443         clk_disable_unprepare(cqspi->clk);
1444 probe_clk_failed:
1445         pm_runtime_put_sync(dev);
1446         pm_runtime_disable(dev);
1447         return ret;
1448 }
1449
1450 static int cqspi_remove(struct platform_device *pdev)
1451 {
1452         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1453         int i;
1454
1455         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1456                 if (cqspi->f_pdata[i].registered)
1457                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1458
1459         cqspi_controller_enable(cqspi, 0);
1460
1461         if (cqspi->rx_chan)
1462                 dma_release_channel(cqspi->rx_chan);
1463
1464         clk_disable_unprepare(cqspi->clk);
1465
1466         pm_runtime_put_sync(&pdev->dev);
1467         pm_runtime_disable(&pdev->dev);
1468
1469         return 0;
1470 }
1471
1472 #ifdef CONFIG_PM_SLEEP
1473 static int cqspi_suspend(struct device *dev)
1474 {
1475         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1476
1477         cqspi_controller_enable(cqspi, 0);
1478         return 0;
1479 }
1480
1481 static int cqspi_resume(struct device *dev)
1482 {
1483         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1484
1485         cqspi_controller_enable(cqspi, 1);
1486         return 0;
1487 }
1488
1489 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1490         .suspend = cqspi_suspend,
1491         .resume = cqspi_resume,
1492 };
1493
1494 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1495 #else
1496 #define CQSPI_DEV_PM_OPS        NULL
1497 #endif
1498
1499 static const struct cqspi_driver_platdata cdns_qspi = {
1500         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
1501 };
1502
1503 static const struct cqspi_driver_platdata k2g_qspi = {
1504         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
1505         .quirks = CQSPI_NEEDS_WR_DELAY,
1506 };
1507
1508 static const struct cqspi_driver_platdata am654_ospi = {
1509         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
1510         .quirks = CQSPI_NEEDS_WR_DELAY,
1511 };
1512
1513 static const struct of_device_id cqspi_dt_ids[] = {
1514         {
1515                 .compatible = "cdns,qspi-nor",
1516                 .data = &cdns_qspi,
1517         },
1518         {
1519                 .compatible = "ti,k2g-qspi",
1520                 .data = &k2g_qspi,
1521         },
1522         {
1523                 .compatible = "ti,am654-ospi",
1524                 .data = &am654_ospi,
1525         },
1526         { /* end of table */ }
1527 };
1528
1529 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1530
1531 static struct platform_driver cqspi_platform_driver = {
1532         .probe = cqspi_probe,
1533         .remove = cqspi_remove,
1534         .driver = {
1535                 .name = CQSPI_NAME,
1536                 .pm = CQSPI_DEV_PM_OPS,
1537                 .of_match_table = cqspi_dt_ids,
1538         },
1539 };
1540
1541 module_platform_driver(cqspi_platform_driver);
1542
1543 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1544 MODULE_LICENSE("GPL v2");
1545 MODULE_ALIAS("platform:" CQSPI_NAME);
1546 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1547 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");