drivers/mtd/spi/spi_flash_ops.c

   1 /*
   2  * SPI flash operations
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
   6  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <common.h>
  12 #include <spi.h>
  13 #include <spi_flash.h>
  14 #include <watchdog.h>
  15
  16 #include "spi_flash_internal.h"
  17
  18 static void spi_flash_addr(u32 addr, u8 *cmd)
  19 {
  20         /* cmd[0] is actual command */
  21         cmd[1] = addr >> 16;
  22         cmd[2] = addr >> 8;
  23         cmd[3] = addr >> 0;
  24 }
  25
  26 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
  27 {
  28         u8 cmd;
  29         int ret;
  30
  31         cmd = CMD_WRITE_STATUS;
  32         ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
  33         if (ret < 0) {
  34                 debug("SF: fail to write status register\n");
  35                 return ret;
  36         }
  37
  38         return 0;
  39 }
  40
  41 #ifdef CONFIG_SPI_FLASH_BAR
  42 static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
  43 {
  44         u8 cmd;
  45         int ret;
  46
  47         if (flash->bank_curr == bank_sel) {
  48                 debug("SF: not require to enable bank%d\n", bank_sel);
  49                 return 0;
  50         }
  51
  52         cmd = flash->bank_write_cmd;
  53         ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
  54         if (ret < 0) {
  55                 debug("SF: fail to write bank register\n");
  56                 return ret;
  57         }
  58         flash->bank_curr = bank_sel;
  59
  60         return 0;
  61 }
  62 #endif
  63
  64 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  65 {
  66         struct spi_slave *spi = flash->spi;
  67         unsigned long timebase;
  68         int ret;
  69         u8 status;
  70         u8 check_status = 0x0;
  71         u8 poll_bit = STATUS_WIP;
  72         u8 cmd = flash->poll_cmd;
  73
  74         if (cmd == CMD_FLAG_STATUS) {
  75                 poll_bit = STATUS_PEC;
  76                 check_status = poll_bit;
  77         }
  78
  79         ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
  80         if (ret) {
  81                 debug("SF: fail to read %s status register\n",
  82                       cmd == CMD_READ_STATUS ? "read" : "flag");
  83                 return ret;
  84         }
  85
  86         timebase = get_timer(0);
  87         do {
  88                 WATCHDOG_RESET();
  89
  90                 ret = spi_xfer(spi, 8, NULL, &status, 0);
  91                 if (ret)
  92                         return -1;
  93
  94                 if ((status & poll_bit) == check_status)
  95                         break;
  96
  97         } while (get_timer(timebase) < timeout);
  98
  99         spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
 100
 101         if ((status & poll_bit) == check_status)
 102                 return 0;
 103
 104         /* Timed out */
 105         debug("SF: time out!\n");
 106         return -1;
 107 }
 108
 109 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 110                 size_t cmd_len, const void *buf, size_t buf_len)
 111 {
 112         struct spi_slave *spi = flash->spi;
 113         unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
 114         int ret;
 115
 116         if (buf == NULL)
 117                 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
 118
 119         ret = spi_claim_bus(flash->spi);
 120         if (ret) {
 121                 debug("SF: unable to claim SPI bus\n");
 122                 return ret;
 123         }
 124
 125         ret = spi_flash_cmd_write_enable(flash);
 126         if (ret < 0) {
 127                 debug("SF: enabling write failed\n");
 128                 return ret;
 129         }
 130
 131         ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
 132         if (ret < 0) {
 133                 debug("SF: write cmd failed\n");
 134                 return ret;
 135         }
 136
 137         ret = spi_flash_cmd_wait_ready(flash, timeout);
 138         if (ret < 0) {
 139                 debug("SF: write %s timed out\n",
 140                       timeout == SPI_FLASH_PROG_TIMEOUT ?
 141                         "program" : "page erase");
 142                 return ret;
 143         }
 144
 145         spi_release_bus(spi);
 146
 147         return ret;
 148 }
 149
 150 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 151 {
 152         u32 erase_size;
 153         u8 cmd[4];
 154         int ret = -1;
 155
 156         erase_size = flash->erase_size;
 157         if (offset % erase_size || len % erase_size) {
 158                 debug("SF: Erase offset/length not multiple of erase size\n");
 159                 return -1;
 160         }
 161
 162         cmd[0] = flash->erase_cmd;
 163         while (len) {
 164 #ifdef CONFIG_SPI_FLASH_BAR
 165                 u8 bank_sel;
 166
 167                 bank_sel = offset / SPI_FLASH_16MB_BOUN;
 168
 169                 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 170                 if (ret) {
 171                         debug("SF: fail to set bank%d\n", bank_sel);
 172                         return ret;
 173                 }
 174 #endif
 175                 spi_flash_addr(offset, cmd);
 176
 177                 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
 178                       cmd[2], cmd[3], offset);
 179
 180                 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
 181                 if (ret < 0) {
 182                         debug("SF: erase failed\n");
 183                         break;
 184                 }
 185
 186                 offset += erase_size;
 187                 len -= erase_size;
 188         }
 189
 190         return ret;
 191 }
 192
 193 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 194                 size_t len, const void *buf)
 195 {
 196         unsigned long byte_addr, page_size;
 197         size_t chunk_len, actual;
 198         u8 cmd[4];
 199         int ret = -1;
 200
 201         page_size = flash->page_size;
 202
 203         cmd[0] = CMD_PAGE_PROGRAM;
 204         for (actual = 0; actual < len; actual += chunk_len) {
 205 #ifdef CONFIG_SPI_FLASH_BAR
 206                 u8 bank_sel;
 207
 208                 bank_sel = offset / SPI_FLASH_16MB_BOUN;
 209
 210                 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 211                 if (ret) {
 212                         debug("SF: fail to set bank%d\n", bank_sel);
 213                         return ret;
 214                 }
 215 #endif
 216                 byte_addr = offset % page_size;
 217                 chunk_len = min(len - actual, page_size - byte_addr);
 218
 219                 if (flash->spi->max_write_size)
 220                         chunk_len = min(chunk_len, flash->spi->max_write_size);
 221
 222                 spi_flash_addr(offset, cmd);
 223
 224                 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
 225                       buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 226
 227                 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
 228                                         buf + actual, chunk_len);
 229                 if (ret < 0) {
 230                         debug("SF: write failed\n");
 231                         break;
 232                 }
 233
 234                 offset += chunk_len;
 235         }
 236
 237         return ret;
 238 }
 239
 240 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 241                 size_t cmd_len, void *data, size_t data_len)
 242 {
 243         struct spi_slave *spi = flash->spi;
 244         int ret;
 245
 246         ret = spi_claim_bus(flash->spi);
 247         if (ret) {
 248                 debug("SF: unable to claim SPI bus\n");
 249                 return ret;
 250         }
 251
 252         ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
 253         if (ret < 0) {
 254                 debug("SF: read cmd failed\n");
 255                 return ret;
 256         }
 257
 258         spi_release_bus(spi);
 259
 260         return ret;
 261 }
 262
 263 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 264                 size_t len, void *data)
 265 {
 266         u8 cmd[5], bank_sel = 0;
 267         u32 remain_len, read_len;
 268         int ret = -1;
 269
 270         /* Handle memory-mapped SPI */
 271         if (flash->memory_map) {
 272                 memcpy(data, flash->memory_map + offset, len);
 273                 return 0;
 274         }
 275
 276         cmd[0] = CMD_READ_ARRAY_FAST;
 277         cmd[4] = 0x00;
 278
 279         while (len) {
 280 #ifdef CONFIG_SPI_FLASH_BAR
 281                 bank_sel = offset / SPI_FLASH_16MB_BOUN;
 282
 283                 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 284                 if (ret) {
 285                         debug("SF: fail to set bank%d\n", bank_sel);
 286                         return ret;
 287                 }
 288 #endif
 289                 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
 290                 if (len < remain_len)
 291                         read_len = len;
 292                 else
 293                         read_len = remain_len;
 294
 295                 spi_flash_addr(offset, cmd);
 296
 297                 ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
 298                                                         data, read_len);
 299                 if (ret < 0) {
 300                         debug("SF: read failed\n");
 301                         break;
 302                 }
 303
 304                 offset += read_len;
 305                 len -= read_len;
 306                 data += read_len;
 307         }
 308
 309         return ret;
 310 }
 311
 312 #ifdef CONFIG_SPI_FLASH_SST
 313 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
 314 {
 315         int ret;
 316         u8 cmd[4] = {
 317                 CMD_SST_BP,
 318                 offset >> 16,
 319                 offset >> 8,
 320                 offset,
 321         };
 322
 323         debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
 324               spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
 325
 326         ret = spi_flash_cmd_write_enable(flash);
 327         if (ret)
 328                 return ret;
 329
 330         ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
 331         if (ret)
 332                 return ret;
 333
 334         return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 335 }
 336
 337 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
 338                 const void *buf)
 339 {
 340         size_t actual, cmd_len;
 341         int ret;
 342         u8 cmd[4];
 343
 344         ret = spi_claim_bus(flash->spi);
 345         if (ret) {
 346                 debug("SF: Unable to claim SPI bus\n");
 347                 return ret;
 348         }
 349
 350         /* If the data is not word aligned, write out leading single byte */
 351         actual = offset % 2;
 352         if (actual) {
 353                 ret = sst_byte_write(flash, offset, buf);
 354                 if (ret)
 355                         goto done;
 356         }
 357         offset += actual;
 358
 359         ret = spi_flash_cmd_write_enable(flash);
 360         if (ret)
 361                 goto done;
 362
 363         cmd_len = 4;
 364         cmd[0] = CMD_SST_AAI_WP;
 365         cmd[1] = offset >> 16;
 366         cmd[2] = offset >> 8;
 367         cmd[3] = offset;
 368
 369         for (; actual < len - 1; actual += 2) {
 370                 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
 371                       spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
 372                       cmd[0], offset);
 373
 374                 ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
 375                                         buf + actual, 2);
 376                 if (ret) {
 377                         debug("SF: sst word program failed\n");
 378                         break;
 379                 }
 380
 381                 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 382                 if (ret)
 383                         break;
 384
 385                 cmd_len = 1;
 386                 offset += 2;
 387         }
 388
 389         if (!ret)
 390                 ret = spi_flash_cmd_write_disable(flash);
 391
 392         /* If there is a single trailing byte, write it out */
 393         if (!ret && actual != len)
 394                 ret = sst_byte_write(flash, offset, buf + actual);
 395
 396  done:
 397         debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
 398               ret ? "failure" : "success", len, offset - actual);
 399
 400         spi_release_bus(flash->spi);
 401         return ret;
 402 }
 403 #endif