4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
7 * Copyright (C) 2008 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <spi_flash.h>
18 #include <linux/log2.h>
19 #include <linux/sizes.h>
22 #include "sf_internal.h"
24 DECLARE_GLOBAL_DATA_PTR;
26 static void spi_flash_addr(u32 addr, u8 *cmd)
28 /* cmd[0] is actual command */
34 static int read_sr(struct spi_flash *flash, u8 *rs)
39 cmd = CMD_READ_STATUS;
40 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
42 debug("SF: fail to read status register\n");
49 static int read_fsr(struct spi_flash *flash, u8 *fsr)
52 const u8 cmd = CMD_FLAG_STATUS;
54 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
56 debug("SF: fail to read flag status register\n");
63 static int write_sr(struct spi_flash *flash, u8 ws)
68 cmd = CMD_WRITE_STATUS;
69 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
71 debug("SF: fail to write status register\n");
78 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
79 static int read_cr(struct spi_flash *flash, u8 *rc)
84 cmd = CMD_READ_CONFIG;
85 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
87 debug("SF: fail to read config register\n");
94 static int write_cr(struct spi_flash *flash, u8 wc)
100 ret = read_sr(flash, &data[0]);
104 cmd = CMD_WRITE_STATUS;
106 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
108 debug("SF: fail to write config register\n");
116 #ifdef CONFIG_SPI_FLASH_BAR
118 * This "clean_bar" is necessary in a situation when one was accessing
119 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
121 * After it the BA24 bit shall be cleared to allow access to correct
122 * memory region after SW reset (by calling "reset" command).
124 * Otherwise, the BA24 bit may be left set and then after reset, the
125 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
127 static int clean_bar(struct spi_flash *flash)
129 u8 cmd, bank_sel = 0;
131 if (flash->bank_curr == 0)
133 cmd = flash->bank_write_cmd;
135 return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
138 static int write_bar(struct spi_flash *flash, u32 offset)
143 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
144 if (bank_sel == flash->bank_curr)
147 cmd = flash->bank_write_cmd;
148 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
150 debug("SF: fail to write bank register\n");
155 flash->bank_curr = bank_sel;
156 return flash->bank_curr;
159 static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
164 if (flash->size <= SPI_FLASH_16MB_BOUN)
167 switch (JEDEC_MFR(info)) {
168 case SPI_FLASH_CFI_MFR_SPANSION:
169 flash->bank_read_cmd = CMD_BANKADDR_BRRD;
170 flash->bank_write_cmd = CMD_BANKADDR_BRWR;
173 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
174 flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
177 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
180 debug("SF: fail to read bank addr register\n");
185 flash->bank_curr = curr_bank;
190 #ifdef CONFIG_SF_DUAL_FLASH
191 static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
193 switch (flash->dual_flash) {
194 case SF_DUAL_STACKED_FLASH:
195 if (*addr >= (flash->size >> 1)) {
196 *addr -= flash->size >> 1;
197 flash->flags |= SNOR_F_USE_UPAGE;
199 flash->flags &= ~SNOR_F_USE_UPAGE;
202 case SF_DUAL_PARALLEL_FLASH:
203 *addr >>= flash->shift;
206 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
212 static int spi_flash_sr_ready(struct spi_flash *flash)
217 ret = read_sr(flash, &sr);
221 return !(sr & STATUS_WIP);
224 static int spi_flash_fsr_ready(struct spi_flash *flash)
229 ret = read_fsr(flash, &fsr);
233 return fsr & STATUS_PEC;
236 static int spi_flash_ready(struct spi_flash *flash)
240 sr = spi_flash_sr_ready(flash);
245 if (flash->flags & SNOR_F_USE_FSR) {
246 fsr = spi_flash_fsr_ready(flash);
254 static int spi_flash_wait_till_ready(struct spi_flash *flash,
255 unsigned long timeout)
257 unsigned long timebase;
260 timebase = get_timer(0);
262 while (get_timer(timebase) < timeout) {
263 ret = spi_flash_ready(flash);
270 printf("SF: Timeout!\n");
275 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
276 size_t cmd_len, const void *buf, size_t buf_len)
278 struct spi_slave *spi = flash->spi;
279 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
283 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
285 ret = spi_claim_bus(spi);
287 debug("SF: unable to claim SPI bus\n");
291 ret = spi_flash_cmd_write_enable(flash);
293 debug("SF: enabling write failed\n");
297 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
299 debug("SF: write cmd failed\n");
303 ret = spi_flash_wait_till_ready(flash, timeout);
305 debug("SF: write %s timed out\n",
306 timeout == SPI_FLASH_PROG_TIMEOUT ?
307 "program" : "page erase");
311 spi_release_bus(spi);
316 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
318 u32 erase_size, erase_addr;
319 u8 cmd[SPI_FLASH_CMD_LEN];
322 erase_size = flash->erase_size;
323 if (offset % erase_size || len % erase_size) {
324 printf("SF: Erase offset/length not multiple of erase size\n");
328 if (flash->flash_is_locked) {
329 if (flash->flash_is_locked(flash, offset, len) > 0) {
330 printf("offset 0x%x is protected and cannot be erased\n",
336 cmd[0] = flash->erase_cmd;
340 #ifdef CONFIG_SF_DUAL_FLASH
341 if (flash->dual_flash > SF_SINGLE_FLASH)
342 spi_flash_dual(flash, &erase_addr);
344 #ifdef CONFIG_SPI_FLASH_BAR
345 ret = write_bar(flash, erase_addr);
349 spi_flash_addr(erase_addr, cmd);
351 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
352 cmd[2], cmd[3], erase_addr);
354 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
356 debug("SF: erase failed\n");
360 offset += erase_size;
364 #ifdef CONFIG_SPI_FLASH_BAR
365 ret = clean_bar(flash);
371 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
372 size_t len, const void *buf)
374 struct spi_slave *spi = flash->spi;
375 unsigned long byte_addr, page_size;
377 size_t chunk_len, actual;
378 u8 cmd[SPI_FLASH_CMD_LEN];
381 page_size = flash->page_size;
383 if (flash->flash_is_locked) {
384 if (flash->flash_is_locked(flash, offset, len) > 0) {
385 printf("offset 0x%x is protected and cannot be written\n",
391 cmd[0] = flash->write_cmd;
392 for (actual = 0; actual < len; actual += chunk_len) {
395 #ifdef CONFIG_SF_DUAL_FLASH
396 if (flash->dual_flash > SF_SINGLE_FLASH)
397 spi_flash_dual(flash, &write_addr);
399 #ifdef CONFIG_SPI_FLASH_BAR
400 ret = write_bar(flash, write_addr);
404 byte_addr = offset % page_size;
405 chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
407 if (spi->max_write_size)
408 chunk_len = min(chunk_len,
409 spi->max_write_size - sizeof(cmd));
411 spi_flash_addr(write_addr, cmd);
413 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
414 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
416 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
417 buf + actual, chunk_len);
419 debug("SF: write failed\n");
426 #ifdef CONFIG_SPI_FLASH_BAR
427 ret = clean_bar(flash);
433 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
434 size_t cmd_len, void *data, size_t data_len)
436 struct spi_slave *spi = flash->spi;
439 ret = spi_claim_bus(spi);
441 debug("SF: unable to claim SPI bus\n");
445 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
447 debug("SF: read cmd failed\n");
451 spi_release_bus(spi);
457 * TODO: remove the weak after all the other spi_flash_copy_mmap
458 * implementations removed from drivers
460 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
463 if (!dma_memcpy(data, offset, len))
466 memcpy(data, offset, len);
469 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
470 size_t len, void *data)
472 struct spi_slave *spi = flash->spi;
474 u32 remain_len, read_len, read_addr;
478 /* Handle memory-mapped SPI */
479 if (flash->memory_map) {
480 ret = spi_claim_bus(spi);
482 debug("SF: unable to claim SPI bus\n");
485 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
486 spi_flash_copy_mmap(data, flash->memory_map + offset, len);
487 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
488 spi_release_bus(spi);
492 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
493 cmd = calloc(1, cmdsz);
495 debug("SF: Failed to allocate cmd\n");
499 cmd[0] = flash->read_cmd;
503 #ifdef CONFIG_SF_DUAL_FLASH
504 if (flash->dual_flash > SF_SINGLE_FLASH)
505 spi_flash_dual(flash, &read_addr);
507 #ifdef CONFIG_SPI_FLASH_BAR
508 ret = write_bar(flash, read_addr);
511 bank_sel = flash->bank_curr;
513 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
514 (bank_sel + 1)) - offset;
515 if (len < remain_len)
518 read_len = remain_len;
520 if (spi->max_read_size)
521 read_len = min(read_len, spi->max_read_size);
523 spi_flash_addr(read_addr, cmd);
525 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
527 debug("SF: read failed\n");
536 #ifdef CONFIG_SPI_FLASH_BAR
537 ret = clean_bar(flash);
544 #ifdef CONFIG_SPI_FLASH_SST
545 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
549 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
551 case SST26_CTL_UNLOCK:
552 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
554 case SST26_CTL_CHECK:
555 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
562 * sst26wf016/sst26wf032/sst26wf064 have next block protection:
563 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
564 * 1x - 32 KByte blocks - write protection bits
565 * rest - 64 KByte blocks - write protection bits
566 * 1x - 32 KByte blocks - write protection bits
567 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
569 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
570 * will be treated as single block.
574 * Lock, unlock or check lock status of the flash region of the flash (depending
575 * on the lock_ctl value)
577 static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl)
579 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
580 bool lower_64k = false, upper_64k = false;
581 u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
584 /* Check length and offset for 64k alignment */
585 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
588 if (ofs + len > flash->size)
591 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
592 if (flash->size != SZ_2M &&
593 flash->size != SZ_4M &&
594 flash->size != SZ_8M)
597 bpr_size = 2 + (flash->size / SZ_64K / 8);
599 cmd = SST26_CMD_READ_BPR;
600 ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size);
602 printf("SF: fail to read block-protection register\n");
606 rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
607 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
609 upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
610 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
612 /* Lower bits in block-protection register are about 64k region */
613 bpr_ptr = lptr_64k / SZ_64K - 1;
615 /* Process 64K blocks region */
616 while (lptr_64k < rptr_64k) {
617 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
624 /* 32K and 8K region bits in BPR are after 64k region bits */
625 bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
627 /* Process lower 32K block region */
629 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
634 /* Process upper 32K block region */
636 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
641 /* Process lower 8K block regions */
642 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
644 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
647 /* In 8K area BPR has both read and write protection bits */
651 /* Process upper 8K block regions */
652 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
654 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
657 /* In 8K area BPR has both read and write protection bits */
661 /* If we check region status we don't need to write BPR back */
662 if (ctl == SST26_CTL_CHECK)
665 cmd = SST26_CMD_WRITE_BPR;
666 ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size);
668 printf("SF: fail to write block-protection register\n");
675 static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len)
677 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK);
680 static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len)
682 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK);
686 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
687 * and negative on errors.
689 static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
692 * is_locked function is used for check before reading or erasing flash
693 * region, so offset and length might be not 64k allighned, so adjust
694 * them to be 64k allighned as sst26_lock_ctl works only with 64k
697 ofs -= ofs & (SZ_64K - 1);
698 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
700 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK);
703 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
705 struct spi_slave *spi = flash->spi;
714 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
715 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
717 ret = spi_flash_cmd_write_enable(flash);
721 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
725 return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
728 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
731 struct spi_slave *spi = flash->spi;
732 size_t actual, cmd_len;
736 ret = spi_claim_bus(spi);
738 debug("SF: Unable to claim SPI bus\n");
742 /* If the data is not word aligned, write out leading single byte */
745 ret = sst_byte_write(flash, offset, buf);
751 ret = spi_flash_cmd_write_enable(flash);
756 cmd[0] = CMD_SST_AAI_WP;
757 cmd[1] = offset >> 16;
758 cmd[2] = offset >> 8;
761 for (; actual < len - 1; actual += 2) {
762 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
763 spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
766 ret = spi_flash_cmd_write(spi, cmd, cmd_len,
769 debug("SF: sst word program failed\n");
773 ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
782 ret = spi_flash_cmd_write_disable(flash);
784 /* If there is a single trailing byte, write it out */
785 if (!ret && actual != len)
786 ret = sst_byte_write(flash, offset, buf + actual);
789 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
790 ret ? "failure" : "success", len, offset - actual);
792 spi_release_bus(spi);
796 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
799 struct spi_slave *spi = flash->spi;
803 ret = spi_claim_bus(spi);
805 debug("SF: Unable to claim SPI bus\n");
809 for (actual = 0; actual < len; actual++) {
810 ret = sst_byte_write(flash, offset, buf + actual);
812 debug("SF: sst byte program failed\n");
819 ret = spi_flash_cmd_write_disable(flash);
821 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
822 ret ? "failure" : "success", len, offset - actual);
824 spi_release_bus(spi);
829 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
830 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
833 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
834 int shift = ffs(mask) - 1;
842 pow = ((sr & mask) ^ mask) >> shift;
843 *len = flash->size >> pow;
844 *ofs = flash->size - *len;
849 * Return 1 if the entire region is locked, 0 otherwise
851 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len,
857 stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
859 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
863 * Check if a region of the flash is (completely) locked. See stm_lock() for
866 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
867 * negative on errors.
869 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
874 status = read_sr(flash, &sr);
878 return stm_is_locked_sr(flash, ofs, len, sr);
882 * Lock a region of the flash. Compatible with ST Micro and similar flash.
883 * Supports only the block protection bits BP{0,1,2} in the status register
884 * (SR). Does not support these features found in newer SR bitfields:
885 * - TB: top/bottom protect - only handle TB=0 (top protect)
886 * - SEC: sector/block protect - only handle SEC=0 (block protect)
887 * - CMP: complement protect - only support CMP=0 (range is not complemented)
889 * Sample table portion for 8MB flash (Winbond w25q64fw):
891 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
892 * --------------------------------------------------------------------------
893 * X | X | 0 | 0 | 0 | NONE | NONE
894 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
895 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
896 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
897 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
898 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
899 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
900 * X | X | 1 | 1 | 1 | 8 MB | ALL
902 * Returns negative on errors, 0 on success.
904 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
906 u8 status_old, status_new;
907 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
908 u8 shift = ffs(mask) - 1, pow, val;
911 ret = read_sr(flash, &status_old);
915 /* SPI NOR always locks to the end */
916 if (ofs + len != flash->size) {
917 /* Does combined region extend to end? */
918 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
921 len = flash->size - ofs;
925 * Need smallest pow such that:
927 * 1 / (2^pow) <= (len / size)
929 * so (assuming power-of-2 size) we do:
931 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
933 pow = ilog2(flash->size) - ilog2(len);
934 val = mask - (pow << shift);
938 /* Don't "lock" with no region! */
942 status_new = (status_old & ~mask) | val;
944 /* Only modify protection if it will not unlock other areas */
945 if ((status_new & mask) <= (status_old & mask))
948 write_sr(flash, status_new);
954 * Unlock a region of the flash. See stm_lock() for more info
956 * Returns negative on errors, 0 on success.
958 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
960 uint8_t status_old, status_new;
961 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
962 u8 shift = ffs(mask) - 1, pow, val;
965 ret = read_sr(flash, &status_old);
969 /* Cannot unlock; would unlock larger region than requested */
970 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
974 * Need largest pow such that:
976 * 1 / (2^pow) >= (len / size)
978 * so (assuming power-of-2 size) we do:
980 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
982 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
983 if (ofs + len == flash->size) {
984 val = 0; /* fully unlocked */
986 val = mask - (pow << shift);
987 /* Some power-of-two sizes are not supported */
992 status_new = (status_old & ~mask) | val;
994 /* Only modify protection if it will not lock other areas */
995 if ((status_new & mask) >= (status_old & mask))
998 write_sr(flash, status_new);
1005 #ifdef CONFIG_SPI_FLASH_MACRONIX
1006 static int macronix_quad_enable(struct spi_flash *flash)
1011 ret = read_sr(flash, &qeb_status);
1015 if (qeb_status & STATUS_QEB_MXIC)
1018 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
1022 /* read SR and check it */
1023 ret = read_sr(flash, &qeb_status);
1024 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
1025 printf("SF: Macronix SR Quad bit not clear\n");
1033 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1034 static int spansion_quad_enable(struct spi_flash *flash)
1039 ret = read_cr(flash, &qeb_status);
1043 if (qeb_status & STATUS_QEB_WINSPAN)
1046 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
1050 /* read CR and check it */
1051 ret = read_cr(flash, &qeb_status);
1052 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
1053 printf("SF: Spansion CR Quad bit not clear\n");
1061 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
1064 u8 id[SPI_FLASH_MAX_ID_LEN];
1065 const struct spi_flash_info *info;
1067 tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
1069 printf("SF: error %d reading JEDEC ID\n", tmp);
1070 return ERR_PTR(tmp);
1073 info = spi_flash_ids;
1074 for (; info->name != NULL; info++) {
1076 if (!memcmp(info->id, id, info->id_len))
1081 printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1082 id[0], id[1], id[2]);
1083 return ERR_PTR(-ENODEV);
1086 static int set_quad_mode(struct spi_flash *flash,
1087 const struct spi_flash_info *info)
1089 switch (JEDEC_MFR(info)) {
1090 #ifdef CONFIG_SPI_FLASH_MACRONIX
1091 case SPI_FLASH_CFI_MFR_MACRONIX:
1092 return macronix_quad_enable(flash);
1094 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1095 case SPI_FLASH_CFI_MFR_SPANSION:
1096 case SPI_FLASH_CFI_MFR_WINBOND:
1097 return spansion_quad_enable(flash);
1099 #ifdef CONFIG_SPI_FLASH_STMICRO
1100 case SPI_FLASH_CFI_MFR_STMICRO:
1101 debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
1105 printf("SF: Need set QEB func for %02x flash\n",
1111 #if CONFIG_IS_ENABLED(OF_CONTROL)
1112 int spi_flash_decode_fdt(struct spi_flash *flash)
1114 #ifdef CONFIG_DM_SPI_FLASH
1118 addr = dev_read_addr_size(flash->dev, "memory-map", &size);
1119 if (addr == FDT_ADDR_T_NONE) {
1120 debug("%s: Cannot decode address\n", __func__);
1124 if (flash->size > size) {
1125 debug("%s: Memory map must cover entire device\n", __func__);
1128 flash->memory_map = map_sysmem(addr, size);
1133 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
1135 int spi_flash_scan(struct spi_flash *flash)
1137 struct spi_slave *spi = flash->spi;
1138 const struct spi_flash_info *info = NULL;
1141 info = spi_flash_read_id(flash);
1142 if (IS_ERR_OR_NULL(info))
1146 * Flash powers up read-only, so clear BP# bits.
1148 * Note on some flash (like Macronix), QE (quad enable) bit is in the
1149 * same status register as BP# bits, and we need preserve its original
1150 * value during a reboot cycle as this is required by some platforms
1151 * (like Intel ICH SPI controller working under descriptor mode).
1153 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
1154 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) ||
1155 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) {
1158 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
1159 read_sr(flash, &sr);
1160 sr &= STATUS_QEB_MXIC;
1162 write_sr(flash, sr);
1165 flash->name = info->name;
1166 flash->memory_map = spi->memory_map;
1168 if (info->flags & SST_WR)
1169 flash->flags |= SNOR_F_SST_WR;
1171 #ifndef CONFIG_DM_SPI_FLASH
1172 flash->write = spi_flash_cmd_write_ops;
1173 #if defined(CONFIG_SPI_FLASH_SST)
1174 if (flash->flags & SNOR_F_SST_WR) {
1175 if (spi->mode & SPI_TX_BYTE)
1176 flash->write = sst_write_bp;
1178 flash->write = sst_write_wp;
1181 flash->erase = spi_flash_cmd_erase_ops;
1182 flash->read = spi_flash_cmd_read_ops;
1185 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
1186 /* NOR protection support for STmicro/Micron chips and similar */
1187 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
1188 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
1189 flash->flash_lock = stm_lock;
1190 flash->flash_unlock = stm_unlock;
1191 flash->flash_is_locked = stm_is_locked;
1195 /* sst26wf series block protection implementation differs from other series */
1196 #if defined(CONFIG_SPI_FLASH_SST)
1197 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) {
1198 flash->flash_lock = sst26_lock;
1199 flash->flash_unlock = sst26_unlock;
1200 flash->flash_is_locked = sst26_is_locked;
1204 /* Compute the flash size */
1205 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
1206 flash->page_size = info->page_size;
1208 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
1209 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
1210 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
1213 if (JEDEC_EXT(info) == 0x4d00) {
1214 if ((JEDEC_ID(info) != 0x0215) &&
1215 (JEDEC_ID(info) != 0x0216))
1216 flash->page_size = 512;
1218 flash->page_size <<= flash->shift;
1219 flash->sector_size = info->sector_size << flash->shift;
1220 flash->size = flash->sector_size * info->n_sectors << flash->shift;
1221 #ifdef CONFIG_SF_DUAL_FLASH
1222 if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
1226 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1227 /* Compute erase sector and command */
1228 if (info->flags & SECT_4K) {
1229 flash->erase_cmd = CMD_ERASE_4K;
1230 flash->erase_size = 4096 << flash->shift;
1234 flash->erase_cmd = CMD_ERASE_64K;
1235 flash->erase_size = flash->sector_size;
1238 /* Now erase size becomes valid sector size */
1239 flash->sector_size = flash->erase_size;
1241 /* Look for read commands */
1242 flash->read_cmd = CMD_READ_ARRAY_FAST;
1243 if (spi->mode & SPI_RX_SLOW)
1244 flash->read_cmd = CMD_READ_ARRAY_SLOW;
1245 else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
1246 flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
1247 else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
1248 flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
1250 /* Look for write commands */
1251 if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
1252 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
1254 /* Go for default supported write cmd */
1255 flash->write_cmd = CMD_PAGE_PROGRAM;
1257 /* Set the quad enable bit - only for quad commands */
1258 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
1259 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
1260 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
1261 ret = set_quad_mode(flash, info);
1263 debug("SF: Fail to set QEB for %02x\n",
1269 /* Read dummy_byte: dummy byte is determined based on the
1270 * dummy cycles of a particular command.
1271 * Fast commands - dummy_byte = dummy_cycles/8
1272 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
1273 * For I/O commands except cmd[0] everything goes on no.of lines
1274 * based on particular command but incase of fast commands except
1275 * data all go on single line irrespective of command.
1277 switch (flash->read_cmd) {
1278 case CMD_READ_QUAD_IO_FAST:
1279 flash->dummy_byte = 2;
1281 case CMD_READ_ARRAY_SLOW:
1282 flash->dummy_byte = 0;
1285 flash->dummy_byte = 1;
1288 #ifdef CONFIG_SPI_FLASH_STMICRO
1289 if (info->flags & E_FSR)
1290 flash->flags |= SNOR_F_USE_FSR;
1293 /* Configure the BAR - discover bank cmds and read current bank */
1294 #ifdef CONFIG_SPI_FLASH_BAR
1295 ret = read_bar(flash, info);
1300 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1301 ret = spi_flash_decode_fdt(flash);
1303 debug("SF: FDT decode error\n");
1308 #ifndef CONFIG_SPL_BUILD
1309 printf("SF: Detected %s with page size ", flash->name);
1310 print_size(flash->page_size, ", erase size ");
1311 print_size(flash->erase_size, ", total ");
1312 print_size(flash->size, "");
1313 if (flash->memory_map)
1314 printf(", mapped at %p", flash->memory_map);
1318 #ifndef CONFIG_SPI_FLASH_BAR
1319 if (((flash->dual_flash == SF_SINGLE_FLASH) &&
1320 (flash->size > SPI_FLASH_16MB_BOUN)) ||
1321 ((flash->dual_flash > SF_SINGLE_FLASH) &&
1322 (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
1323 puts("SF: Warning - Only lower 16MiB accessible,");
1324 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");