1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
7 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
8 * Copyright (C) 2008 Atmel Corporation
16 #include <spi_flash.h>
17 #include <linux/log2.h>
18 #include <linux/sizes.h>
21 #include "sf_internal.h"
23 static void spi_flash_addr(u32 addr, u8 *cmd)
25 /* cmd[0] is actual command */
31 static int read_sr(struct spi_flash *flash, u8 *rs)
36 cmd = CMD_READ_STATUS;
37 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
39 debug("SF: fail to read status register\n");
46 static int read_fsr(struct spi_flash *flash, u8 *fsr)
49 const u8 cmd = CMD_FLAG_STATUS;
51 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
53 debug("SF: fail to read flag status register\n");
60 static int write_sr(struct spi_flash *flash, u8 ws)
65 cmd = CMD_WRITE_STATUS;
66 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
68 debug("SF: fail to write status register\n");
75 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
76 static int read_cr(struct spi_flash *flash, u8 *rc)
81 cmd = CMD_READ_CONFIG;
82 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
84 debug("SF: fail to read config register\n");
91 static int write_cr(struct spi_flash *flash, u8 wc)
97 ret = read_sr(flash, &data[0]);
101 cmd = CMD_WRITE_STATUS;
103 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
105 debug("SF: fail to write config register\n");
113 #ifdef CONFIG_SPI_FLASH_BAR
115 * This "clean_bar" is necessary in a situation when one was accessing
116 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
118 * After it the BA24 bit shall be cleared to allow access to correct
119 * memory region after SW reset (by calling "reset" command).
121 * Otherwise, the BA24 bit may be left set and then after reset, the
122 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
124 static int clean_bar(struct spi_flash *flash)
126 u8 cmd, bank_sel = 0;
128 if (flash->bank_curr == 0)
130 cmd = flash->bank_write_cmd;
131 flash->bank_curr = 0;
133 return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
136 static int write_bar(struct spi_flash *flash, u32 offset)
141 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
142 if (bank_sel == flash->bank_curr)
145 cmd = flash->bank_write_cmd;
146 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
148 debug("SF: fail to write bank register\n");
153 flash->bank_curr = bank_sel;
154 return flash->bank_curr;
157 static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
162 if (flash->size <= SPI_FLASH_16MB_BOUN)
165 switch (JEDEC_MFR(info)) {
166 case SPI_FLASH_CFI_MFR_SPANSION:
167 flash->bank_read_cmd = CMD_BANKADDR_BRRD;
168 flash->bank_write_cmd = CMD_BANKADDR_BRWR;
171 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
172 flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
175 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
178 debug("SF: fail to read bank addr register\n");
183 flash->bank_curr = curr_bank;
188 #ifdef CONFIG_SF_DUAL_FLASH
189 static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
191 switch (flash->dual_flash) {
192 case SF_DUAL_STACKED_FLASH:
193 if (*addr >= (flash->size >> 1)) {
194 *addr -= flash->size >> 1;
195 flash->flags |= SNOR_F_USE_UPAGE;
197 flash->flags &= ~SNOR_F_USE_UPAGE;
200 case SF_DUAL_PARALLEL_FLASH:
201 *addr >>= flash->shift;
204 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
210 static int spi_flash_sr_ready(struct spi_flash *flash)
215 ret = read_sr(flash, &sr);
219 return !(sr & STATUS_WIP);
222 static int spi_flash_fsr_ready(struct spi_flash *flash)
227 ret = read_fsr(flash, &fsr);
231 return fsr & STATUS_PEC;
234 static int spi_flash_ready(struct spi_flash *flash)
238 sr = spi_flash_sr_ready(flash);
243 if (flash->flags & SNOR_F_USE_FSR) {
244 fsr = spi_flash_fsr_ready(flash);
252 static int spi_flash_wait_till_ready(struct spi_flash *flash,
253 unsigned long timeout)
255 unsigned long timebase;
258 timebase = get_timer(0);
260 while (get_timer(timebase) < timeout) {
261 ret = spi_flash_ready(flash);
268 printf("SF: Timeout!\n");
273 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
274 size_t cmd_len, const void *buf, size_t buf_len)
276 struct spi_slave *spi = flash->spi;
277 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
281 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
283 ret = spi_claim_bus(spi);
285 debug("SF: unable to claim SPI bus\n");
289 ret = spi_flash_cmd_write_enable(flash);
291 debug("SF: enabling write failed\n");
295 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
297 debug("SF: write cmd failed\n");
301 ret = spi_flash_wait_till_ready(flash, timeout);
303 debug("SF: write %s timed out\n",
304 timeout == SPI_FLASH_PROG_TIMEOUT ?
305 "program" : "page erase");
309 spi_release_bus(spi);
314 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
316 u32 erase_size, erase_addr;
317 u8 cmd[SPI_FLASH_CMD_LEN];
320 erase_size = flash->erase_size;
321 if (offset % erase_size || len % erase_size) {
322 printf("SF: Erase offset/length not multiple of erase size\n");
326 if (flash->flash_is_locked) {
327 if (flash->flash_is_locked(flash, offset, len) > 0) {
328 printf("offset 0x%x is protected and cannot be erased\n",
334 cmd[0] = flash->erase_cmd;
338 #ifdef CONFIG_SF_DUAL_FLASH
339 if (flash->dual_flash > SF_SINGLE_FLASH)
340 spi_flash_dual(flash, &erase_addr);
342 #ifdef CONFIG_SPI_FLASH_BAR
343 ret = write_bar(flash, erase_addr);
347 spi_flash_addr(erase_addr, cmd);
349 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
350 cmd[2], cmd[3], erase_addr);
352 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
354 debug("SF: erase failed\n");
358 offset += erase_size;
362 #ifdef CONFIG_SPI_FLASH_BAR
363 ret = clean_bar(flash);
369 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
370 size_t len, const void *buf)
372 struct spi_slave *spi = flash->spi;
373 unsigned long byte_addr, page_size;
375 size_t chunk_len, actual;
376 u8 cmd[SPI_FLASH_CMD_LEN];
379 page_size = flash->page_size;
381 if (flash->flash_is_locked) {
382 if (flash->flash_is_locked(flash, offset, len) > 0) {
383 printf("offset 0x%x is protected and cannot be written\n",
389 cmd[0] = flash->write_cmd;
390 for (actual = 0; actual < len; actual += chunk_len) {
393 #ifdef CONFIG_SF_DUAL_FLASH
394 if (flash->dual_flash > SF_SINGLE_FLASH)
395 spi_flash_dual(flash, &write_addr);
397 #ifdef CONFIG_SPI_FLASH_BAR
398 ret = write_bar(flash, write_addr);
402 byte_addr = offset % page_size;
403 chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
405 if (spi->max_write_size)
406 chunk_len = min(chunk_len,
407 spi->max_write_size - sizeof(cmd));
409 spi_flash_addr(write_addr, cmd);
411 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
412 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
414 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
415 buf + actual, chunk_len);
417 debug("SF: write failed\n");
424 #ifdef CONFIG_SPI_FLASH_BAR
425 ret = clean_bar(flash);
431 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
432 size_t cmd_len, void *data, size_t data_len)
434 struct spi_slave *spi = flash->spi;
437 ret = spi_claim_bus(spi);
439 debug("SF: unable to claim SPI bus\n");
443 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
445 debug("SF: read cmd failed\n");
449 spi_release_bus(spi);
455 * TODO: remove the weak after all the other spi_flash_copy_mmap
456 * implementations removed from drivers
458 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
461 if (!dma_memcpy(data, offset, len))
464 memcpy(data, offset, len);
467 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
468 size_t len, void *data)
470 struct spi_slave *spi = flash->spi;
472 u32 remain_len, read_len, read_addr;
476 /* Handle memory-mapped SPI */
477 if (flash->memory_map) {
478 ret = spi_claim_bus(spi);
480 debug("SF: unable to claim SPI bus\n");
483 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
484 spi_flash_copy_mmap(data, flash->memory_map + offset, len);
485 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
486 spi_release_bus(spi);
490 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
493 cmd[0] = flash->read_cmd;
497 #ifdef CONFIG_SF_DUAL_FLASH
498 if (flash->dual_flash > SF_SINGLE_FLASH)
499 spi_flash_dual(flash, &read_addr);
501 #ifdef CONFIG_SPI_FLASH_BAR
502 ret = write_bar(flash, read_addr);
505 bank_sel = flash->bank_curr;
507 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
508 (bank_sel + 1)) - offset;
509 if (len < remain_len)
512 read_len = remain_len;
514 if (spi->max_read_size)
515 read_len = min(read_len, spi->max_read_size);
517 spi_flash_addr(read_addr, cmd);
519 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
521 debug("SF: read failed\n");
530 #ifdef CONFIG_SPI_FLASH_BAR
531 ret = clean_bar(flash);
537 #ifdef CONFIG_SPI_FLASH_SST
538 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
542 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
544 case SST26_CTL_UNLOCK:
545 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
547 case SST26_CTL_CHECK:
548 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
555 * sst26wf016/sst26wf032/sst26wf064 have next block protection:
556 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
557 * 1x - 32 KByte blocks - write protection bits
558 * rest - 64 KByte blocks - write protection bits
559 * 1x - 32 KByte blocks - write protection bits
560 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
562 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
563 * will be treated as single block.
567 * Lock, unlock or check lock status of the flash region of the flash (depending
568 * on the lock_ctl value)
570 static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl)
572 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
573 bool lower_64k = false, upper_64k = false;
574 u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
577 /* Check length and offset for 64k alignment */
578 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
581 if (ofs + len > flash->size)
584 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
585 if (flash->size != SZ_2M &&
586 flash->size != SZ_4M &&
587 flash->size != SZ_8M)
590 bpr_size = 2 + (flash->size / SZ_64K / 8);
592 cmd = SST26_CMD_READ_BPR;
593 ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size);
595 printf("SF: fail to read block-protection register\n");
599 rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
600 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
602 upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
603 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
605 /* Lower bits in block-protection register are about 64k region */
606 bpr_ptr = lptr_64k / SZ_64K - 1;
608 /* Process 64K blocks region */
609 while (lptr_64k < rptr_64k) {
610 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
617 /* 32K and 8K region bits in BPR are after 64k region bits */
618 bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
620 /* Process lower 32K block region */
622 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
627 /* Process upper 32K block region */
629 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
634 /* Process lower 8K block regions */
635 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
637 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
640 /* In 8K area BPR has both read and write protection bits */
644 /* Process upper 8K block regions */
645 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
647 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
650 /* In 8K area BPR has both read and write protection bits */
654 /* If we check region status we don't need to write BPR back */
655 if (ctl == SST26_CTL_CHECK)
658 cmd = SST26_CMD_WRITE_BPR;
659 ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size);
661 printf("SF: fail to write block-protection register\n");
668 static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len)
670 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK);
673 static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len)
675 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK);
679 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
680 * and negative on errors.
682 static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
685 * is_locked function is used for check before reading or erasing flash
686 * region, so offset and length might be not 64k allighned, so adjust
687 * them to be 64k allighned as sst26_lock_ctl works only with 64k
690 ofs -= ofs & (SZ_64K - 1);
691 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
693 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK);
696 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
698 struct spi_slave *spi = flash->spi;
707 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
708 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
710 ret = spi_flash_cmd_write_enable(flash);
714 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
718 return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
721 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
724 struct spi_slave *spi = flash->spi;
725 size_t actual, cmd_len;
729 ret = spi_claim_bus(spi);
731 debug("SF: Unable to claim SPI bus\n");
735 /* If the data is not word aligned, write out leading single byte */
738 ret = sst_byte_write(flash, offset, buf);
744 ret = spi_flash_cmd_write_enable(flash);
749 cmd[0] = CMD_SST_AAI_WP;
750 cmd[1] = offset >> 16;
751 cmd[2] = offset >> 8;
754 for (; actual < len - 1; actual += 2) {
755 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
756 spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
759 ret = spi_flash_cmd_write(spi, cmd, cmd_len,
762 debug("SF: sst word program failed\n");
766 ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
775 ret = spi_flash_cmd_write_disable(flash);
777 /* If there is a single trailing byte, write it out */
778 if (!ret && actual != len)
779 ret = sst_byte_write(flash, offset, buf + actual);
782 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
783 ret ? "failure" : "success", len, offset - actual);
785 spi_release_bus(spi);
789 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
792 struct spi_slave *spi = flash->spi;
796 ret = spi_claim_bus(spi);
798 debug("SF: Unable to claim SPI bus\n");
802 for (actual = 0; actual < len; actual++) {
803 ret = sst_byte_write(flash, offset, buf + actual);
805 debug("SF: sst byte program failed\n");
812 ret = spi_flash_cmd_write_disable(flash);
814 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
815 ret ? "failure" : "success", len, offset - actual);
817 spi_release_bus(spi);
822 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
823 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
826 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
827 int shift = ffs(mask) - 1;
835 pow = ((sr & mask) ^ mask) >> shift;
836 *len = flash->size >> pow;
837 *ofs = flash->size - *len;
842 * Return 1 if the entire region is locked, 0 otherwise
844 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len,
850 stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
852 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
856 * Check if a region of the flash is (completely) locked. See stm_lock() for
859 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
860 * negative on errors.
862 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
867 status = read_sr(flash, &sr);
871 return stm_is_locked_sr(flash, ofs, len, sr);
875 * Lock a region of the flash. Compatible with ST Micro and similar flash.
876 * Supports only the block protection bits BP{0,1,2} in the status register
877 * (SR). Does not support these features found in newer SR bitfields:
878 * - TB: top/bottom protect - only handle TB=0 (top protect)
879 * - SEC: sector/block protect - only handle SEC=0 (block protect)
880 * - CMP: complement protect - only support CMP=0 (range is not complemented)
882 * Sample table portion for 8MB flash (Winbond w25q64fw):
884 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
885 * --------------------------------------------------------------------------
886 * X | X | 0 | 0 | 0 | NONE | NONE
887 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
888 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
889 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
890 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
891 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
892 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
893 * X | X | 1 | 1 | 1 | 8 MB | ALL
895 * Returns negative on errors, 0 on success.
897 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
899 u8 status_old, status_new;
900 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
901 u8 shift = ffs(mask) - 1, pow, val;
904 ret = read_sr(flash, &status_old);
908 /* SPI NOR always locks to the end */
909 if (ofs + len != flash->size) {
910 /* Does combined region extend to end? */
911 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
914 len = flash->size - ofs;
918 * Need smallest pow such that:
920 * 1 / (2^pow) <= (len / size)
922 * so (assuming power-of-2 size) we do:
924 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
926 pow = ilog2(flash->size) - ilog2(len);
927 val = mask - (pow << shift);
931 /* Don't "lock" with no region! */
935 status_new = (status_old & ~mask) | val;
937 /* Only modify protection if it will not unlock other areas */
938 if ((status_new & mask) <= (status_old & mask))
941 write_sr(flash, status_new);
947 * Unlock a region of the flash. See stm_lock() for more info
949 * Returns negative on errors, 0 on success.
951 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
953 uint8_t status_old, status_new;
954 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
955 u8 shift = ffs(mask) - 1, pow, val;
958 ret = read_sr(flash, &status_old);
962 /* Cannot unlock; would unlock larger region than requested */
963 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
967 * Need largest pow such that:
969 * 1 / (2^pow) >= (len / size)
971 * so (assuming power-of-2 size) we do:
973 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
975 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
976 if (ofs + len == flash->size) {
977 val = 0; /* fully unlocked */
979 val = mask - (pow << shift);
980 /* Some power-of-two sizes are not supported */
985 status_new = (status_old & ~mask) | val;
987 /* Only modify protection if it will not lock other areas */
988 if ((status_new & mask) >= (status_old & mask))
991 write_sr(flash, status_new);
998 #ifdef CONFIG_SPI_FLASH_MACRONIX
999 static int macronix_quad_enable(struct spi_flash *flash)
1004 ret = read_sr(flash, &qeb_status);
1008 if (qeb_status & STATUS_QEB_MXIC)
1011 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
1015 /* read SR and check it */
1016 ret = read_sr(flash, &qeb_status);
1017 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
1018 printf("SF: Macronix SR Quad bit not clear\n");
1026 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1027 static int spansion_quad_enable(struct spi_flash *flash)
1032 ret = read_cr(flash, &qeb_status);
1036 if (qeb_status & STATUS_QEB_WINSPAN)
1039 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
1043 /* read CR and check it */
1044 ret = read_cr(flash, &qeb_status);
1045 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
1046 printf("SF: Spansion CR Quad bit not clear\n");
1054 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
1057 u8 id[SPI_FLASH_MAX_ID_LEN];
1058 const struct spi_flash_info *info;
1060 tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
1062 printf("SF: error %d reading JEDEC ID\n", tmp);
1063 return ERR_PTR(tmp);
1066 info = spi_flash_ids;
1067 for (; info->name != NULL; info++) {
1069 if (!memcmp(info->id, id, info->id_len))
1074 printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1075 id[0], id[1], id[2]);
1076 return ERR_PTR(-ENODEV);
1079 static int set_quad_mode(struct spi_flash *flash,
1080 const struct spi_flash_info *info)
1082 switch (JEDEC_MFR(info)) {
1083 #ifdef CONFIG_SPI_FLASH_MACRONIX
1084 case SPI_FLASH_CFI_MFR_MACRONIX:
1085 return macronix_quad_enable(flash);
1087 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1088 case SPI_FLASH_CFI_MFR_SPANSION:
1089 case SPI_FLASH_CFI_MFR_WINBOND:
1090 return spansion_quad_enable(flash);
1092 #ifdef CONFIG_SPI_FLASH_STMICRO
1093 case SPI_FLASH_CFI_MFR_STMICRO:
1094 debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
1098 printf("SF: Need set QEB func for %02x flash\n",
1104 #if CONFIG_IS_ENABLED(OF_CONTROL)
1105 int spi_flash_decode_fdt(struct spi_flash *flash)
1107 #ifdef CONFIG_DM_SPI_FLASH
1111 addr = dev_read_addr_size(flash->dev, "memory-map", &size);
1112 if (addr == FDT_ADDR_T_NONE) {
1113 debug("%s: Cannot decode address\n", __func__);
1117 if (flash->size > size) {
1118 debug("%s: Memory map must cover entire device\n", __func__);
1121 flash->memory_map = map_sysmem(addr, size);
1126 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
1128 int spi_flash_scan(struct spi_flash *flash)
1130 struct spi_slave *spi = flash->spi;
1131 const struct spi_flash_info *info = NULL;
1134 info = spi_flash_read_id(flash);
1135 if (IS_ERR_OR_NULL(info))
1139 * Flash powers up read-only, so clear BP# bits.
1141 * Note on some flash (like Macronix), QE (quad enable) bit is in the
1142 * same status register as BP# bits, and we need preserve its original
1143 * value during a reboot cycle as this is required by some platforms
1144 * (like Intel ICH SPI controller working under descriptor mode).
1146 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
1147 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) ||
1148 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) {
1151 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
1152 read_sr(flash, &sr);
1153 sr &= STATUS_QEB_MXIC;
1155 write_sr(flash, sr);
1158 flash->name = info->name;
1159 flash->memory_map = spi->memory_map;
1161 if (info->flags & SST_WR)
1162 flash->flags |= SNOR_F_SST_WR;
1164 #ifndef CONFIG_DM_SPI_FLASH
1165 flash->write = spi_flash_cmd_write_ops;
1166 #if defined(CONFIG_SPI_FLASH_SST)
1167 if (flash->flags & SNOR_F_SST_WR) {
1168 if (spi->mode & SPI_TX_BYTE)
1169 flash->write = sst_write_bp;
1171 flash->write = sst_write_wp;
1174 flash->erase = spi_flash_cmd_erase_ops;
1175 flash->read = spi_flash_cmd_read_ops;
1178 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
1179 /* NOR protection support for STmicro/Micron chips and similar */
1180 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
1181 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
1182 flash->flash_lock = stm_lock;
1183 flash->flash_unlock = stm_unlock;
1184 flash->flash_is_locked = stm_is_locked;
1188 /* sst26wf series block protection implementation differs from other series */
1189 #if defined(CONFIG_SPI_FLASH_SST)
1190 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) {
1191 flash->flash_lock = sst26_lock;
1192 flash->flash_unlock = sst26_unlock;
1193 flash->flash_is_locked = sst26_is_locked;
1197 /* Compute the flash size */
1198 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
1199 flash->page_size = info->page_size;
1201 * The Spansion S25FS512S, S25FL032P and S25FL064P have 256b pages,
1202 * yet use the 0x4d00 Extended JEDEC code. The rest of the Spansion
1203 * flashes with the 0x4d00 Extended JEDEC code have 512b pages.
1204 * All of the others have 256b pages.
1206 if (JEDEC_EXT(info) == 0x4d00) {
1207 if ((JEDEC_ID(info) != 0x0215) &&
1208 (JEDEC_ID(info) != 0x0216) &&
1209 (JEDEC_ID(info) != 0x0220))
1210 flash->page_size = 512;
1212 flash->page_size <<= flash->shift;
1213 flash->sector_size = info->sector_size << flash->shift;
1214 flash->size = flash->sector_size * info->n_sectors << flash->shift;
1215 #ifdef CONFIG_SF_DUAL_FLASH
1216 if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
1220 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1221 /* Compute erase sector and command */
1222 if (info->flags & SECT_4K) {
1223 flash->erase_cmd = CMD_ERASE_4K;
1224 flash->erase_size = 4096 << flash->shift;
1228 flash->erase_cmd = CMD_ERASE_64K;
1229 flash->erase_size = flash->sector_size;
1232 /* Now erase size becomes valid sector size */
1233 flash->sector_size = flash->erase_size;
1235 /* Look for read commands */
1236 flash->read_cmd = CMD_READ_ARRAY_FAST;
1237 if (spi->mode & SPI_RX_SLOW)
1238 flash->read_cmd = CMD_READ_ARRAY_SLOW;
1239 else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
1240 flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
1241 else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
1242 flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
1244 /* Look for write commands */
1245 if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
1246 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
1248 /* Go for default supported write cmd */
1249 flash->write_cmd = CMD_PAGE_PROGRAM;
1251 /* Set the quad enable bit - only for quad commands */
1252 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
1253 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
1254 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
1255 ret = set_quad_mode(flash, info);
1257 debug("SF: Fail to set QEB for %02x\n",
1263 /* Read dummy_byte: dummy byte is determined based on the
1264 * dummy cycles of a particular command.
1265 * Fast commands - dummy_byte = dummy_cycles/8
1266 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
1267 * For I/O commands except cmd[0] everything goes on no.of lines
1268 * based on particular command but incase of fast commands except
1269 * data all go on single line irrespective of command.
1271 switch (flash->read_cmd) {
1272 case CMD_READ_QUAD_IO_FAST:
1273 flash->dummy_byte = 2;
1275 case CMD_READ_ARRAY_SLOW:
1276 flash->dummy_byte = 0;
1279 flash->dummy_byte = 1;
1282 #ifdef CONFIG_SPI_FLASH_STMICRO
1283 if (info->flags & E_FSR)
1284 flash->flags |= SNOR_F_USE_FSR;
1287 /* Configure the BAR - discover bank cmds and read current bank */
1288 #ifdef CONFIG_SPI_FLASH_BAR
1289 ret = read_bar(flash, info);
1294 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1295 ret = spi_flash_decode_fdt(flash);
1297 debug("SF: FDT decode error\n");
1302 #ifndef CONFIG_SPL_BUILD
1303 printf("SF: Detected %s with page size ", flash->name);
1304 print_size(flash->page_size, ", erase size ");
1305 print_size(flash->erase_size, ", total ");
1306 print_size(flash->size, "");
1307 if (flash->memory_map)
1308 printf(", mapped at %p", flash->memory_map);
1312 #ifndef CONFIG_SPI_FLASH_BAR
1313 if (((flash->dual_flash == SF_SINGLE_FLASH) &&
1314 (flash->size > SPI_FLASH_16MB_BOUN)) ||
1315 ((flash->dual_flash > SF_SINGLE_FLASH) &&
1316 (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
1317 puts("SF: Warning - Only lower 16MiB accessible,");
1318 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");