1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/log2.h>
16 #include <linux/math64.h>
17 #include <linux/sizes.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/spi-nor.h>
24 /* Define max times to check status register before we give up. */
27 * For everything but full-chip erase; probably could be much smaller, but kept
28 * around for safety for now
31 #define HZ CONFIG_SYS_HZ
33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
35 #define SPI_NOR_MAX_ID_LEN 6
36 #define SPI_NOR_MAX_ADDR_WIDTH 4
42 * This array stores the ID bytes.
43 * The first three bytes are the JEDIC ID.
44 * JEDEC ID zero means "no ID" (mostly older chips).
46 u8 id[SPI_NOR_MAX_ID_LEN];
49 /* The size listed here is what works with SPINOR_OP_SE, which isn't
50 * necessarily called a "sector" by the vendor.
52 unsigned int sector_size;
59 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
60 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
61 #define SST_WRITE BIT(2) /* use SST byte programming */
62 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
63 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
64 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
65 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
66 #define USE_FSR BIT(7) /* use flag status register */
67 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
68 #define SPI_NOR_HAS_TB BIT(9) /*
69 * Flash SR has Top/Bottom (TB) protect
70 * bit. Must be used with
73 #define SPI_S3AN BIT(10) /*
74 * Xilinx Spartan 3AN In-System Flash
75 * (MFR cannot be used for probing
76 * because it has the same value as
79 #define SPI_NOR_4B_OPCODES BIT(11) /*
80 * Use dedicated 4byte address op codes
81 * to support memory size above 128Mib.
83 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
84 #define USE_CLSR BIT(14) /* use CLSR command */
86 int (*quad_enable)(struct spi_nor *nor);
89 #define JEDEC_MFR(info) ((info)->id[0])
91 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
94 if (op->data.dir == SPI_MEM_DATA_IN)
95 op->data.buf.in = buf;
97 op->data.buf.out = buf;
98 return spi_mem_exec_op(nor->spi, op);
101 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
103 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
106 SPI_MEM_OP_DATA_IN(len, NULL, 1));
109 ret = spi_nor_read_write_reg(nor, &op, val);
111 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
117 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
119 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
122 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
124 return spi_nor_read_write_reg(nor, &op, buf);
127 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
130 struct spi_mem_op op =
131 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
132 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
133 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
134 SPI_MEM_OP_DATA_IN(len, buf, 1));
135 size_t remaining = len;
138 /* get transfer protocols. */
139 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
140 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
141 op.dummy.buswidth = op.addr.buswidth;
142 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
144 /* convert the dummy cycles to the number of bytes */
145 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
148 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
149 ret = spi_mem_adjust_op_size(nor->spi, &op);
153 ret = spi_mem_exec_op(nor->spi, &op);
157 op.addr.val += op.data.nbytes;
158 remaining -= op.data.nbytes;
159 op.data.buf.in += op.data.nbytes;
165 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
168 struct spi_mem_op op =
169 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
170 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
172 SPI_MEM_OP_DATA_OUT(len, buf, 1));
173 size_t remaining = len;
176 /* get transfer protocols. */
177 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
178 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
179 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
181 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
185 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
186 ret = spi_mem_adjust_op_size(nor->spi, &op);
190 ret = spi_mem_exec_op(nor->spi, &op);
194 op.addr.val += op.data.nbytes;
195 remaining -= op.data.nbytes;
196 op.data.buf.out += op.data.nbytes;
203 * Read the status register, returning its value in the location
204 * Return the status register value.
205 * Returns negative if error occurred.
207 static int read_sr(struct spi_nor *nor)
212 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
214 pr_debug("error %d reading SR\n", (int)ret);
222 * Read the flag status register, returning its value in the location
223 * Return the status register value.
224 * Returns negative if error occurred.
226 static int read_fsr(struct spi_nor *nor)
231 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
233 pr_debug("error %d reading FSR\n", ret);
241 * Read configuration register, returning its value in the
242 * location. Return the configuration register value.
243 * Returns negative if error occurred.
245 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
246 static int read_cr(struct spi_nor *nor)
251 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
253 dev_dbg(nor->dev, "error %d reading CR\n", ret);
262 * Write status register 1 byte
263 * Returns negative if error occurred.
265 static int write_sr(struct spi_nor *nor, u8 val)
267 nor->cmd_buf[0] = val;
268 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
272 * Set write enable latch with Write Enable command.
273 * Returns negative if error occurred.
275 static int write_enable(struct spi_nor *nor)
277 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
281 * Send write disable instruction to the chip.
283 static int write_disable(struct spi_nor *nor)
285 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
288 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
293 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
297 for (i = 0; i < size; i++)
298 if (table[i][0] == opcode)
301 /* No conversion found, keep input op code. */
305 static u8 spi_nor_convert_3to4_read(u8 opcode)
307 static const u8 spi_nor_3to4_read[][2] = {
308 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
309 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
310 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
311 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
312 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
313 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
315 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
316 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
317 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
320 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
321 ARRAY_SIZE(spi_nor_3to4_read));
324 static u8 spi_nor_convert_3to4_program(u8 opcode)
326 static const u8 spi_nor_3to4_program[][2] = {
327 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
328 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
329 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
332 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
333 ARRAY_SIZE(spi_nor_3to4_program));
336 static u8 spi_nor_convert_3to4_erase(u8 opcode)
338 static const u8 spi_nor_3to4_erase[][2] = {
339 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
340 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
341 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
344 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
345 ARRAY_SIZE(spi_nor_3to4_erase));
348 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
349 const struct flash_info *info)
351 /* Do some manufacturer fixups first */
352 switch (JEDEC_MFR(info)) {
353 case SNOR_MFR_SPANSION:
354 /* No small sector erase for 4-byte command set */
355 nor->erase_opcode = SPINOR_OP_SE;
356 nor->mtd.erasesize = info->sector_size;
363 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
364 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
365 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
368 /* Enable/disable 4-byte addressing mode. */
369 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
373 bool need_wren = false;
376 switch (JEDEC_MFR(info)) {
378 case SNOR_MFR_MICRON:
379 /* Some Micron need WREN command; all will accept it */
381 case SNOR_MFR_MACRONIX:
382 case SNOR_MFR_WINBOND:
386 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
387 status = nor->write_reg(nor, cmd, NULL, 0);
391 if (!status && !enable &&
392 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
394 * On Winbond W25Q256FV, leaving 4byte mode causes
395 * the Extended Address Register to be set to 1, so all
396 * 3-byte-address reads come from the second 16M.
397 * We must clear the register to enable normal behavior.
401 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
408 nor->cmd_buf[0] = enable << 7;
409 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
413 static int spi_nor_sr_ready(struct spi_nor *nor)
415 int sr = read_sr(nor);
420 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
422 dev_dbg(nor->dev, "Erase Error occurred\n");
424 dev_dbg(nor->dev, "Programming Error occurred\n");
426 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
430 return !(sr & SR_WIP);
433 static int spi_nor_fsr_ready(struct spi_nor *nor)
435 int fsr = read_fsr(nor);
440 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
442 dev_dbg(nor->dev, "Erase operation failed.\n");
444 dev_dbg(nor->dev, "Program operation failed.\n");
446 if (fsr & FSR_PT_ERR)
448 "Attempted to modify a protected sector.\n");
450 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
454 return fsr & FSR_READY;
457 static int spi_nor_ready(struct spi_nor *nor)
461 sr = spi_nor_sr_ready(nor);
464 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
471 * Service routine to read status register until ready, or timeout occurs.
472 * Returns non-zero if error.
474 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
475 unsigned long timeout)
477 unsigned long timebase;
480 timebase = get_timer(0);
482 while (get_timer(timebase) < timeout) {
483 ret = spi_nor_ready(nor);
490 dev_err(nor->dev, "flash operation timed out\n");
495 static int spi_nor_wait_till_ready(struct spi_nor *nor)
497 return spi_nor_wait_till_ready_with_timeout(nor,
498 DEFAULT_READY_WAIT_JIFFIES);
502 * Initiate the erasure of a single sector
504 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
506 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
510 return nor->erase(nor, addr);
513 * Default implementation, if driver doesn't have a specialized HW
516 for (i = nor->addr_width - 1; i >= 0; i--) {
517 buf[i] = addr & 0xff;
521 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
525 * Erase an address range on the nor chip. The address range may extend
526 * one or more erase sectors. Return an error is there is a problem erasing.
528 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
530 struct spi_nor *nor = mtd_to_spi_nor(mtd);
534 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
535 (long long)instr->len);
537 div_u64_rem(instr->len, mtd->erasesize, &rem);
547 ret = spi_nor_erase_sector(nor, addr);
551 addr += mtd->erasesize;
552 len -= mtd->erasesize;
554 ret = spi_nor_wait_till_ready(nor);
565 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
566 /* Write status register and ensure bits in mask match written values */
567 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
572 ret = write_sr(nor, status_new);
576 ret = spi_nor_wait_till_ready(nor);
584 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
587 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
590 struct mtd_info *mtd = &nor->mtd;
591 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
592 int shift = ffs(mask) - 1;
600 pow = ((sr & mask) ^ mask) >> shift;
601 *len = mtd->size >> pow;
602 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
605 *ofs = mtd->size - *len;
610 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
611 * @locked is false); 0 otherwise
613 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
622 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
625 /* Requested range is a sub-range of locked range */
626 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
628 /* Requested range does not overlap with locked range */
629 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
632 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
635 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
638 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
641 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
645 * Lock a region of the flash. Compatible with ST Micro and similar flash.
646 * Supports the block protection bits BP{0,1,2} in the status register
647 * (SR). Does not support these features found in newer SR bitfields:
648 * - SEC: sector/block protect - only handle SEC=0 (block protect)
649 * - CMP: complement protect - only support CMP=0 (range is not complemented)
651 * Support for the following is provided conditionally for some flash:
652 * - TB: top/bottom protect
654 * Sample table portion for 8MB flash (Winbond w25q64fw):
656 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
657 * --------------------------------------------------------------------------
658 * X | X | 0 | 0 | 0 | NONE | NONE
659 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
660 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
661 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
662 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
663 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
664 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
665 * X | X | 1 | 1 | 1 | 8 MB | ALL
666 * ------|-------|-------|-------|-------|---------------|-------------------
667 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
668 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
669 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
670 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
671 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
672 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
674 * Returns negative on errors, 0 on success.
676 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
678 struct mtd_info *mtd = &nor->mtd;
679 int status_old, status_new;
680 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
681 u8 shift = ffs(mask) - 1, pow, val;
683 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
686 status_old = read_sr(nor);
690 /* If nothing in our range is unlocked, we don't need to do anything */
691 if (stm_is_locked_sr(nor, ofs, len, status_old))
694 /* If anything below us is unlocked, we can't use 'bottom' protection */
695 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
696 can_be_bottom = false;
698 /* If anything above us is unlocked, we can't use 'top' protection */
699 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
703 if (!can_be_bottom && !can_be_top)
706 /* Prefer top, if both are valid */
707 use_top = can_be_top;
709 /* lock_len: length of region that should end up locked */
711 lock_len = mtd->size - ofs;
713 lock_len = ofs + len;
716 * Need smallest pow such that:
718 * 1 / (2^pow) <= (len / size)
720 * so (assuming power-of-2 size) we do:
722 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
724 pow = ilog2(mtd->size) - ilog2(lock_len);
725 val = mask - (pow << shift);
728 /* Don't "lock" with no region! */
732 status_new = (status_old & ~mask & ~SR_TB) | val;
734 /* Disallow further writes if WP pin is asserted */
735 status_new |= SR_SRWD;
740 /* Don't bother if they're the same */
741 if (status_new == status_old)
744 /* Only modify protection if it will not unlock other areas */
745 if ((status_new & mask) < (status_old & mask))
748 return write_sr_and_check(nor, status_new, mask);
752 * Unlock a region of the flash. See stm_lock() for more info
754 * Returns negative on errors, 0 on success.
756 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
758 struct mtd_info *mtd = &nor->mtd;
759 int status_old, status_new;
760 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
761 u8 shift = ffs(mask) - 1, pow, val;
763 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
766 status_old = read_sr(nor);
770 /* If nothing in our range is locked, we don't need to do anything */
771 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
774 /* If anything below us is locked, we can't use 'top' protection */
775 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
778 /* If anything above us is locked, we can't use 'bottom' protection */
779 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
781 can_be_bottom = false;
783 if (!can_be_bottom && !can_be_top)
786 /* Prefer top, if both are valid */
787 use_top = can_be_top;
789 /* lock_len: length of region that should remain locked */
791 lock_len = mtd->size - (ofs + len);
796 * Need largest pow such that:
798 * 1 / (2^pow) >= (len / size)
800 * so (assuming power-of-2 size) we do:
802 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
804 pow = ilog2(mtd->size) - order_base_2(lock_len);
806 val = 0; /* fully unlocked */
808 val = mask - (pow << shift);
809 /* Some power-of-two sizes are not supported */
814 status_new = (status_old & ~mask & ~SR_TB) | val;
816 /* Don't protect status register if we're fully unlocked */
818 status_new &= ~SR_SRWD;
823 /* Don't bother if they're the same */
824 if (status_new == status_old)
827 /* Only modify protection if it will not lock other areas */
828 if ((status_new & mask) > (status_old & mask))
831 return write_sr_and_check(nor, status_new, mask);
835 * Check if a region of the flash is (completely) locked. See stm_lock() for
838 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
839 * negative on errors.
841 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
845 status = read_sr(nor);
849 return stm_is_locked_sr(nor, ofs, len, status);
851 #endif /* CONFIG_SPI_FLASH_STMICRO */
853 /* Used when the "_ext_id" is two bytes at most */
854 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
856 ((_jedec_id) >> 16) & 0xff, \
857 ((_jedec_id) >> 8) & 0xff, \
858 (_jedec_id) & 0xff, \
859 ((_ext_id) >> 8) & 0xff, \
862 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
863 .sector_size = (_sector_size), \
864 .n_sectors = (_n_sectors), \
868 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
870 ((_jedec_id) >> 16) & 0xff, \
871 ((_jedec_id) >> 8) & 0xff, \
872 (_jedec_id) & 0xff, \
873 ((_ext_id) >> 16) & 0xff, \
874 ((_ext_id) >> 8) & 0xff, \
878 .sector_size = (_sector_size), \
879 .n_sectors = (_n_sectors), \
883 /* NOTE: double check command sets and memory organization when you add
884 * more nor chips. This current list focusses on newer chips, which
885 * have been converging on command sets which including JEDEC ID.
887 * All newly added entries should describe *hardware* and should use SECT_4K
888 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
889 * scenarios excluding small sectors there is config option that can be
890 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
891 * For historical (and compatibility) reasons (before we got above config) some
892 * old entries may be missing 4K flag.
894 const struct flash_info spi_nor_ids[] = {
895 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
896 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
897 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
898 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
900 { "at45db011d", INFO(0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
901 { "at45db021d", INFO(0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
902 { "at45db041d", INFO(0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
903 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
904 { "at45db161d", INFO(0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
905 { "at45db321d", INFO(0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
906 { "at45db641d", INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
907 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
909 #ifdef CONFIG_SPI_FLASH_EON /* EON */
911 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
912 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
913 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
914 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
916 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
919 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
920 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
921 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
924 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
925 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
926 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
929 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
930 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
931 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
934 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
935 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
936 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
939 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
941 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
942 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
943 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 0) },
944 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 0) },
945 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
946 SECT_4K | SPI_NOR_DUAL_READ) },
947 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
948 SECT_4K | SPI_NOR_DUAL_READ) },
949 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
950 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
951 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
952 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
953 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
954 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
956 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
958 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
959 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
960 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
961 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
962 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
963 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
964 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
965 { "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32, SECT_4K) },
966 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
967 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
968 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
969 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
970 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
971 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
972 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
973 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
974 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
975 { "mx25l1633e", INFO(0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
978 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
980 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
981 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
982 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
983 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
984 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
985 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
986 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
987 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
988 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
989 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
990 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
991 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
992 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
993 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
995 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
996 /* Spansion/Cypress -- single (large) sector size only, at least
997 * for the chips listed here (without boot sectors).
999 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1000 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1001 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
1002 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1003 { "s25fl512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1004 { "s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1005 { "s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1006 { "s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1007 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1008 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1009 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1010 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1011 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1012 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1013 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
1014 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
1015 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
1016 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1017 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
1018 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
1019 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1021 #ifdef CONFIG_SPI_FLASH_SST /* SST */
1022 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1023 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1024 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1025 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
1026 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
1027 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
1028 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
1029 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
1030 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
1031 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
1032 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
1033 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1034 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1035 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1036 { "sst26wf016", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K) },
1037 { "sst26wf032", INFO(0xbf2622, 0, 64 * 1024, 64, SECT_4K) },
1038 { "sst26wf064", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) },
1040 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
1041 /* ST Microelectronics -- newer production may have feature updates */
1042 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1043 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1044 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1045 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1046 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1047 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1048 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1049 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1050 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1051 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1052 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1054 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
1055 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1056 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
1057 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1058 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1059 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1060 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1061 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1063 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
1064 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1065 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1067 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1068 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
1069 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
1070 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
1071 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1073 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
1074 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1075 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1078 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
1079 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1080 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1082 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1083 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1085 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1086 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1087 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1090 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1091 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1092 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1094 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1095 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1096 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1097 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1098 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
1099 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
1101 #ifdef CONFIG_SPI_FLASH_XMC
1102 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
1103 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1104 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1109 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1112 u8 id[SPI_NOR_MAX_ID_LEN];
1113 const struct flash_info *info;
1115 if (!ARRAY_SIZE(spi_nor_ids))
1116 return ERR_PTR(-ENODEV);
1118 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1120 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1121 return ERR_PTR(tmp);
1124 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1125 info = &spi_nor_ids[tmp];
1127 if (!memcmp(info->id, id, info->id_len))
1128 return &spi_nor_ids[tmp];
1131 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1132 id[0], id[1], id[2]);
1133 return ERR_PTR(-ENODEV);
1136 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1137 size_t *retlen, u_char *buf)
1139 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1142 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1147 ret = nor->read(nor, addr, len, buf);
1149 /* We shouldn't see 0-length reads */
1167 #ifdef CONFIG_SPI_FLASH_SST
1168 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1169 size_t *retlen, const u_char *buf)
1171 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1175 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1179 nor->sst_write_second = false;
1182 /* Start write from odd address. */
1184 nor->program_opcode = SPINOR_OP_BP;
1186 /* write one byte. */
1187 ret = nor->write(nor, to, 1, buf);
1190 ret = spi_nor_wait_till_ready(nor);
1196 /* Write out most of the data here. */
1197 for (; actual < len - 1; actual += 2) {
1198 nor->program_opcode = SPINOR_OP_AAI_WP;
1200 /* write two bytes. */
1201 ret = nor->write(nor, to, 2, buf + actual);
1204 ret = spi_nor_wait_till_ready(nor);
1208 nor->sst_write_second = true;
1210 nor->sst_write_second = false;
1213 ret = spi_nor_wait_till_ready(nor);
1217 /* Write out trailing byte if it exists. */
1218 if (actual != len) {
1221 nor->program_opcode = SPINOR_OP_BP;
1222 ret = nor->write(nor, to, 1, buf + actual);
1225 ret = spi_nor_wait_till_ready(nor);
1237 * Write an address range to the nor chip. Data must be written in
1238 * FLASH_PAGESIZE chunks. The address range may be any size provided
1239 * it is within the physical boundaries.
1241 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1242 size_t *retlen, const u_char *buf)
1244 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1245 size_t page_offset, page_remain, i;
1248 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1250 for (i = 0; i < len; ) {
1252 loff_t addr = to + i;
1255 * If page_size is a power of two, the offset can be quickly
1256 * calculated with an AND operation. On the other cases we
1257 * need to do a modulus operation (more expensive).
1258 * Power of two numbers have only one bit set and we can use
1259 * the instruction hweight32 to detect if we need to do a
1260 * modulus (do_div()) or not.
1262 if (hweight32(nor->page_size) == 1) {
1263 page_offset = addr & (nor->page_size - 1);
1267 page_offset = do_div(aux, nor->page_size);
1269 /* the size of data remaining on the first page */
1270 page_remain = min_t(size_t,
1271 nor->page_size - page_offset, len - i);
1274 ret = nor->write(nor, addr, page_remain, buf + i);
1279 ret = spi_nor_wait_till_ready(nor);
1284 if (written != page_remain) {
1294 #ifdef CONFIG_SPI_FLASH_MACRONIX
1296 * macronix_quad_enable() - set QE bit in Status Register.
1297 * @nor: pointer to a 'struct spi_nor'
1299 * Set the Quad Enable (QE) bit in the Status Register.
1301 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1303 * Return: 0 on success, -errno otherwise.
1305 static int macronix_quad_enable(struct spi_nor *nor)
1312 if (val & SR_QUAD_EN_MX)
1317 write_sr(nor, val | SR_QUAD_EN_MX);
1319 ret = spi_nor_wait_till_ready(nor);
1324 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1325 dev_err(nor->dev, "Macronix Quad bit not set\n");
1333 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1335 * Write status Register and configuration register with 2 bytes
1336 * The first byte will be written to the status register, while the
1337 * second byte will be written to the configuration register.
1338 * Return negative if error occurred.
1340 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1346 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1349 "error while writing configuration register\n");
1353 ret = spi_nor_wait_till_ready(nor);
1356 "timeout while writing configuration register\n");
1364 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1365 * @nor: pointer to a 'struct spi_nor'
1367 * Set the Quad Enable (QE) bit in the Configuration Register.
1368 * This function should be used with QSPI memories supporting the Read
1369 * Configuration Register (35h) instruction.
1371 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1374 * Return: 0 on success, -errno otherwise.
1376 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1381 /* Check current Quad Enable bit value. */
1384 dev_dbg(dev, "error while reading configuration register\n");
1388 if (ret & CR_QUAD_EN_SPAN)
1391 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1393 /* Keep the current value of the Status Register. */
1396 dev_dbg(dev, "error while reading status register\n");
1401 ret = write_sr_cr(nor, sr_cr);
1405 /* Read back and check it. */
1407 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1408 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1414 #endif /* CONFIG_SPI_FLASH_SPANSION */
1416 struct spi_nor_read_command {
1420 enum spi_nor_protocol proto;
1423 struct spi_nor_pp_command {
1425 enum spi_nor_protocol proto;
1428 enum spi_nor_read_command_index {
1431 SNOR_CMD_READ_1_1_1_DTR,
1434 SNOR_CMD_READ_1_1_2,
1435 SNOR_CMD_READ_1_2_2,
1436 SNOR_CMD_READ_2_2_2,
1437 SNOR_CMD_READ_1_2_2_DTR,
1440 SNOR_CMD_READ_1_1_4,
1441 SNOR_CMD_READ_1_4_4,
1442 SNOR_CMD_READ_4_4_4,
1443 SNOR_CMD_READ_1_4_4_DTR,
1446 SNOR_CMD_READ_1_1_8,
1447 SNOR_CMD_READ_1_8_8,
1448 SNOR_CMD_READ_8_8_8,
1449 SNOR_CMD_READ_1_8_8_DTR,
1454 enum spi_nor_pp_command_index {
1470 struct spi_nor_flash_parameter {
1474 struct spi_nor_hwcaps hwcaps;
1475 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1476 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1478 int (*quad_enable)(struct spi_nor *nor);
1482 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1486 enum spi_nor_protocol proto)
1488 read->num_mode_clocks = num_mode_clocks;
1489 read->num_wait_states = num_wait_states;
1490 read->opcode = opcode;
1491 read->proto = proto;
1495 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1497 enum spi_nor_protocol proto)
1499 pp->opcode = opcode;
1503 static int spi_nor_init_params(struct spi_nor *nor,
1504 const struct flash_info *info,
1505 struct spi_nor_flash_parameter *params)
1507 /* Set legacy flash parameters as default. */
1508 memset(params, 0, sizeof(*params));
1510 /* Set SPI NOR sizes. */
1511 params->size = info->sector_size * info->n_sectors;
1512 params->page_size = info->page_size;
1514 /* (Fast) Read settings. */
1515 params->hwcaps.mask |= SNOR_HWCAPS_READ;
1516 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
1517 0, 0, SPINOR_OP_READ,
1520 if (!(info->flags & SPI_NOR_NO_FR)) {
1521 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
1522 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
1523 0, 8, SPINOR_OP_READ_FAST,
1527 if (info->flags & SPI_NOR_DUAL_READ) {
1528 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
1529 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
1530 0, 8, SPINOR_OP_READ_1_1_2,
1534 if (info->flags & SPI_NOR_QUAD_READ) {
1535 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
1536 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
1537 0, 8, SPINOR_OP_READ_1_1_4,
1541 /* Page Program settings. */
1542 params->hwcaps.mask |= SNOR_HWCAPS_PP;
1543 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
1544 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
1546 if (info->flags & SPI_NOR_QUAD_READ) {
1547 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
1548 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
1549 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
1552 /* Select the procedure to set the Quad Enable bit. */
1553 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
1554 SNOR_HWCAPS_PP_QUAD)) {
1555 switch (JEDEC_MFR(info)) {
1556 #ifdef CONFIG_SPI_FLASH_MACRONIX
1557 case SNOR_MFR_MACRONIX:
1558 params->quad_enable = macronix_quad_enable;
1562 case SNOR_MFR_MICRON:
1566 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1567 /* Kept only for backward compatibility purpose. */
1568 params->quad_enable = spansion_read_cr_quad_enable;
1575 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
1579 for (i = 0; i < size; i++)
1580 if (table[i][0] == (int)hwcaps)
1586 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
1588 static const int hwcaps_read2cmd[][2] = {
1589 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
1590 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
1591 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
1592 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
1593 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
1594 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
1595 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
1596 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
1597 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
1598 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
1599 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
1600 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
1601 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
1602 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
1603 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
1606 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
1607 ARRAY_SIZE(hwcaps_read2cmd));
1610 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
1612 static const int hwcaps_pp2cmd[][2] = {
1613 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
1614 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
1615 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
1616 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
1617 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
1618 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
1619 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
1622 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
1623 ARRAY_SIZE(hwcaps_pp2cmd));
1626 static int spi_nor_select_read(struct spi_nor *nor,
1627 const struct spi_nor_flash_parameter *params,
1630 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
1631 const struct spi_nor_read_command *read;
1636 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
1640 read = ¶ms->reads[cmd];
1641 nor->read_opcode = read->opcode;
1642 nor->read_proto = read->proto;
1645 * In the spi-nor framework, we don't need to make the difference
1646 * between mode clock cycles and wait state clock cycles.
1647 * Indeed, the value of the mode clock cycles is used by a QSPI
1648 * flash memory to know whether it should enter or leave its 0-4-4
1649 * (Continuous Read / XIP) mode.
1650 * eXecution In Place is out of the scope of the mtd sub-system.
1651 * Hence we choose to merge both mode and wait state clock cycles
1652 * into the so called dummy clock cycles.
1654 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
1658 static int spi_nor_select_pp(struct spi_nor *nor,
1659 const struct spi_nor_flash_parameter *params,
1662 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
1663 const struct spi_nor_pp_command *pp;
1668 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
1672 pp = ¶ms->page_programs[cmd];
1673 nor->program_opcode = pp->opcode;
1674 nor->write_proto = pp->proto;
1678 static int spi_nor_select_erase(struct spi_nor *nor,
1679 const struct flash_info *info)
1681 struct mtd_info *mtd = &nor->mtd;
1683 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1684 /* prefer "small sector" erase if possible */
1685 if (info->flags & SECT_4K) {
1686 nor->erase_opcode = SPINOR_OP_BE_4K;
1687 mtd->erasesize = 4096;
1688 } else if (info->flags & SECT_4K_PMC) {
1689 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1690 mtd->erasesize = 4096;
1694 nor->erase_opcode = SPINOR_OP_SE;
1695 mtd->erasesize = info->sector_size;
1700 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
1701 const struct spi_nor_flash_parameter *params,
1702 const struct spi_nor_hwcaps *hwcaps)
1704 u32 ignored_mask, shared_mask;
1705 bool enable_quad_io;
1709 * Keep only the hardware capabilities supported by both the SPI
1710 * controller and the SPI flash memory.
1712 shared_mask = hwcaps->mask & params->hwcaps.mask;
1714 /* SPI n-n-n protocols are not supported yet. */
1715 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
1716 SNOR_HWCAPS_READ_4_4_4 |
1717 SNOR_HWCAPS_READ_8_8_8 |
1718 SNOR_HWCAPS_PP_4_4_4 |
1719 SNOR_HWCAPS_PP_8_8_8);
1720 if (shared_mask & ignored_mask) {
1722 "SPI n-n-n protocols are not supported yet.\n");
1723 shared_mask &= ~ignored_mask;
1726 /* Select the (Fast) Read command. */
1727 err = spi_nor_select_read(nor, params, shared_mask);
1730 "can't select read settings supported by both the SPI controller and memory.\n");
1734 /* Select the Page Program command. */
1735 err = spi_nor_select_pp(nor, params, shared_mask);
1738 "can't select write settings supported by both the SPI controller and memory.\n");
1742 /* Select the Sector Erase command. */
1743 err = spi_nor_select_erase(nor, info);
1746 "can't select erase settings supported by both the SPI controller and memory.\n");
1750 /* Enable Quad I/O if needed. */
1751 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
1752 spi_nor_get_protocol_width(nor->write_proto) == 4);
1753 if (enable_quad_io && params->quad_enable)
1754 nor->quad_enable = params->quad_enable;
1756 nor->quad_enable = NULL;
1761 static int spi_nor_init(struct spi_nor *nor)
1766 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1767 * with the software protection bits set
1769 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
1770 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
1771 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
1772 nor->info->flags & SPI_NOR_HAS_LOCK) {
1775 spi_nor_wait_till_ready(nor);
1778 if (nor->quad_enable) {
1779 err = nor->quad_enable(nor);
1781 dev_dbg(nor->dev, "quad mode not supported\n");
1786 if (nor->addr_width == 4 &&
1787 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
1788 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
1790 * If the RESET# pin isn't hooked up properly, or the system
1791 * otherwise doesn't perform a reset command in the boot
1792 * sequence, it's impossible to 100% protect against unexpected
1793 * reboots (e.g., crashes). Warn the user (or hopefully, system
1794 * designer) that this is bad.
1796 if (nor->flags & SNOR_F_BROKEN_RESET)
1797 printf("enabling reset hack; may not recover from unexpected reboots\n");
1798 set_4byte(nor, nor->info, 1);
1804 int spi_nor_scan(struct spi_nor *nor)
1806 struct spi_nor_flash_parameter params;
1807 const struct flash_info *info = NULL;
1808 struct mtd_info *mtd = &nor->mtd;
1809 struct spi_nor_hwcaps hwcaps = {
1810 .mask = SNOR_HWCAPS_READ |
1811 SNOR_HWCAPS_READ_FAST |
1814 struct spi_slave *spi = nor->spi;
1817 /* Reset SPI protocol for all commands. */
1818 nor->reg_proto = SNOR_PROTO_1_1_1;
1819 nor->read_proto = SNOR_PROTO_1_1_1;
1820 nor->write_proto = SNOR_PROTO_1_1_1;
1821 nor->read = spi_nor_read_data;
1822 nor->write = spi_nor_write_data;
1823 nor->read_reg = spi_nor_read_reg;
1824 nor->write_reg = spi_nor_write_reg;
1826 if (spi->mode & SPI_RX_QUAD) {
1827 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
1829 if (spi->mode & SPI_TX_QUAD)
1830 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
1831 SNOR_HWCAPS_PP_1_1_4 |
1832 SNOR_HWCAPS_PP_1_4_4);
1833 } else if (spi->mode & SPI_RX_DUAL) {
1834 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
1836 if (spi->mode & SPI_TX_DUAL)
1837 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
1840 info = spi_nor_read_id(nor);
1841 if (IS_ERR_OR_NULL(info))
1844 ret = spi_nor_init_params(nor, info, ¶ms);
1849 mtd->name = info->name;
1851 mtd->type = MTD_NORFLASH;
1853 mtd->flags = MTD_CAP_NORFLASH;
1854 mtd->size = params.size;
1855 mtd->_erase = spi_nor_erase;
1856 mtd->_read = spi_nor_read;
1858 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
1859 /* NOR protection support for STmicro/Micron chips and similar */
1860 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
1861 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1862 JEDEC_MFR(info) == SNOR_MFR_SST ||
1863 info->flags & SPI_NOR_HAS_LOCK) {
1864 nor->flash_lock = stm_lock;
1865 nor->flash_unlock = stm_unlock;
1866 nor->flash_is_locked = stm_is_locked;
1870 #ifdef CONFIG_SPI_FLASH_SST
1871 /* sst nor chips use AAI word program */
1872 if (info->flags & SST_WRITE)
1873 mtd->_write = sst_write;
1876 mtd->_write = spi_nor_write;
1878 if (info->flags & USE_FSR)
1879 nor->flags |= SNOR_F_USE_FSR;
1880 if (info->flags & SPI_NOR_HAS_TB)
1881 nor->flags |= SNOR_F_HAS_SR_TB;
1882 if (info->flags & NO_CHIP_ERASE)
1883 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
1884 if (info->flags & USE_CLSR)
1885 nor->flags |= SNOR_F_USE_CLSR;
1887 if (info->flags & SPI_NOR_NO_ERASE)
1888 mtd->flags |= MTD_NO_ERASE;
1890 nor->page_size = params.page_size;
1891 mtd->writebufsize = nor->page_size;
1893 /* Some devices cannot do fast-read, no matter what DT tells us */
1894 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
1895 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
1898 * Configure the SPI memory:
1899 * - select op codes for (Fast) Read, Page Program and Sector Erase.
1900 * - set the number of dummy cycles (mode cycles + wait states).
1901 * - set the SPI protocols for register and memory accesses.
1902 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
1904 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
1908 if (info->addr_width) {
1909 nor->addr_width = info->addr_width;
1910 } else if (mtd->size > 0x1000000) {
1911 /* enable 4-byte addressing if the device exceeds 16MiB */
1912 nor->addr_width = 4;
1913 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
1914 info->flags & SPI_NOR_4B_OPCODES)
1915 spi_nor_set_4byte_opcodes(nor, info);
1917 nor->addr_width = 3;
1920 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
1921 dev_dbg(dev, "address width is too large: %u\n",
1926 /* Send all the required SPI flash commands to initialize device */
1928 ret = spi_nor_init(nor);
1932 nor->name = mtd->name;
1933 nor->size = mtd->size;
1934 nor->erase_size = mtd->erasesize;
1935 nor->sector_size = mtd->erasesize;
1937 #ifndef CONFIG_SPL_BUILD
1938 printf("SF: Detected %s with page size ", nor->name);
1939 print_size(nor->page_size, ", erase size ");
1940 print_size(nor->erase_size, ", total ");
1941 print_size(nor->size, "");