1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
17 #include <dm/device_compat.h>
18 #include <dm/devres.h>
19 #include <linux/bitops.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/log2.h>
23 #include <linux/math64.h>
24 #include <linux/sizes.h>
25 #include <linux/bitfield.h>
26 #include <linux/delay.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/spi-nor.h>
30 #include <mtd/cfi_flash.h>
34 #include "sf_internal.h"
36 /* Define max times to check status register before we give up. */
39 * For everything but full-chip erase; probably could be much smaller, but kept
40 * around for safety for now
43 #define HZ CONFIG_SYS_HZ
45 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
47 #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
49 struct sfdp_parameter_header {
53 u8 length; /* in double words */
54 u8 parameter_table_pointer[3]; /* byte address */
58 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
59 #define SFDP_PARAM_HEADER_PTP(p) \
60 (((p)->parameter_table_pointer[2] << 16) | \
61 ((p)->parameter_table_pointer[1] << 8) | \
62 ((p)->parameter_table_pointer[0] << 0))
64 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
65 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
66 #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
67 #define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */
69 #define SFDP_SIGNATURE 0x50444653U
70 #define SFDP_JESD216_MAJOR 1
71 #define SFDP_JESD216_MINOR 0
72 #define SFDP_JESD216A_MINOR 5
73 #define SFDP_JESD216B_MINOR 6
76 u32 signature; /* Ox50444653U <=> "SFDP" */
79 u8 nph; /* 0-base number of parameter headers */
82 /* Basic Flash Parameter Table. */
83 struct sfdp_parameter_header bfpt_header;
86 /* Basic Flash Parameter Table */
89 * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs.
90 * They are indexed from 1 but C arrays are indexed from 0.
92 #define BFPT_DWORD(i) ((i) - 1)
93 #define BFPT_DWORD_MAX 20
95 /* The first version of JESB216 defined only 9 DWORDs. */
96 #define BFPT_DWORD_MAX_JESD216 9
97 #define BFPT_DWORD_MAX_JESD216B 16
100 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
101 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
102 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
103 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
104 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
105 #define BFPT_DWORD1_DTR BIT(19)
106 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
107 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
108 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
111 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
112 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
115 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
116 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
121 * (from JESD216 rev B)
122 * Quad Enable Requirements (QER):
123 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
124 * reads based on instruction. DQ3/HOLD# functions are hold during
126 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
127 * two data bytes where bit 1 of the second byte is one.
129 * Writing only one byte to the status register has the side-effect of
130 * clearing status register 2, including the QE bit. The 100b code is
131 * used if writing one byte to the status register does not modify
133 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
134 * one data byte where bit 6 is one.
136 * - 011b: QE is bit 7 of status register 2. It is set via Write status
137 * register 2 instruction 3Eh with one data byte where bit 7 is one.
139 * The status register 2 is read using instruction 3Fh.
140 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
141 * two data bytes where bit 1 of the second byte is one.
143 * In contrast to the 001b code, writing one byte to the status
144 * register does not modify status register 2.
145 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
146 * Read Status instruction 05h. Status register2 is read using
147 * instruction 35h. QE is set via Writ Status instruction 01h with
148 * two data bytes where bit 1 of the second byte is one.
151 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
152 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
153 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
154 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
155 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
156 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
157 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
159 #define BFPT_DWORD16_SOFT_RST BIT(12)
161 #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29)
162 #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */
163 #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */
164 #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */
165 #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
167 /* xSPI Profile 1.0 table (from JESD216D.01). */
168 #define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8)
169 #define PROFILE1_DWORD1_RDSR_DUMMY BIT(28)
170 #define PROFILE1_DWORD1_RDSR_ADDR_BYTES BIT(29)
171 #define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7)
172 #define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27)
173 #define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17)
174 #define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)
175 #define PROFILE1_DUMMY_DEFAULT 20
178 u32 dwords[BFPT_DWORD_MAX];
182 * struct spi_nor_fixups - SPI NOR fixup hooks
183 * @default_init: called after default flash parameters init. Used to tweak
184 * flash parameters when information provided by the flash_info
185 * table is incomplete or wrong.
186 * @post_bfpt: called after the BFPT table has been parsed
187 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
188 * that do not support RDSFDP). Typically used to tweak various
189 * parameters that could not be extracted by other means (i.e.
190 * when information provided by the SFDP/flash_info tables are
191 * incomplete or wrong).
193 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
194 * table is broken or not available.
196 struct spi_nor_fixups {
197 void (*default_init)(struct spi_nor *nor);
198 int (*post_bfpt)(struct spi_nor *nor,
199 const struct sfdp_parameter_header *bfpt_header,
200 const struct sfdp_bfpt *bfpt,
201 struct spi_nor_flash_parameter *params);
202 void (*post_sfdp)(struct spi_nor *nor,
203 struct spi_nor_flash_parameter *params);
206 #define SPI_NOR_SRST_SLEEP_LEN 200
209 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
211 * @nor: pointer to a 'struct spi_nor'
212 * @op: pointer to the 'struct spi_mem_op' whose properties
213 * need to be initialized.
215 * Right now, only "repeat" and "invert" are supported.
217 * Return: The opcode extension.
219 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
220 const struct spi_mem_op *op)
222 switch (nor->cmd_ext_type) {
223 case SPI_NOR_EXT_INVERT:
224 return ~op->cmd.opcode;
226 case SPI_NOR_EXT_REPEAT:
227 return op->cmd.opcode;
230 dev_dbg(nor->dev, "Unknown command extension type\n");
236 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
237 * @nor: pointer to a 'struct spi_nor'
238 * @op: pointer to the 'struct spi_mem_op' whose properties
239 * need to be initialized.
240 * @proto: the protocol from which the properties need to be set.
242 static void spi_nor_setup_op(const struct spi_nor *nor,
243 struct spi_mem_op *op,
244 const enum spi_nor_protocol proto)
248 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
251 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
253 if (op->dummy.nbytes)
254 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
257 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
259 if (spi_nor_protocol_is_dtr(proto)) {
261 * spi-mem supports mixed DTR modes, but right now we can only
262 * have all phases either DTR or STR. IOW, spi-mem can have
263 * something like 4S-4D-4D, but spi-nor can't. So, set all 4
264 * phases to either DTR or STR.
266 op->cmd.dtr = op->addr.dtr = op->dummy.dtr =
269 /* 2 bytes per clock cycle in DTR mode. */
270 op->dummy.nbytes *= 2;
272 ext = spi_nor_get_cmd_ext(nor, op);
273 op->cmd.opcode = (op->cmd.opcode << 8) | ext;
278 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
281 if (op->data.dir == SPI_MEM_DATA_IN)
282 op->data.buf.in = buf;
284 op->data.buf.out = buf;
285 return spi_mem_exec_op(nor->spi, op);
288 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
290 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 0),
293 SPI_MEM_OP_DATA_IN(len, NULL, 0));
296 spi_nor_setup_op(nor, &op, nor->reg_proto);
298 ret = spi_nor_read_write_reg(nor, &op, val);
300 dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
305 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
307 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),
310 SPI_MEM_OP_DATA_OUT(len, NULL, 0));
312 spi_nor_setup_op(nor, &op, nor->reg_proto);
315 op.data.dir = SPI_MEM_NO_DATA;
317 return spi_nor_read_write_reg(nor, &op, buf);
320 #ifdef CONFIG_SPI_FLASH_SPANSION
321 static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy,
324 struct spi_mem_op op =
325 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1),
326 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
327 SPI_MEM_OP_DUMMY(dummy / 8, 1),
328 SPI_MEM_OP_DATA_IN(1, NULL, 1));
330 return spi_nor_read_write_reg(nor, &op, val);
333 static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val)
335 struct spi_mem_op op =
336 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1),
337 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
339 SPI_MEM_OP_DATA_OUT(1, NULL, 1));
341 return spi_nor_read_write_reg(nor, &op, &val);
345 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
348 struct spi_mem_op op =
349 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
350 SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
351 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
352 SPI_MEM_OP_DATA_IN(len, buf, 0));
353 size_t remaining = len;
356 spi_nor_setup_op(nor, &op, nor->read_proto);
358 /* convert the dummy cycles to the number of bytes */
359 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
360 if (spi_nor_protocol_is_dtr(nor->read_proto))
361 op.dummy.nbytes *= 2;
364 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
365 ret = spi_mem_adjust_op_size(nor->spi, &op);
369 ret = spi_mem_exec_op(nor->spi, &op);
373 op.addr.val += op.data.nbytes;
374 remaining -= op.data.nbytes;
375 op.data.buf.in += op.data.nbytes;
381 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
384 struct spi_mem_op op =
385 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
386 SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
388 SPI_MEM_OP_DATA_OUT(len, buf, 0));
391 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
394 spi_nor_setup_op(nor, &op, nor->write_proto);
396 ret = spi_mem_adjust_op_size(nor->spi, &op);
399 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
401 ret = spi_mem_exec_op(nor->spi, &op);
405 return op.data.nbytes;
409 * Read the status register, returning its value in the location
410 * Return the status register value.
411 * Returns negative if error occurred.
413 static int read_sr(struct spi_nor *nor)
415 struct spi_mem_op op;
418 u8 addr_nbytes, dummy;
420 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
421 addr_nbytes = nor->rdsr_addr_nbytes;
422 dummy = nor->rdsr_dummy;
428 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0),
429 SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
430 SPI_MEM_OP_DUMMY(dummy, 0),
431 SPI_MEM_OP_DATA_IN(1, NULL, 0));
433 spi_nor_setup_op(nor, &op, nor->reg_proto);
436 * We don't want to read only one byte in DTR mode. So, read 2 and then
437 * discard the second byte.
439 if (spi_nor_protocol_is_dtr(nor->reg_proto))
442 ret = spi_nor_read_write_reg(nor, &op, val);
444 pr_debug("error %d reading SR\n", (int)ret);
452 * Read the flag status register, returning its value in the location
453 * Return the status register value.
454 * Returns negative if error occurred.
456 static int read_fsr(struct spi_nor *nor)
458 struct spi_mem_op op;
461 u8 addr_nbytes, dummy;
463 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
464 addr_nbytes = nor->rdsr_addr_nbytes;
465 dummy = nor->rdsr_dummy;
471 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
472 SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
473 SPI_MEM_OP_DUMMY(dummy, 0),
474 SPI_MEM_OP_DATA_IN(1, NULL, 0));
476 spi_nor_setup_op(nor, &op, nor->reg_proto);
479 * We don't want to read only one byte in DTR mode. So, read 2 and then
480 * discard the second byte.
482 if (spi_nor_protocol_is_dtr(nor->reg_proto))
485 ret = spi_nor_read_write_reg(nor, &op, val);
487 pr_debug("error %d reading FSR\n", ret);
495 * Read configuration register, returning its value in the
496 * location. Return the configuration register value.
497 * Returns negative if error occurred.
499 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
500 static int read_cr(struct spi_nor *nor)
505 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
507 dev_dbg(nor->dev, "error %d reading CR\n", ret);
516 * Write status register 1 byte
517 * Returns negative if error occurred.
519 static int write_sr(struct spi_nor *nor, u8 val)
521 nor->cmd_buf[0] = val;
522 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
526 * Set write enable latch with Write Enable command.
527 * Returns negative if error occurred.
529 static int write_enable(struct spi_nor *nor)
531 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
535 * Send write disable instruction to the chip.
537 static int write_disable(struct spi_nor *nor)
539 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
542 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
547 #ifndef CONFIG_SPI_FLASH_BAR
548 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
552 for (i = 0; i < size; i++)
553 if (table[i][0] == opcode)
556 /* No conversion found, keep input op code. */
560 static u8 spi_nor_convert_3to4_read(u8 opcode)
562 static const u8 spi_nor_3to4_read[][2] = {
563 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
564 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
565 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
566 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
567 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
568 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
569 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
570 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
572 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
573 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
574 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
577 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
578 ARRAY_SIZE(spi_nor_3to4_read));
581 static u8 spi_nor_convert_3to4_program(u8 opcode)
583 static const u8 spi_nor_3to4_program[][2] = {
584 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
585 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
586 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
587 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
588 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
591 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
592 ARRAY_SIZE(spi_nor_3to4_program));
595 static u8 spi_nor_convert_3to4_erase(u8 opcode)
597 static const u8 spi_nor_3to4_erase[][2] = {
598 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
599 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
600 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
603 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
604 ARRAY_SIZE(spi_nor_3to4_erase));
607 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
608 const struct flash_info *info)
610 /* Do some manufacturer fixups first */
611 switch (JEDEC_MFR(info)) {
612 case SNOR_MFR_SPANSION:
613 /* No small sector erase for 4-byte command set */
614 nor->erase_opcode = SPINOR_OP_SE;
615 nor->mtd.erasesize = info->sector_size;
622 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
623 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
624 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
626 #endif /* !CONFIG_SPI_FLASH_BAR */
628 /* Enable/disable 4-byte addressing mode. */
629 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
633 bool need_wren = false;
636 switch (JEDEC_MFR(info)) {
638 case SNOR_MFR_MICRON:
639 /* Some Micron need WREN command; all will accept it */
642 case SNOR_MFR_MACRONIX:
643 case SNOR_MFR_WINBOND:
647 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
648 status = nor->write_reg(nor, cmd, NULL, 0);
652 if (!status && !enable &&
653 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
655 * On Winbond W25Q256FV, leaving 4byte mode causes
656 * the Extended Address Register to be set to 1, so all
657 * 3-byte-address reads come from the second 16M.
658 * We must clear the register to enable normal behavior.
662 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
667 case SNOR_MFR_CYPRESS:
668 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS;
669 return nor->write_reg(nor, cmd, NULL, 0);
672 nor->cmd_buf[0] = enable << 7;
673 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
677 #ifdef CONFIG_SPI_FLASH_SPANSION
679 * Read status register 1 by using Read Any Register command to support multi
682 static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy)
684 u32 reg_addr = addr_base + SPINOR_REG_ADDR_STR1V;
688 ret = spansion_read_any_reg(nor, reg_addr, dummy, &sr);
692 if (sr & (SR_E_ERR | SR_P_ERR)) {
694 dev_dbg(nor->dev, "Erase Error occurred\n");
696 dev_dbg(nor->dev, "Programming Error occurred\n");
698 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
702 return !(sr & SR_WIP);
706 static int spi_nor_sr_ready(struct spi_nor *nor)
708 int sr = read_sr(nor);
713 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
715 dev_dbg(nor->dev, "Erase Error occurred\n");
717 dev_dbg(nor->dev, "Programming Error occurred\n");
719 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
723 return !(sr & SR_WIP);
726 static int spi_nor_fsr_ready(struct spi_nor *nor)
728 int fsr = read_fsr(nor);
733 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
735 dev_err(nor->dev, "Erase operation failed.\n");
737 dev_err(nor->dev, "Program operation failed.\n");
739 if (fsr & FSR_PT_ERR)
741 "Attempted to modify a protected sector.\n");
743 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
747 return fsr & FSR_READY;
750 static int spi_nor_default_ready(struct spi_nor *nor)
754 sr = spi_nor_sr_ready(nor);
757 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
763 static int spi_nor_ready(struct spi_nor *nor)
766 return nor->ready(nor);
768 return spi_nor_default_ready(nor);
772 * Service routine to read status register until ready, or timeout occurs.
773 * Returns non-zero if error.
775 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
776 unsigned long timeout)
778 unsigned long timebase;
781 timebase = get_timer(0);
783 while (get_timer(timebase) < timeout) {
784 ret = spi_nor_ready(nor);
791 dev_err(nor->dev, "flash operation timed out\n");
796 static int spi_nor_wait_till_ready(struct spi_nor *nor)
798 return spi_nor_wait_till_ready_with_timeout(nor,
799 DEFAULT_READY_WAIT_JIFFIES);
802 #ifdef CONFIG_SPI_FLASH_BAR
804 * This "clean_bar" is necessary in a situation when one was accessing
805 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
807 * After it the BA24 bit shall be cleared to allow access to correct
808 * memory region after SW reset (by calling "reset" command).
810 * Otherwise, the BA24 bit may be left set and then after reset, the
811 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
813 static int clean_bar(struct spi_nor *nor)
815 u8 cmd, bank_sel = 0;
817 if (nor->bank_curr == 0)
819 cmd = nor->bank_write_cmd;
823 return nor->write_reg(nor, cmd, &bank_sel, 1);
826 static int write_bar(struct spi_nor *nor, u32 offset)
831 bank_sel = offset / SZ_16M;
832 if (bank_sel == nor->bank_curr)
835 cmd = nor->bank_write_cmd;
837 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
839 debug("SF: fail to write bank register\n");
844 nor->bank_curr = bank_sel;
845 return nor->bank_curr;
848 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
853 switch (JEDEC_MFR(info)) {
854 case SNOR_MFR_SPANSION:
855 nor->bank_read_cmd = SPINOR_OP_BRRD;
856 nor->bank_write_cmd = SPINOR_OP_BRWR;
859 nor->bank_read_cmd = SPINOR_OP_RDEAR;
860 nor->bank_write_cmd = SPINOR_OP_WREAR;
863 ret = nor->read_reg(nor, nor->bank_read_cmd,
866 debug("SF: fail to read bank addr register\n");
869 nor->bank_curr = curr_bank;
876 * Initiate the erasure of a single sector. Returns the number of bytes erased
877 * on success, a negative error code on error.
879 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
881 struct spi_mem_op op =
882 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
883 SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
888 spi_nor_setup_op(nor, &op, nor->write_proto);
891 return nor->erase(nor, addr);
894 * Default implementation, if driver doesn't have a specialized HW
897 ret = spi_mem_exec_op(nor->spi, &op);
901 return nor->mtd.erasesize;
905 * Erase an address range on the nor chip. The address range may extend
906 * one or more erase sectors. Return an error is there is a problem erasing.
908 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
910 struct spi_nor *nor = mtd_to_spi_nor(mtd);
914 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
915 (long long)instr->len);
920 div_u64_rem(instr->len, mtd->erasesize, &rem);
929 #ifdef CONFIG_SPI_FLASH_BAR
930 ret = write_bar(nor, addr);
934 ret = write_enable(nor);
938 ret = spi_nor_erase_sector(nor, addr);
945 ret = spi_nor_wait_till_ready(nor);
951 #ifdef CONFIG_SPI_FLASH_BAR
952 ret = clean_bar(nor);
959 #ifdef CONFIG_SPI_FLASH_SPANSION
961 * spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress
963 * @nor: pointer to a 'struct spi_nor'
964 * @addr: address of the sector to erase
965 * @opcode_4k: opcode for 4K sector erase
966 * @ovlsz_top: size of overlaid portion at the top address
967 * @ovlsz_btm: size of overlaid portion at the bottom address
969 * Erase an address range on the nor chip that can contain 4KB sectors overlaid
970 * on top and/or bottom. The appropriate erase opcode and size are chosen by
971 * address to erase and size of overlaid portion.
973 * Return: number of bytes erased on success, -errno otherwise.
975 static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr,
976 u8 opcode_4k, u32 ovlsz_top,
979 struct spi_mem_op op =
980 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
981 SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
984 struct mtd_info *mtd = &nor->mtd;
989 if (op.addr.val < ovlsz_btm ||
990 op.addr.val >= mtd->size - ovlsz_top) {
991 op.cmd.opcode = opcode_4k;
994 /* Non-overlaid portion in the normal sector at the bottom */
995 } else if (op.addr.val == ovlsz_btm) {
996 op.cmd.opcode = nor->erase_opcode;
997 erasesize = mtd->erasesize - ovlsz_btm;
999 /* Non-overlaid portion in the normal sector at the top */
1000 } else if (op.addr.val == mtd->size - mtd->erasesize) {
1001 op.cmd.opcode = nor->erase_opcode;
1002 erasesize = mtd->erasesize - ovlsz_top;
1004 /* Normal sectors */
1006 op.cmd.opcode = nor->erase_opcode;
1007 erasesize = mtd->erasesize;
1010 spi_nor_setup_op(nor, &op, nor->write_proto);
1012 ret = spi_mem_exec_op(nor->spi, &op);
1020 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
1021 /* Write status register and ensure bits in mask match written values */
1022 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
1027 ret = write_sr(nor, status_new);
1031 ret = spi_nor_wait_till_ready(nor);
1039 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
1042 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
1045 struct mtd_info *mtd = &nor->mtd;
1046 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1047 int shift = ffs(mask) - 1;
1055 pow = ((sr & mask) ^ mask) >> shift;
1056 *len = mtd->size >> pow;
1057 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
1060 *ofs = mtd->size - *len;
1065 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
1066 * @locked is false); 0 otherwise
1068 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
1077 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
1080 /* Requested range is a sub-range of locked range */
1081 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
1083 /* Requested range does not overlap with locked range */
1084 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
1087 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1090 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
1093 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1096 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
1100 * Lock a region of the flash. Compatible with ST Micro and similar flash.
1101 * Supports the block protection bits BP{0,1,2} in the status register
1102 * (SR). Does not support these features found in newer SR bitfields:
1103 * - SEC: sector/block protect - only handle SEC=0 (block protect)
1104 * - CMP: complement protect - only support CMP=0 (range is not complemented)
1106 * Support for the following is provided conditionally for some flash:
1107 * - TB: top/bottom protect
1109 * Sample table portion for 8MB flash (Winbond w25q64fw):
1111 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
1112 * --------------------------------------------------------------------------
1113 * X | X | 0 | 0 | 0 | NONE | NONE
1114 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
1115 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
1116 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
1117 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
1118 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
1119 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
1120 * X | X | 1 | 1 | 1 | 8 MB | ALL
1121 * ------|-------|-------|-------|-------|---------------|-------------------
1122 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
1123 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
1124 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
1125 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
1126 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
1127 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
1129 * Returns negative on errors, 0 on success.
1131 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1133 struct mtd_info *mtd = &nor->mtd;
1134 int status_old, status_new;
1135 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1136 u8 shift = ffs(mask) - 1, pow, val;
1138 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1141 status_old = read_sr(nor);
1145 /* If nothing in our range is unlocked, we don't need to do anything */
1146 if (stm_is_locked_sr(nor, ofs, len, status_old))
1149 /* If anything below us is unlocked, we can't use 'bottom' protection */
1150 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
1151 can_be_bottom = false;
1153 /* If anything above us is unlocked, we can't use 'top' protection */
1154 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1158 if (!can_be_bottom && !can_be_top)
1161 /* Prefer top, if both are valid */
1162 use_top = can_be_top;
1164 /* lock_len: length of region that should end up locked */
1166 lock_len = mtd->size - ofs;
1168 lock_len = ofs + len;
1171 * Need smallest pow such that:
1173 * 1 / (2^pow) <= (len / size)
1175 * so (assuming power-of-2 size) we do:
1177 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
1179 pow = ilog2(mtd->size) - ilog2(lock_len);
1180 val = mask - (pow << shift);
1183 /* Don't "lock" with no region! */
1187 status_new = (status_old & ~mask & ~SR_TB) | val;
1189 /* Disallow further writes if WP pin is asserted */
1190 status_new |= SR_SRWD;
1193 status_new |= SR_TB;
1195 /* Don't bother if they're the same */
1196 if (status_new == status_old)
1199 /* Only modify protection if it will not unlock other areas */
1200 if ((status_new & mask) < (status_old & mask))
1203 return write_sr_and_check(nor, status_new, mask);
1207 * Unlock a region of the flash. See stm_lock() for more info
1209 * Returns negative on errors, 0 on success.
1211 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1213 struct mtd_info *mtd = &nor->mtd;
1214 int status_old, status_new;
1215 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1216 u8 shift = ffs(mask) - 1, pow, val;
1218 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1221 status_old = read_sr(nor);
1225 /* If nothing in our range is locked, we don't need to do anything */
1226 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
1229 /* If anything below us is locked, we can't use 'top' protection */
1230 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
1233 /* If anything above us is locked, we can't use 'bottom' protection */
1234 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1236 can_be_bottom = false;
1238 if (!can_be_bottom && !can_be_top)
1241 /* Prefer top, if both are valid */
1242 use_top = can_be_top;
1244 /* lock_len: length of region that should remain locked */
1246 lock_len = mtd->size - (ofs + len);
1251 * Need largest pow such that:
1253 * 1 / (2^pow) >= (len / size)
1255 * so (assuming power-of-2 size) we do:
1257 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
1259 pow = ilog2(mtd->size) - order_base_2(lock_len);
1260 if (lock_len == 0) {
1261 val = 0; /* fully unlocked */
1263 val = mask - (pow << shift);
1264 /* Some power-of-two sizes are not supported */
1269 status_new = (status_old & ~mask & ~SR_TB) | val;
1271 /* Don't protect status register if we're fully unlocked */
1273 status_new &= ~SR_SRWD;
1276 status_new |= SR_TB;
1278 /* Don't bother if they're the same */
1279 if (status_new == status_old)
1282 /* Only modify protection if it will not lock other areas */
1283 if ((status_new & mask) > (status_old & mask))
1286 return write_sr_and_check(nor, status_new, mask);
1290 * Check if a region of the flash is (completely) locked. See stm_lock() for
1293 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1294 * negative on errors.
1296 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1300 status = read_sr(nor);
1304 return stm_is_locked_sr(nor, ofs, len, status);
1306 #endif /* CONFIG_SPI_FLASH_STMICRO */
1308 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1311 u8 id[SPI_NOR_MAX_ID_LEN];
1312 const struct flash_info *info;
1314 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1316 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1317 return ERR_PTR(tmp);
1321 for (; info->name; info++) {
1323 if (!memcmp(info->id, id, info->id_len))
1328 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1329 id[0], id[1], id[2]);
1330 return ERR_PTR(-ENODEV);
1333 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1334 size_t *retlen, u_char *buf)
1336 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1339 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1343 size_t read_len = len;
1345 #ifdef CONFIG_SPI_FLASH_BAR
1348 ret = write_bar(nor, addr);
1350 return log_ret(ret);
1351 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
1353 if (len < remain_len)
1356 read_len = remain_len;
1359 ret = nor->read(nor, addr, read_len, buf);
1361 /* We shouldn't see 0-length reads */
1376 #ifdef CONFIG_SPI_FLASH_BAR
1377 ret = clean_bar(nor);
1382 #ifdef CONFIG_SPI_FLASH_SST
1384 * sst26 flash series has its own block protection implementation:
1385 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
1386 * 1x - 32 KByte blocks - write protection bits
1387 * rest - 64 KByte blocks - write protection bits
1388 * 1x - 32 KByte blocks - write protection bits
1389 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
1391 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
1392 * will be treated as single block.
1394 #define SST26_BPR_8K_NUM 4
1395 #define SST26_MAX_BPR_REG_LEN (18 + 1)
1396 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
1404 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
1407 case SST26_CTL_LOCK:
1408 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
1410 case SST26_CTL_UNLOCK:
1411 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
1413 case SST26_CTL_CHECK:
1414 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
1421 * Lock, unlock or check lock status of the flash region of the flash (depending
1422 * on the lock_ctl value)
1424 static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
1426 struct mtd_info *mtd = &nor->mtd;
1427 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
1428 bool lower_64k = false, upper_64k = false;
1429 u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
1432 /* Check length and offset for 64k alignment */
1433 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
1434 dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
1438 if (ofs + len > mtd->size) {
1439 dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
1440 ofs, len, mtd->size);
1444 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
1445 if (mtd->size != SZ_2M &&
1446 mtd->size != SZ_4M &&
1450 bpr_size = 2 + (mtd->size / SZ_64K / 8);
1452 ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
1454 dev_err(nor->dev, "fail to read block-protection register\n");
1458 rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
1459 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
1461 upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
1462 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
1464 /* Lower bits in block-protection register are about 64k region */
1465 bpr_ptr = lptr_64k / SZ_64K - 1;
1467 /* Process 64K blocks region */
1468 while (lptr_64k < rptr_64k) {
1469 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1476 /* 32K and 8K region bits in BPR are after 64k region bits */
1477 bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
1479 /* Process lower 32K block region */
1481 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1486 /* Process upper 32K block region */
1488 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1493 /* Process lower 8K block regions */
1494 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1496 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1499 /* In 8K area BPR has both read and write protection bits */
1503 /* Process upper 8K block regions */
1504 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1506 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1509 /* In 8K area BPR has both read and write protection bits */
1513 /* If we check region status we don't need to write BPR back */
1514 if (ctl == SST26_CTL_CHECK)
1517 ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
1519 dev_err(nor->dev, "fail to write block-protection register\n");
1526 static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1528 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
1531 static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1533 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
1537 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
1538 * and negative on errors.
1540 static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1543 * is_locked function is used for check before reading or erasing flash
1544 * region, so offset and length might be not 64k allighned, so adjust
1545 * them to be 64k allighned as sst26_lock_ctl works only with 64k
1546 * allighned regions.
1548 ofs -= ofs & (SZ_64K - 1);
1549 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
1551 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
1554 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
1555 size_t *retlen, const u_char *buf)
1560 for (actual = 0; actual < len; actual++) {
1561 nor->program_opcode = SPINOR_OP_BP;
1564 /* write one byte. */
1565 ret = nor->write(nor, to, 1, buf + actual);
1568 ret = spi_nor_wait_till_ready(nor);
1579 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1580 size_t *retlen, const u_char *buf)
1582 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1583 struct spi_slave *spi = nor->spi;
1587 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1588 if (spi->mode & SPI_TX_BYTE)
1589 return sst_write_byteprogram(nor, to, len, retlen, buf);
1593 nor->sst_write_second = false;
1596 /* Start write from odd address. */
1598 nor->program_opcode = SPINOR_OP_BP;
1600 /* write one byte. */
1601 ret = nor->write(nor, to, 1, buf);
1604 ret = spi_nor_wait_till_ready(nor);
1610 /* Write out most of the data here. */
1611 for (; actual < len - 1; actual += 2) {
1612 nor->program_opcode = SPINOR_OP_AAI_WP;
1614 /* write two bytes. */
1615 ret = nor->write(nor, to, 2, buf + actual);
1618 ret = spi_nor_wait_till_ready(nor);
1622 nor->sst_write_second = true;
1624 nor->sst_write_second = false;
1627 ret = spi_nor_wait_till_ready(nor);
1631 /* Write out trailing byte if it exists. */
1632 if (actual != len) {
1635 nor->program_opcode = SPINOR_OP_BP;
1636 ret = nor->write(nor, to, 1, buf + actual);
1639 ret = spi_nor_wait_till_ready(nor);
1651 * Write an address range to the nor chip. Data must be written in
1652 * FLASH_PAGESIZE chunks. The address range may be any size provided
1653 * it is within the physical boundaries.
1655 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1656 size_t *retlen, const u_char *buf)
1658 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1659 size_t page_offset, page_remain, i;
1662 #ifdef CONFIG_SPI_FLASH_SST
1663 /* sst nor chips use AAI word program */
1664 if (nor->info->flags & SST_WRITE)
1665 return sst_write(mtd, to, len, retlen, buf);
1668 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1673 for (i = 0; i < len; ) {
1675 loff_t addr = to + i;
1679 * If page_size is a power of two, the offset can be quickly
1680 * calculated with an AND operation. On the other cases we
1681 * need to do a modulus operation (more expensive).
1683 if (is_power_of_2(nor->page_size)) {
1684 page_offset = addr & (nor->page_size - 1);
1688 page_offset = do_div(aux, nor->page_size);
1690 /* the size of data remaining on the first page */
1691 page_remain = min_t(size_t,
1692 nor->page_size - page_offset, len - i);
1694 #ifdef CONFIG_SPI_FLASH_BAR
1695 ret = write_bar(nor, addr);
1700 ret = nor->write(nor, addr, page_remain, buf + i);
1705 ret = spi_nor_wait_till_ready(nor);
1713 #ifdef CONFIG_SPI_FLASH_BAR
1714 ret = clean_bar(nor);
1719 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
1721 * macronix_quad_enable() - set QE bit in Status Register.
1722 * @nor: pointer to a 'struct spi_nor'
1724 * Set the Quad Enable (QE) bit in the Status Register.
1726 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1728 * Return: 0 on success, -errno otherwise.
1730 static int macronix_quad_enable(struct spi_nor *nor)
1737 if (val & SR_QUAD_EN_MX)
1742 write_sr(nor, val | SR_QUAD_EN_MX);
1744 ret = spi_nor_wait_till_ready(nor);
1749 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1750 dev_err(nor->dev, "Macronix Quad bit not set\n");
1758 #ifdef CONFIG_SPI_FLASH_SPANSION
1760 * spansion_quad_enable_volatile() - enable Quad I/O mode in volatile register.
1761 * @nor: pointer to a 'struct spi_nor'
1762 * @addr_base: base address of register (can be >0 in multi-die parts)
1763 * @dummy: number of dummy cycles for register read
1765 * It is recommended to update volatile registers in the field application due
1766 * to a risk of the non-volatile registers corruption by power interrupt. This
1767 * function sets Quad Enable bit in CFR1 volatile.
1769 * Return: 0 on success, -errno otherwise.
1771 static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base,
1774 u32 addr = addr_base + SPINOR_REG_ADDR_CFR1V;
1779 /* Check current Quad Enable bit value. */
1780 ret = spansion_read_any_reg(nor, addr, dummy, &cr);
1783 "error while reading configuration register\n");
1787 if (cr & CR_QUAD_EN_SPAN)
1790 cr |= CR_QUAD_EN_SPAN;
1794 ret = spansion_write_any_reg(nor, addr, cr);
1798 "error while writing configuration register\n");
1802 /* Read back and check it. */
1803 ret = spansion_read_any_reg(nor, addr, dummy, &cr);
1804 if (ret || !(cr & CR_QUAD_EN_SPAN)) {
1805 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1813 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1815 * Write status Register and configuration register with 2 bytes
1816 * The first byte will be written to the status register, while the
1817 * second byte will be written to the configuration register.
1818 * Return negative if error occurred.
1820 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1826 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1829 "error while writing configuration register\n");
1833 ret = spi_nor_wait_till_ready(nor);
1836 "timeout while writing configuration register\n");
1844 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1845 * @nor: pointer to a 'struct spi_nor'
1847 * Set the Quad Enable (QE) bit in the Configuration Register.
1848 * This function should be used with QSPI memories supporting the Read
1849 * Configuration Register (35h) instruction.
1851 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1854 * Return: 0 on success, -errno otherwise.
1856 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1861 /* Check current Quad Enable bit value. */
1865 "error while reading configuration register\n");
1869 if (ret & CR_QUAD_EN_SPAN)
1872 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1874 /* Keep the current value of the Status Register. */
1877 dev_dbg(nor->dev, "error while reading status register\n");
1882 ret = write_sr_cr(nor, sr_cr);
1886 /* Read back and check it. */
1888 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1889 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1896 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1898 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1899 * @nor: pointer to a 'struct spi_nor'
1901 * Set the Quad Enable (QE) bit in the Configuration Register.
1902 * This function should be used with QSPI memories not supporting the Read
1903 * Configuration Register (35h) instruction.
1905 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1908 * Return: 0 on success, -errno otherwise.
1910 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1915 /* Keep the current value of the Status Register. */
1918 dev_dbg(nor->dev, "error while reading status register\n");
1922 sr_cr[1] = CR_QUAD_EN_SPAN;
1924 return write_sr_cr(nor, sr_cr);
1927 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1928 #endif /* CONFIG_SPI_FLASH_SPANSION */
1931 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1935 enum spi_nor_protocol proto)
1937 read->num_mode_clocks = num_mode_clocks;
1938 read->num_wait_states = num_wait_states;
1939 read->opcode = opcode;
1940 read->proto = proto;
1944 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1946 enum spi_nor_protocol proto)
1948 pp->opcode = opcode;
1952 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1954 * Serial Flash Discoverable Parameters (SFDP) parsing.
1958 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1959 * @nor: pointer to a 'struct spi_nor'
1960 * @addr: offset in the SFDP area to start reading data from
1961 * @len: number of bytes to read
1962 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1964 * Whatever the actual numbers of bytes for address and dummy cycles are
1965 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1966 * followed by a 3-byte address and 8 dummy clock cycles.
1968 * Return: 0 on success, -errno otherwise.
1970 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1971 size_t len, void *buf)
1973 u8 addr_width, read_opcode, read_dummy;
1976 read_opcode = nor->read_opcode;
1977 addr_width = nor->addr_width;
1978 read_dummy = nor->read_dummy;
1980 nor->read_opcode = SPINOR_OP_RDSFDP;
1981 nor->addr_width = 3;
1982 nor->read_dummy = 8;
1985 ret = nor->read(nor, addr, len, (u8 *)buf);
1986 if (!ret || ret > len) {
2000 nor->read_opcode = read_opcode;
2001 nor->addr_width = addr_width;
2002 nor->read_dummy = read_dummy;
2007 /* Fast Read settings. */
2010 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
2012 enum spi_nor_protocol proto)
2014 read->num_mode_clocks = (half >> 5) & 0x07;
2015 read->num_wait_states = (half >> 0) & 0x1f;
2016 read->opcode = (half >> 8) & 0xff;
2017 read->proto = proto;
2020 struct sfdp_bfpt_read {
2021 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
2025 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
2026 * whether the Fast Read x-y-z command is supported.
2028 u32 supported_dword;
2032 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
2033 * encodes the op code, the number of mode clocks and the number of wait
2034 * states to be used by Fast Read x-y-z command.
2039 /* The SPI protocol for this Fast Read x-y-z command. */
2040 enum spi_nor_protocol proto;
2043 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
2044 /* Fast Read 1-1-2 */
2046 SNOR_HWCAPS_READ_1_1_2,
2047 BFPT_DWORD(1), BIT(16), /* Supported bit */
2048 BFPT_DWORD(4), 0, /* Settings */
2052 /* Fast Read 1-2-2 */
2054 SNOR_HWCAPS_READ_1_2_2,
2055 BFPT_DWORD(1), BIT(20), /* Supported bit */
2056 BFPT_DWORD(4), 16, /* Settings */
2060 /* Fast Read 2-2-2 */
2062 SNOR_HWCAPS_READ_2_2_2,
2063 BFPT_DWORD(5), BIT(0), /* Supported bit */
2064 BFPT_DWORD(6), 16, /* Settings */
2068 /* Fast Read 1-1-4 */
2070 SNOR_HWCAPS_READ_1_1_4,
2071 BFPT_DWORD(1), BIT(22), /* Supported bit */
2072 BFPT_DWORD(3), 16, /* Settings */
2076 /* Fast Read 1-4-4 */
2078 SNOR_HWCAPS_READ_1_4_4,
2079 BFPT_DWORD(1), BIT(21), /* Supported bit */
2080 BFPT_DWORD(3), 0, /* Settings */
2084 /* Fast Read 4-4-4 */
2086 SNOR_HWCAPS_READ_4_4_4,
2087 BFPT_DWORD(5), BIT(4), /* Supported bit */
2088 BFPT_DWORD(7), 16, /* Settings */
2093 struct sfdp_bfpt_erase {
2095 * The half-word at offset <shift> in DWORD <dwoard> encodes the
2096 * op code and erase sector size to be used by Sector Erase commands.
2102 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
2103 /* Erase Type 1 in DWORD8 bits[15:0] */
2106 /* Erase Type 2 in DWORD8 bits[31:16] */
2107 {BFPT_DWORD(8), 16},
2109 /* Erase Type 3 in DWORD9 bits[15:0] */
2112 /* Erase Type 4 in DWORD9 bits[31:16] */
2113 {BFPT_DWORD(9), 16},
2116 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
2119 spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2120 const struct sfdp_parameter_header *bfpt_header,
2121 const struct sfdp_bfpt *bfpt,
2122 struct spi_nor_flash_parameter *params)
2124 if (nor->fixups && nor->fixups->post_bfpt)
2125 return nor->fixups->post_bfpt(nor, bfpt_header, bfpt, params);
2131 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
2132 * @nor: pointer to a 'struct spi_nor'
2133 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
2134 * the Basic Flash Parameter Table length and version
2135 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2138 * The Basic Flash Parameter Table is the main and only mandatory table as
2139 * defined by the SFDP (JESD216) specification.
2140 * It provides us with the total size (memory density) of the data array and
2141 * the number of address bytes for Fast Read, Page Program and Sector Erase
2143 * For Fast READ commands, it also gives the number of mode clock cycles and
2144 * wait states (regrouped in the number of dummy clock cycles) for each
2145 * supported instruction op code.
2146 * For Page Program, the page size is now available since JESD216 rev A, however
2147 * the supported instruction op codes are still not provided.
2148 * For Sector Erase commands, this table stores the supported instruction op
2149 * codes and the associated sector sizes.
2150 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
2151 * rev A. The QER bits encode the manufacturer dependent procedure to be
2152 * executed to set the Quad Enable (QE) bit in some internal register of the
2153 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
2154 * sending any Quad SPI command to the memory. Actually, setting the QE bit
2155 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
2156 * and IO3 hence enabling 4 (Quad) I/O lines.
2158 * Return: 0 on success, -errno otherwise.
2160 static int spi_nor_parse_bfpt(struct spi_nor *nor,
2161 const struct sfdp_parameter_header *bfpt_header,
2162 struct spi_nor_flash_parameter *params)
2164 struct mtd_info *mtd = &nor->mtd;
2165 struct sfdp_bfpt bfpt;
2171 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
2172 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
2175 /* Read the Basic Flash Parameter Table. */
2176 len = min_t(size_t, sizeof(bfpt),
2177 bfpt_header->length * sizeof(u32));
2178 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2179 memset(&bfpt, 0, sizeof(bfpt));
2180 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
2184 /* Fix endianness of the BFPT DWORDs. */
2185 for (i = 0; i < BFPT_DWORD_MAX; i++)
2186 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
2188 /* Number of address bytes. */
2189 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
2190 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
2191 nor->addr_width = 3;
2194 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
2195 nor->addr_width = 4;
2202 /* Flash Memory Density (in bits). */
2203 params->size = bfpt.dwords[BFPT_DWORD(2)];
2204 if (params->size & BIT(31)) {
2205 params->size &= ~BIT(31);
2208 * Prevent overflows on params->size. Anyway, a NOR of 2^64
2209 * bits is unlikely to exist so this error probably means
2210 * the BFPT we are reading is corrupted/wrong.
2212 if (params->size > 63)
2215 params->size = 1ULL << params->size;
2219 params->size >>= 3; /* Convert to bytes. */
2221 /* Fast Read settings. */
2222 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
2223 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
2224 struct spi_nor_read_command *read;
2226 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
2227 params->hwcaps.mask &= ~rd->hwcaps;
2231 params->hwcaps.mask |= rd->hwcaps;
2232 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
2233 read = ¶ms->reads[cmd];
2234 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
2235 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
2238 /* Sector Erase settings. */
2239 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
2240 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
2244 half = bfpt.dwords[er->dword] >> er->shift;
2245 erasesize = half & 0xff;
2247 /* erasesize == 0 means this Erase Type is not supported. */
2251 erasesize = 1U << erasesize;
2252 opcode = (half >> 8) & 0xff;
2253 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2254 if (erasesize == SZ_4K) {
2255 nor->erase_opcode = opcode;
2256 mtd->erasesize = erasesize;
2260 if (!mtd->erasesize || mtd->erasesize < erasesize) {
2261 nor->erase_opcode = opcode;
2262 mtd->erasesize = erasesize;
2266 /* Stop here if not JESD216 rev A or later. */
2267 if (bfpt_header->length == BFPT_DWORD_MAX_JESD216)
2268 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2271 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2272 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2273 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2274 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2275 params->page_size = 1U << params->page_size;
2277 /* Quad Enable Requirements. */
2278 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2279 case BFPT_DWORD15_QER_NONE:
2280 params->quad_enable = NULL;
2282 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2283 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2284 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2285 params->quad_enable = spansion_no_read_cr_quad_enable;
2288 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
2289 case BFPT_DWORD15_QER_SR1_BIT6:
2290 params->quad_enable = macronix_quad_enable;
2293 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2294 case BFPT_DWORD15_QER_SR2_BIT1:
2295 params->quad_enable = spansion_read_cr_quad_enable;
2299 dev_dbg(nor->dev, "BFPT QER reserved value used\n");
2303 /* Soft Reset support. */
2304 if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SOFT_RST)
2305 nor->flags |= SNOR_F_SOFT_RESET;
2307 /* Stop here if JESD216 rev B. */
2308 if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B)
2309 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2312 /* 8D-8D-8D command extension. */
2313 switch (bfpt.dwords[BFPT_DWORD(18)] & BFPT_DWORD18_CMD_EXT_MASK) {
2314 case BFPT_DWORD18_CMD_EXT_REP:
2315 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
2318 case BFPT_DWORD18_CMD_EXT_INV:
2319 nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
2322 case BFPT_DWORD18_CMD_EXT_RES:
2325 case BFPT_DWORD18_CMD_EXT_16B:
2326 dev_err(nor->dev, "16-bit opcodes not supported\n");
2330 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
2334 * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
2336 * @nor: pointer to a 'struct spi_nor'.
2337 * @param_header: pointer to the SFDP parameter header.
2339 * Return: 0 on success, -errno otherwise.
2342 spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
2343 const struct sfdp_parameter_header *param_header)
2349 size = param_header->length * sizeof(u32);
2350 addr = SFDP_PARAM_HEADER_PTP(param_header);
2352 nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
2353 if (!nor->manufacturer_sfdp)
2356 ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
2362 * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
2363 * @nor: pointer to a 'struct spi_nor'
2364 * @profile1_header: pointer to the 'struct sfdp_parameter_header' describing
2365 * the 4-Byte Address Instruction Table length and version.
2366 * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
2368 * Return: 0 on success, -errno otherwise.
2370 static int spi_nor_parse_profile1(struct spi_nor *nor,
2371 const struct sfdp_parameter_header *profile1_header,
2372 struct spi_nor_flash_parameter *params)
2374 u32 *table, opcode, addr;
2379 len = profile1_header->length * sizeof(*table);
2380 table = kmalloc(len, GFP_KERNEL);
2384 addr = SFDP_PARAM_HEADER_PTP(profile1_header);
2385 ret = spi_nor_read_sfdp(nor, addr, len, table);
2389 /* Fix endianness of the table DWORDs. */
2390 for (i = 0; i < profile1_header->length; i++)
2391 table[i] = le32_to_cpu(table[i]);
2393 /* Get 8D-8D-8D fast read opcode and dummy cycles. */
2394 opcode = FIELD_GET(PROFILE1_DWORD1_RD_FAST_CMD, table[0]);
2397 * We don't know what speed the controller is running at. Find the
2398 * dummy cycles for the fastest frequency the flash can run at to be
2399 * sure we are never short of dummy cycles. A value of 0 means the
2400 * frequency is not supported.
2402 * Default to PROFILE1_DUMMY_DEFAULT if we don't find anything, and let
2403 * flashes set the correct value if needed in their fixup hooks.
2405 dummy = FIELD_GET(PROFILE1_DWORD4_DUMMY_200MHZ, table[3]);
2407 dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_166MHZ, table[4]);
2409 dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_133MHZ, table[4]);
2411 dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_100MHZ, table[4]);
2413 dummy = PROFILE1_DUMMY_DEFAULT;
2415 /* Round up to an even value to avoid tripping controllers up. */
2416 dummy = ROUND_UP_TO(dummy, 2);
2418 /* Update the fast read settings. */
2419 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
2421 SNOR_PROTO_8_8_8_DTR);
2424 * Set the Read Status Register dummy cycles and dummy address bytes.
2426 if (table[0] & PROFILE1_DWORD1_RDSR_DUMMY)
2427 params->rdsr_dummy = 8;
2429 params->rdsr_dummy = 4;
2431 if (table[0] & PROFILE1_DWORD1_RDSR_ADDR_BYTES)
2432 params->rdsr_addr_nbytes = 4;
2434 params->rdsr_addr_nbytes = 0;
2442 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2443 * @nor: pointer to a 'struct spi_nor'
2444 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2447 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2448 * specification. This is a standard which tends to supported by almost all
2449 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2450 * runtime the main parameters needed to perform basic SPI flash operations such
2451 * as Fast Read, Page Program or Sector Erase commands.
2453 * Return: 0 on success, -errno otherwise.
2455 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2456 struct spi_nor_flash_parameter *params)
2458 const struct sfdp_parameter_header *param_header, *bfpt_header;
2459 struct sfdp_parameter_header *param_headers = NULL;
2460 struct sfdp_header header;
2464 /* Get the SFDP header. */
2465 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2469 /* Check the SFDP header version. */
2470 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2471 header.major != SFDP_JESD216_MAJOR)
2475 * Verify that the first and only mandatory parameter header is a
2476 * Basic Flash Parameter Table header as specified in JESD216.
2478 bfpt_header = &header.bfpt_header;
2479 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2480 bfpt_header->major != SFDP_JESD216_MAJOR)
2484 * Allocate memory then read all parameter headers with a single
2485 * Read SFDP command. These parameter headers will actually be parsed
2486 * twice: a first time to get the latest revision of the basic flash
2487 * parameter table, then a second time to handle the supported optional
2489 * Hence we read the parameter headers once for all to reduce the
2490 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2491 * because we don't need to keep these parameter headers: the allocated
2492 * memory is always released with kfree() before exiting this function.
2495 psize = header.nph * sizeof(*param_headers);
2497 param_headers = kmalloc(psize, GFP_KERNEL);
2501 err = spi_nor_read_sfdp(nor, sizeof(header),
2502 psize, param_headers);
2505 "failed to read SFDP parameter headers\n");
2511 * Check other parameter headers to get the latest revision of
2512 * the basic flash parameter table.
2514 for (i = 0; i < header.nph; i++) {
2515 param_header = ¶m_headers[i];
2517 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2518 param_header->major == SFDP_JESD216_MAJOR &&
2519 (param_header->minor > bfpt_header->minor ||
2520 (param_header->minor == bfpt_header->minor &&
2521 param_header->length > bfpt_header->length)))
2522 bfpt_header = param_header;
2525 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2529 /* Parse other parameter headers. */
2530 for (i = 0; i < header.nph; i++) {
2531 param_header = ¶m_headers[i];
2533 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2534 case SFDP_SECTOR_MAP_ID:
2536 "non-uniform erase sector maps are not supported yet.\n");
2540 err = spi_nor_parse_microchip_sfdp(nor, param_header);
2543 case SFDP_PROFILE1_ID:
2544 err = spi_nor_parse_profile1(nor, param_header, params);
2553 "Failed to parse optional parameter table: %04x\n",
2554 SFDP_PARAM_HEADER_ID(param_header));
2556 * Let's not drop all information we extracted so far
2557 * if optional table parsers fail. In case of failing,
2558 * each optional parser is responsible to roll back to
2559 * the previously known spi_nor data.
2566 kfree(param_headers);
2570 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2571 struct spi_nor_flash_parameter *params)
2575 #endif /* SPI_FLASH_SFDP_SUPPORT */
2578 * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
2579 * after SFDP has been parsed (is also called for SPI NORs that do not
2581 * @nor: pointer to a 'struct spi_nor'
2583 * Typically used to tweak various parameters that could not be extracted by
2584 * other means (i.e. when information provided by the SFDP/flash_info tables
2585 * are incomplete or wrong).
2587 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor,
2588 struct spi_nor_flash_parameter *params)
2590 if (nor->fixups && nor->fixups->post_sfdp)
2591 nor->fixups->post_sfdp(nor, params);
2594 static void spi_nor_default_init_fixups(struct spi_nor *nor)
2596 if (nor->fixups && nor->fixups->default_init)
2597 nor->fixups->default_init(nor);
2600 static int spi_nor_init_params(struct spi_nor *nor,
2601 const struct flash_info *info,
2602 struct spi_nor_flash_parameter *params)
2604 /* Set legacy flash parameters as default. */
2605 memset(params, 0, sizeof(*params));
2607 /* Set SPI NOR sizes. */
2608 params->size = info->sector_size * info->n_sectors;
2609 params->page_size = info->page_size;
2611 if (!(info->flags & SPI_NOR_NO_FR)) {
2612 /* Default to Fast Read for DT and non-DT platform devices. */
2613 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2615 /* Mask out Fast Read if not requested at DT instantiation. */
2616 #if CONFIG_IS_ENABLED(DM_SPI)
2617 if (!ofnode_read_bool(dev_ofnode(nor->spi->dev),
2619 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2623 /* (Fast) Read settings. */
2624 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2625 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2626 0, 0, SPINOR_OP_READ,
2629 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
2630 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2631 0, 8, SPINOR_OP_READ_FAST,
2634 if (info->flags & SPI_NOR_DUAL_READ) {
2635 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2636 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2637 0, 8, SPINOR_OP_READ_1_1_2,
2641 if (info->flags & SPI_NOR_QUAD_READ) {
2642 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2643 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2644 0, 8, SPINOR_OP_READ_1_1_4,
2648 if (info->flags & SPI_NOR_OCTAL_READ) {
2649 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2650 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
2651 0, 8, SPINOR_OP_READ_1_1_8,
2655 if (info->flags & SPI_NOR_OCTAL_DTR_READ) {
2656 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2657 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
2658 0, 20, SPINOR_OP_READ_FAST,
2659 SNOR_PROTO_8_8_8_DTR);
2662 /* Page Program settings. */
2663 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2664 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2665 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2668 * Since xSPI Page Program opcode is backward compatible with
2669 * Legacy SPI, use Legacy SPI opcode there as well.
2671 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2672 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2674 if (info->flags & SPI_NOR_QUAD_READ) {
2675 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2676 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2677 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2680 /* Select the procedure to set the Quad Enable bit. */
2681 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2682 SNOR_HWCAPS_PP_QUAD)) {
2683 switch (JEDEC_MFR(info)) {
2684 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
2685 case SNOR_MFR_MACRONIX:
2687 params->quad_enable = macronix_quad_enable;
2691 case SNOR_MFR_MICRON:
2695 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2696 /* Kept only for backward compatibility purpose. */
2697 params->quad_enable = spansion_read_cr_quad_enable;
2703 spi_nor_default_init_fixups(nor);
2705 /* Override the parameters with data read from SFDP tables. */
2706 nor->addr_width = 0;
2707 nor->mtd.erasesize = 0;
2708 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2709 SPI_NOR_OCTAL_DTR_READ)) &&
2710 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2711 struct spi_nor_flash_parameter sfdp_params;
2713 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2714 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2715 nor->addr_width = 0;
2716 nor->mtd.erasesize = 0;
2718 memcpy(params, &sfdp_params, sizeof(*params));
2722 spi_nor_post_sfdp_fixups(nor, params);
2727 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2731 for (i = 0; i < size; i++)
2732 if (table[i][0] == (int)hwcaps)
2738 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2740 static const int hwcaps_read2cmd[][2] = {
2741 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2742 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2743 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2744 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2745 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2746 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2747 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2748 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2749 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2750 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2751 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2752 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2753 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2754 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2755 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2756 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },
2759 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2760 ARRAY_SIZE(hwcaps_read2cmd));
2763 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2765 static const int hwcaps_pp2cmd[][2] = {
2766 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2767 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2768 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2769 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2770 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2771 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2772 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2773 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },
2776 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2777 ARRAY_SIZE(hwcaps_pp2cmd));
2780 #ifdef CONFIG_SPI_FLASH_SMART_HWCAPS
2782 * spi_nor_check_op - check if the operation is supported by controller
2783 * @nor: pointer to a 'struct spi_nor'
2784 * @op: pointer to op template to be checked
2786 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2788 static int spi_nor_check_op(struct spi_nor *nor,
2789 struct spi_mem_op *op)
2792 * First test with 4 address bytes. The opcode itself might be a 3B
2793 * addressing opcode but we don't care, because SPI controller
2794 * implementation should not check the opcode, but just the sequence.
2796 op->addr.nbytes = 4;
2797 if (!spi_mem_supports_op(nor->spi, op)) {
2798 if (nor->mtd.size > SZ_16M)
2801 /* If flash size <= 16MB, 3 address bytes are sufficient */
2802 op->addr.nbytes = 3;
2803 if (!spi_mem_supports_op(nor->spi, op))
2811 * spi_nor_check_readop - check if the read op is supported by controller
2812 * @nor: pointer to a 'struct spi_nor'
2813 * @read: pointer to op template to be checked
2815 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2817 static int spi_nor_check_readop(struct spi_nor *nor,
2818 const struct spi_nor_read_command *read)
2820 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0),
2821 SPI_MEM_OP_ADDR(3, 0, 0),
2822 SPI_MEM_OP_DUMMY(1, 0),
2823 SPI_MEM_OP_DATA_IN(2, NULL, 0));
2825 spi_nor_setup_op(nor, &op, read->proto);
2827 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2828 op.dummy.buswidth / 8;
2829 if (spi_nor_protocol_is_dtr(nor->read_proto))
2830 op.dummy.nbytes *= 2;
2832 return spi_nor_check_op(nor, &op);
2836 * spi_nor_check_pp - check if the page program op is supported by controller
2837 * @nor: pointer to a 'struct spi_nor'
2838 * @pp: pointer to op template to be checked
2840 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2842 static int spi_nor_check_pp(struct spi_nor *nor,
2843 const struct spi_nor_pp_command *pp)
2845 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0),
2846 SPI_MEM_OP_ADDR(3, 0, 0),
2847 SPI_MEM_OP_NO_DUMMY,
2848 SPI_MEM_OP_DATA_OUT(2, NULL, 0));
2850 spi_nor_setup_op(nor, &op, pp->proto);
2852 return spi_nor_check_op(nor, &op);
2856 * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
2857 * controller capabilities
2858 * @nor: pointer to a 'struct spi_nor'
2859 * @params: pointer to the 'struct spi_nor_flash_parameter'
2860 * representing SPI NOR flash capabilities
2861 * @hwcaps: pointer to resulting capabilities after adjusting
2862 * according to controller and flash's capability
2864 * Discard caps based on what the SPI controller actually supports (using
2865 * spi_mem_supports_op()).
2868 spi_nor_adjust_hwcaps(struct spi_nor *nor,
2869 const struct spi_nor_flash_parameter *params,
2875 * Start by assuming the controller supports every capability.
2876 * We will mask them after checking what's really supported
2877 * using spi_mem_supports_op().
2879 *hwcaps = SNOR_HWCAPS_ALL & params->hwcaps.mask;
2881 /* X-X-X modes are not supported yet, mask them all. */
2882 *hwcaps &= ~SNOR_HWCAPS_X_X_X;
2885 * If the reset line is broken, we do not want to enter a stateful
2888 if (nor->flags & SNOR_F_BROKEN_RESET)
2889 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
2891 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2894 if (!(*hwcaps & BIT(cap)))
2897 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2899 spi_nor_check_readop(nor, ¶ms->reads[rdidx]))
2900 *hwcaps &= ~BIT(cap);
2902 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2906 if (spi_nor_check_pp(nor, ¶ms->page_programs[ppidx]))
2907 *hwcaps &= ~BIT(cap);
2912 * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
2913 * controller capabilities
2914 * @nor: pointer to a 'struct spi_nor'
2915 * @params: pointer to the 'struct spi_nor_flash_parameter'
2916 * representing SPI NOR flash capabilities
2917 * @hwcaps: pointer to resulting capabilities after adjusting
2918 * according to controller and flash's capability
2920 * Select caps based on what the SPI controller and SPI flash both support.
2923 spi_nor_adjust_hwcaps(struct spi_nor *nor,
2924 const struct spi_nor_flash_parameter *params,
2927 struct spi_slave *spi = nor->spi;
2928 u32 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2929 SNOR_HWCAPS_READ_4_4_4 |
2930 SNOR_HWCAPS_READ_8_8_8 |
2931 SNOR_HWCAPS_PP_4_4_4 |
2932 SNOR_HWCAPS_PP_8_8_8);
2933 u32 spi_hwcaps = (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |
2936 /* Get the hardware capabilities the SPI controller supports. */
2937 if (spi->mode & SPI_RX_OCTAL) {
2938 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_8;
2940 if (spi->mode & SPI_TX_OCTAL)
2941 spi_hwcaps |= (SNOR_HWCAPS_READ_1_8_8 |
2942 SNOR_HWCAPS_PP_1_1_8 |
2943 SNOR_HWCAPS_PP_1_8_8);
2944 } else if (spi->mode & SPI_RX_QUAD) {
2945 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_4;
2947 if (spi->mode & SPI_TX_QUAD)
2948 spi_hwcaps |= (SNOR_HWCAPS_READ_1_4_4 |
2949 SNOR_HWCAPS_PP_1_1_4 |
2950 SNOR_HWCAPS_PP_1_4_4);
2951 } else if (spi->mode & SPI_RX_DUAL) {
2952 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_2;
2954 if (spi->mode & SPI_TX_DUAL)
2955 spi_hwcaps |= SNOR_HWCAPS_READ_1_2_2;
2959 * Keep only the hardware capabilities supported by both the SPI
2960 * controller and the SPI flash memory.
2962 *hwcaps = spi_hwcaps & params->hwcaps.mask;
2963 if (*hwcaps & ignored_mask) {
2965 "SPI n-n-n protocols are not supported yet.\n");
2966 *hwcaps &= ~ignored_mask;
2969 #endif /* CONFIG_SPI_FLASH_SMART_HWCAPS */
2971 static int spi_nor_select_read(struct spi_nor *nor,
2972 const struct spi_nor_flash_parameter *params,
2975 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2976 const struct spi_nor_read_command *read;
2981 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2985 read = ¶ms->reads[cmd];
2986 nor->read_opcode = read->opcode;
2987 nor->read_proto = read->proto;
2990 * In the spi-nor framework, we don't need to make the difference
2991 * between mode clock cycles and wait state clock cycles.
2992 * Indeed, the value of the mode clock cycles is used by a QSPI
2993 * flash memory to know whether it should enter or leave its 0-4-4
2994 * (Continuous Read / XIP) mode.
2995 * eXecution In Place is out of the scope of the mtd sub-system.
2996 * Hence we choose to merge both mode and wait state clock cycles
2997 * into the so called dummy clock cycles.
2999 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
3003 static int spi_nor_select_pp(struct spi_nor *nor,
3004 const struct spi_nor_flash_parameter *params,
3007 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
3008 const struct spi_nor_pp_command *pp;
3013 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
3017 pp = ¶ms->page_programs[cmd];
3018 nor->program_opcode = pp->opcode;
3019 nor->write_proto = pp->proto;
3023 static int spi_nor_select_erase(struct spi_nor *nor,
3024 const struct flash_info *info)
3026 struct mtd_info *mtd = &nor->mtd;
3028 /* Do nothing if already configured from SFDP. */
3032 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
3033 /* prefer "small sector" erase if possible */
3034 if (info->flags & SECT_4K) {
3035 nor->erase_opcode = SPINOR_OP_BE_4K;
3036 mtd->erasesize = 4096;
3037 } else if (info->flags & SECT_4K_PMC) {
3038 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
3039 mtd->erasesize = 4096;
3043 nor->erase_opcode = SPINOR_OP_SE;
3044 mtd->erasesize = info->sector_size;
3049 static int spi_nor_default_setup(struct spi_nor *nor,
3050 const struct flash_info *info,
3051 const struct spi_nor_flash_parameter *params)
3054 bool enable_quad_io;
3057 spi_nor_adjust_hwcaps(nor, params, &shared_mask);
3059 /* Select the (Fast) Read command. */
3060 err = spi_nor_select_read(nor, params, shared_mask);
3063 "can't select read settings supported by both the SPI controller and memory.\n");
3067 /* Select the Page Program command. */
3068 err = spi_nor_select_pp(nor, params, shared_mask);
3071 "can't select write settings supported by both the SPI controller and memory.\n");
3075 /* Select the Sector Erase command. */
3076 err = spi_nor_select_erase(nor, info);
3079 "can't select erase settings supported by both the SPI controller and memory.\n");
3083 /* Enable Quad I/O if needed. */
3084 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
3085 spi_nor_get_protocol_width(nor->write_proto) == 4);
3086 if (enable_quad_io && params->quad_enable)
3087 nor->quad_enable = params->quad_enable;
3089 nor->quad_enable = NULL;
3094 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
3095 const struct spi_nor_flash_parameter *params)
3100 return nor->setup(nor, info, params);
3103 #ifdef CONFIG_SPI_FLASH_SPANSION
3104 static int s25hx_t_mdp_ready(struct spi_nor *nor)
3109 for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
3110 ret = spansion_sr_ready(nor, addr, 0);
3118 static int s25hx_t_quad_enable(struct spi_nor *nor)
3123 for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
3124 ret = spansion_quad_enable_volatile(nor, addr, 0);
3132 static int s25hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
3134 /* Support 32 x 4KB sectors at bottom */
3135 return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0,
3139 static int s25hx_t_setup(struct spi_nor *nor, const struct flash_info *info,
3140 const struct spi_nor_flash_parameter *params)
3145 #ifdef CONFIG_SPI_FLASH_BAR
3146 return -ENOTSUPP; /* Bank Address Register is not supported */
3149 * Read CFR3V to check if uniform sector is selected. If not, assign an
3150 * erase hook that supports non-uniform erase.
3152 ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cfr3v);
3155 if (!(cfr3v & CFR3V_UNHYSA))
3156 nor->erase = s25hx_t_erase_non_uniform;
3159 * For the multi-die package parts, the ready() hook is needed to check
3160 * all dies' status via read any register.
3162 if (nor->mtd.size > SZ_128M)
3163 nor->ready = s25hx_t_mdp_ready;
3165 return spi_nor_default_setup(nor, info, params);
3168 static void s25hx_t_default_init(struct spi_nor *nor)
3170 nor->setup = s25hx_t_setup;
3173 static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
3174 const struct sfdp_parameter_header *header,
3175 const struct sfdp_bfpt *bfpt,
3176 struct spi_nor_flash_parameter *params)
3182 /* erase size in case it is set to 4K from BFPT */
3183 nor->erase_opcode = SPINOR_OP_SE_4B;
3184 nor->mtd.erasesize = nor->info->sector_size;
3186 ret = set_4byte(nor, nor->info, 1);
3189 nor->addr_width = 4;
3192 * The page_size is set to 512B from BFPT, but it actually depends on
3193 * the configuration register. Look up the CFR3V and determine the
3194 * page_size. For multi-die package parts, use 512B only when the all
3195 * dies are configured to 512B buffer.
3197 for (addr = 0; addr < params->size; addr += SZ_128M) {
3198 ret = spansion_read_any_reg(nor, addr + SPINOR_REG_ADDR_CFR3V,
3203 if (!(cfr3v & CFR3V_PGMBUF)) {
3204 params->page_size = 256;
3208 params->page_size = 512;
3213 static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor,
3214 struct spi_nor_flash_parameter *params)
3216 /* READ_FAST_4B (0Ch) requires mode cycles*/
3217 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
3218 /* PP_1_1_4 is not supported */
3219 params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
3220 /* Use volatile register to enable quad */
3221 params->quad_enable = s25hx_t_quad_enable;
3224 static struct spi_nor_fixups s25hx_t_fixups = {
3225 .default_init = s25hx_t_default_init,
3226 .post_bfpt = s25hx_t_post_bfpt_fixup,
3227 .post_sfdp = s25hx_t_post_sfdp_fixup,
3230 static int s25fl256l_setup(struct spi_nor *nor, const struct flash_info *info,
3231 const struct spi_nor_flash_parameter *params)
3233 return -ENOTSUPP; /* Bank Address Register is not supported */
3236 static void s25fl256l_default_init(struct spi_nor *nor)
3238 nor->setup = s25fl256l_setup;
3241 static struct spi_nor_fixups s25fl256l_fixups = {
3242 .default_init = s25fl256l_default_init,
3246 #ifdef CONFIG_SPI_FLASH_S28HS512T
3248 * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
3249 * @nor: pointer to a 'struct spi_nor'
3251 * This also sets the memory access latency cycles to 24 to allow the flash to
3252 * run at up to 200MHz.
3254 * Return: 0 on success, -errno otherwise.
3256 static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
3258 struct spi_mem_op op;
3263 /* Use 24 dummy cycles for memory array reads. */
3264 ret = write_enable(nor);
3268 buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
3269 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
3270 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1),
3271 SPI_MEM_OP_NO_DUMMY,
3272 SPI_MEM_OP_DATA_OUT(1, &buf, 1));
3273 ret = spi_mem_exec_op(nor->spi, &op);
3276 "failed to set default memory latency value: %d\n",
3280 ret = spi_nor_wait_till_ready(nor);
3284 nor->read_dummy = 24;
3286 /* Set the octal and DTR enable bits. */
3287 ret = write_enable(nor);
3291 buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
3292 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
3293 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1),
3294 SPI_MEM_OP_NO_DUMMY,
3295 SPI_MEM_OP_DATA_OUT(1, &buf, 1));
3296 ret = spi_mem_exec_op(nor->spi, &op);
3298 dev_warn(nor->dev, "Failed to enable octal DTR mode\n");
3305 static int s28hs512t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
3307 /* Factory default configuration: 32 x 4 KiB sectors at bottom. */
3308 return spansion_erase_non_uniform(nor, addr, SPINOR_OP_S28_SE_4K,
3312 static int s28hs512t_setup(struct spi_nor *nor, const struct flash_info *info,
3313 const struct spi_nor_flash_parameter *params)
3315 struct spi_mem_op op;
3320 ret = spi_nor_wait_till_ready(nor);
3325 * Check CFR3V to check if non-uniform sector mode is selected. If it
3326 * is, set the erase hook to the non-uniform erase procedure.
3328 op = (struct spi_mem_op)
3329 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
3330 SPI_MEM_OP_ADDR(addr_width,
3331 SPINOR_REG_CYPRESS_CFR3V, 1),
3332 SPI_MEM_OP_NO_DUMMY,
3333 SPI_MEM_OP_DATA_IN(1, &buf, 1));
3335 ret = spi_mem_exec_op(nor->spi, &op);
3339 if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT))
3340 nor->erase = s28hs512t_erase_non_uniform;
3342 return spi_nor_default_setup(nor, info, params);
3345 static void s28hs512t_default_init(struct spi_nor *nor)
3347 nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
3348 nor->setup = s28hs512t_setup;
3351 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor,
3352 struct spi_nor_flash_parameter *params)
3355 * On older versions of the flash the xSPI Profile 1.0 table has the
3356 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
3358 if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
3359 params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
3360 SPINOR_OP_CYPRESS_RD_FAST;
3362 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
3364 /* This flash is also missing the 4-byte Page Program opcode bit. */
3365 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
3366 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
3368 * Since xSPI Page Program opcode is backward compatible with
3369 * Legacy SPI, use Legacy SPI opcode there as well.
3371 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
3372 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
3375 * The xSPI Profile 1.0 table advertises the number of additional
3376 * address bytes needed for Read Status Register command as 0 but the
3377 * actual value for that is 4.
3379 params->rdsr_addr_nbytes = 4;
3382 static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
3383 const struct sfdp_parameter_header *bfpt_header,
3384 const struct sfdp_bfpt *bfpt,
3385 struct spi_nor_flash_parameter *params)
3387 struct spi_mem_op op;
3393 * The BFPT table advertises a 512B page size but the page size is
3394 * actually configurable (with the default being 256B). Read from
3395 * CFR3V[4] and set the correct size.
3397 op = (struct spi_mem_op)
3398 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
3399 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR3V, 1),
3400 SPI_MEM_OP_NO_DUMMY,
3401 SPI_MEM_OP_DATA_IN(1, &buf, 1));
3402 ret = spi_mem_exec_op(nor->spi, &op);
3406 if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
3407 params->page_size = 512;
3409 params->page_size = 256;
3412 * The BFPT advertises that it supports 4k erases, and the datasheet
3413 * says the same. But 4k erases did not work when testing. So, use 256k
3416 nor->erase_opcode = SPINOR_OP_SE_4B;
3417 nor->mtd.erasesize = 0x40000;
3422 static struct spi_nor_fixups s28hs512t_fixups = {
3423 .default_init = s28hs512t_default_init,
3424 .post_sfdp = s28hs512t_post_sfdp_fixup,
3425 .post_bfpt = s28hs512t_post_bfpt_fixup,
3427 #endif /* CONFIG_SPI_FLASH_S28HS512T */
3429 #ifdef CONFIG_SPI_FLASH_MT35XU
3430 static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
3432 struct spi_mem_op op;
3437 /* Set dummy cycles for Fast Read to the default of 20. */
3438 ret = write_enable(nor);
3443 op = (struct spi_mem_op)
3444 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
3445 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR1V, 1),
3446 SPI_MEM_OP_NO_DUMMY,
3447 SPI_MEM_OP_DATA_OUT(1, &buf, 1));
3448 ret = spi_mem_exec_op(nor->spi, &op);
3452 ret = spi_nor_wait_till_ready(nor);
3456 nor->read_dummy = 20;
3458 ret = write_enable(nor);
3462 buf = SPINOR_MT_OCT_DTR;
3463 op = (struct spi_mem_op)
3464 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
3465 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR0V, 1),
3466 SPI_MEM_OP_NO_DUMMY,
3467 SPI_MEM_OP_DATA_OUT(1, &buf, 1));
3468 ret = spi_mem_exec_op(nor->spi, &op);
3470 dev_err(nor->dev, "Failed to enable octal DTR mode\n");
3477 static void mt35xu512aba_default_init(struct spi_nor *nor)
3479 nor->octal_dtr_enable = spi_nor_micron_octal_dtr_enable;
3482 static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor,
3483 struct spi_nor_flash_parameter *params)
3485 /* Set the Fast Read settings. */
3486 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
3487 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
3488 0, 20, SPINOR_OP_MT_DTR_RD,
3489 SNOR_PROTO_8_8_8_DTR);
3491 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
3493 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
3494 params->rdsr_dummy = 8;
3495 params->rdsr_addr_nbytes = 0;
3498 * The BFPT quad enable field is set to a reserved value so the quad
3499 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
3502 params->quad_enable = NULL;
3505 static struct spi_nor_fixups mt35xu512aba_fixups = {
3506 .default_init = mt35xu512aba_default_init,
3507 .post_sfdp = mt35xu512aba_post_sfdp_fixup,
3509 #endif /* CONFIG_SPI_FLASH_MT35XU */
3511 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
3512 * @nor: pointer to a 'struct spi_nor'
3514 * Return: 0 on success, -errno otherwise.
3516 static int spi_nor_octal_dtr_enable(struct spi_nor *nor)
3520 if (!nor->octal_dtr_enable)
3523 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
3524 nor->write_proto == SNOR_PROTO_8_8_8_DTR))
3527 ret = nor->octal_dtr_enable(nor);
3531 nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
3536 static int spi_nor_init(struct spi_nor *nor)
3540 err = spi_nor_octal_dtr_enable(nor);
3542 dev_dbg(nor->dev, "Octal DTR mode not supported\n");
3547 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
3548 * with the software protection bits set
3550 if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) &&
3551 (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
3552 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
3553 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
3554 nor->info->flags & SPI_NOR_HAS_LOCK)) {
3557 spi_nor_wait_till_ready(nor);
3560 if (nor->quad_enable) {
3561 err = nor->quad_enable(nor);
3563 dev_dbg(nor->dev, "quad mode not supported\n");
3568 if (nor->addr_width == 4 &&
3569 !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) &&
3570 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
3571 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
3573 * If the RESET# pin isn't hooked up properly, or the system
3574 * otherwise doesn't perform a reset command in the boot
3575 * sequence, it's impossible to 100% protect against unexpected
3576 * reboots (e.g., crashes). Warn the user (or hopefully, system
3577 * designer) that this is bad.
3579 if (nor->flags & SNOR_F_BROKEN_RESET)
3580 debug("enabling reset hack; may not recover from unexpected reboots\n");
3581 set_4byte(nor, nor->info, 1);
3587 #ifdef CONFIG_SPI_FLASH_SOFT_RESET
3589 * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence
3590 * @nor: the spi_nor structure
3592 * This function can be used to switch from Octal DTR mode to legacy mode on a
3593 * flash that supports it. The soft reset is executed in Octal DTR mode.
3595 * Return: 0 for success, -errno for failure.
3597 static int spi_nor_soft_reset(struct spi_nor *nor)
3599 struct spi_mem_op op;
3601 enum spi_nor_cmd_ext ext;
3603 ext = nor->cmd_ext_type;
3604 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
3606 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
3607 SPI_MEM_OP_NO_DUMMY,
3609 SPI_MEM_OP_NO_DATA);
3610 spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
3611 ret = spi_mem_exec_op(nor->spi, &op);
3613 dev_warn(nor->dev, "Software reset enable failed: %d\n", ret);
3617 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0),
3618 SPI_MEM_OP_NO_DUMMY,
3620 SPI_MEM_OP_NO_DATA);
3621 spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
3622 ret = spi_mem_exec_op(nor->spi, &op);
3624 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
3629 * Software Reset is not instant, and the delay varies from flash to
3630 * flash. Looking at a few flashes, most range somewhere below 100
3631 * microseconds. So, wait for 200ms just to be sure.
3633 udelay(SPI_NOR_SRST_SLEEP_LEN);
3636 nor->cmd_ext_type = ext;
3639 #endif /* CONFIG_SPI_FLASH_SOFT_RESET */
3641 int spi_nor_remove(struct spi_nor *nor)
3643 #ifdef CONFIG_SPI_FLASH_SOFT_RESET
3644 if (nor->info->flags & SPI_NOR_OCTAL_DTR_READ &&
3645 nor->flags & SNOR_F_SOFT_RESET)
3646 return spi_nor_soft_reset(nor);
3652 void spi_nor_set_fixups(struct spi_nor *nor)
3654 #ifdef CONFIG_SPI_FLASH_SPANSION
3655 if (JEDEC_MFR(nor->info) == SNOR_MFR_CYPRESS) {
3656 switch (nor->info->id[1]) {
3657 case 0x2a: /* S25HL (QSPI, 3.3V) */
3658 case 0x2b: /* S25HS (QSPI, 1.8V) */
3659 nor->fixups = &s25hx_t_fixups;
3667 if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) &&
3668 !strcmp(nor->info->name, "s25fl256l"))
3669 nor->fixups = &s25fl256l_fixups;
3672 #ifdef CONFIG_SPI_FLASH_S28HS512T
3673 if (!strcmp(nor->info->name, "s28hs512t"))
3674 nor->fixups = &s28hs512t_fixups;
3677 #ifdef CONFIG_SPI_FLASH_MT35XU
3678 if (!strcmp(nor->info->name, "mt35xu512aba"))
3679 nor->fixups = &mt35xu512aba_fixups;
3683 int spi_nor_scan(struct spi_nor *nor)
3685 struct spi_nor_flash_parameter params;
3686 const struct flash_info *info = NULL;
3687 struct mtd_info *mtd = &nor->mtd;
3688 struct spi_slave *spi = nor->spi;
3692 #ifdef CONFIG_SYS_MAX_FLASH_BANKS
3693 cfi_mtd_nb = CONFIG_SYS_MAX_FLASH_BANKS;
3696 /* Reset SPI protocol for all commands. */
3697 nor->reg_proto = SNOR_PROTO_1_1_1;
3698 nor->read_proto = SNOR_PROTO_1_1_1;
3699 nor->write_proto = SNOR_PROTO_1_1_1;
3700 nor->read = spi_nor_read_data;
3701 nor->write = spi_nor_write_data;
3702 nor->read_reg = spi_nor_read_reg;
3703 nor->write_reg = spi_nor_write_reg;
3705 nor->setup = spi_nor_default_setup;
3707 #ifdef CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT
3709 * When the flash is handed to us in a stateful mode like 8D-8D-8D, it
3710 * is difficult to detect the mode the flash is in. One option is to
3711 * read SFDP in all modes and see which one gives the correct "SFDP"
3712 * signature, but not all flashes support SFDP in 8D-8D-8D mode.
3714 * Further, even if you detect the mode of the flash via SFDP, you
3715 * still have the problem of actually reading the ID. The Read ID
3716 * command is not standardized across flash vendors. Flashes can have
3717 * different dummy cycles needed for reading the ID. Some flashes even
3718 * expect a 4-byte dummy address with the Read ID command. All this
3719 * information cannot be obtained from the SFDP table.
3721 * So, perform a Software Reset sequence before reading the ID and
3722 * initializing the flash. A Soft Reset will bring back the flash in
3723 * its default protocol mode assuming no non-volatile configuration was
3724 * set. This will let us detect the flash even if ROM hands it to us in
3727 * To accommodate cases where there is more than one flash on a board,
3728 * and only one of them needs a soft reset, failure to reset is not
3729 * made fatal, and we still try to read ID if possible.
3731 spi_nor_soft_reset(nor);
3732 #endif /* CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT */
3734 info = spi_nor_read_id(nor);
3735 if (IS_ERR_OR_NULL(info))
3739 spi_nor_set_fixups(nor);
3741 /* Parse the Serial Flash Discoverable Parameters table. */
3742 ret = spi_nor_init_params(nor, info, ¶ms);
3747 sprintf(nor->mtd_name, "%s%d",
3748 MTD_DEV_TYPE(MTD_DEV_TYPE_NOR),
3749 cfi_mtd_nb + dev_seq(nor->dev));
3750 mtd->name = nor->mtd_name;
3752 mtd->dev = nor->dev;
3754 mtd->type = MTD_NORFLASH;
3756 mtd->flags = MTD_CAP_NORFLASH;
3757 mtd->size = params.size;
3758 mtd->_erase = spi_nor_erase;
3759 mtd->_read = spi_nor_read;
3760 mtd->_write = spi_nor_write;
3762 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
3763 /* NOR protection support for STmicro/Micron chips and similar */
3764 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
3765 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
3766 JEDEC_MFR(info) == SNOR_MFR_SST ||
3767 info->flags & SPI_NOR_HAS_LOCK) {
3768 nor->flash_lock = stm_lock;
3769 nor->flash_unlock = stm_unlock;
3770 nor->flash_is_locked = stm_is_locked;
3774 #ifdef CONFIG_SPI_FLASH_SST
3776 * sst26 series block protection implementation differs from other
3779 if (info->flags & SPI_NOR_HAS_SST26LOCK) {
3780 nor->flash_lock = sst26_lock;
3781 nor->flash_unlock = sst26_unlock;
3782 nor->flash_is_locked = sst26_is_locked;
3786 if (info->flags & USE_FSR)
3787 nor->flags |= SNOR_F_USE_FSR;
3788 if (info->flags & SPI_NOR_HAS_TB)
3789 nor->flags |= SNOR_F_HAS_SR_TB;
3790 if (info->flags & NO_CHIP_ERASE)
3791 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
3792 if (info->flags & USE_CLSR)
3793 nor->flags |= SNOR_F_USE_CLSR;
3795 if (info->flags & SPI_NOR_NO_ERASE)
3796 mtd->flags |= MTD_NO_ERASE;
3798 nor->page_size = params.page_size;
3799 mtd->writebufsize = nor->page_size;
3801 /* Some devices cannot do fast-read, no matter what DT tells us */
3802 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
3803 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
3806 * Configure the SPI memory:
3807 * - select op codes for (Fast) Read, Page Program and Sector Erase.
3808 * - set the number of dummy cycles (mode cycles + wait states).
3809 * - set the SPI protocols for register and memory accesses.
3810 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
3812 ret = spi_nor_setup(nor, info, ¶ms);
3816 if (spi_nor_protocol_is_dtr(nor->read_proto)) {
3817 /* Always use 4-byte addresses in DTR mode. */
3818 nor->addr_width = 4;
3819 } else if (nor->addr_width) {
3820 /* already configured from SFDP */
3821 } else if (info->addr_width) {
3822 nor->addr_width = info->addr_width;
3824 nor->addr_width = 3;
3827 if (nor->addr_width == 3 && mtd->size > SZ_16M) {
3828 #ifndef CONFIG_SPI_FLASH_BAR
3829 /* enable 4-byte addressing if the device exceeds 16MiB */
3830 nor->addr_width = 4;
3831 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
3832 info->flags & SPI_NOR_4B_OPCODES)
3833 spi_nor_set_4byte_opcodes(nor, info);
3835 /* Configure the BAR - discover bank cmds and read current bank */
3836 nor->addr_width = 3;
3837 ret = read_bar(nor, info);
3843 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
3844 dev_dbg(nor->dev, "address width is too large: %u\n",
3849 /* Send all the required SPI flash commands to initialize device */
3850 ret = spi_nor_init(nor);
3854 nor->rdsr_dummy = params.rdsr_dummy;
3855 nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes;
3856 nor->name = info->name;
3857 nor->size = mtd->size;
3858 nor->erase_size = mtd->erasesize;
3859 nor->sector_size = mtd->erasesize;
3861 #ifndef CONFIG_SPL_BUILD
3862 printf("SF: Detected %s with page size ", nor->name);
3863 print_size(nor->page_size, ", erase size ");
3864 print_size(nor->erase_size, ", total ");
3865 print_size(nor->size, "");
3872 /* U-Boot specific functions, need to extend MTD to support these */
3873 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
3875 int sr = read_sr(nor);
3880 return (sr >> 2) & 7;