1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/log2.h>
16 #include <linux/math64.h>
17 #include <linux/sizes.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/spi-nor.h>
24 /* Define max times to check status register before we give up. */
27 * For everything but full-chip erase; probably could be much smaller, but kept
28 * around for safety for now
31 #define HZ CONFIG_SYS_HZ
33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
35 #define SPI_NOR_MAX_ID_LEN 6
36 #define SPI_NOR_MAX_ADDR_WIDTH 4
42 * This array stores the ID bytes.
43 * The first three bytes are the JEDIC ID.
44 * JEDEC ID zero means "no ID" (mostly older chips).
46 u8 id[SPI_NOR_MAX_ID_LEN];
49 /* The size listed here is what works with SPINOR_OP_SE, which isn't
50 * necessarily called a "sector" by the vendor.
52 unsigned int sector_size;
59 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
60 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
61 #define SST_WRITE BIT(2) /* use SST byte programming */
62 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
63 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
64 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
65 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
66 #define USE_FSR BIT(7) /* use flag status register */
67 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
68 #define SPI_NOR_HAS_TB BIT(9) /*
69 * Flash SR has Top/Bottom (TB) protect
70 * bit. Must be used with
73 #define SPI_S3AN BIT(10) /*
74 * Xilinx Spartan 3AN In-System Flash
75 * (MFR cannot be used for probing
76 * because it has the same value as
79 #define SPI_NOR_4B_OPCODES BIT(11) /*
80 * Use dedicated 4byte address op codes
81 * to support memory size above 128Mib.
83 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
84 #define USE_CLSR BIT(14) /* use CLSR command */
86 int (*quad_enable)(struct spi_nor *nor);
89 #define JEDEC_MFR(info) ((info)->id[0])
91 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
94 if (op->data.dir == SPI_MEM_DATA_IN)
95 op->data.buf.in = buf;
97 op->data.buf.out = buf;
98 return spi_mem_exec_op(nor->spi, op);
101 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
103 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
106 SPI_MEM_OP_DATA_IN(len, NULL, 1));
109 ret = spi_nor_read_write_reg(nor, &op, val);
111 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
117 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
119 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
122 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
124 return spi_nor_read_write_reg(nor, &op, buf);
127 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
130 struct spi_mem_op op =
131 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
132 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
133 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
134 SPI_MEM_OP_DATA_IN(len, buf, 1));
135 size_t remaining = len;
138 /* get transfer protocols. */
139 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
140 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
141 op.dummy.buswidth = op.addr.buswidth;
142 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
144 /* convert the dummy cycles to the number of bytes */
145 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
148 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
149 ret = spi_mem_adjust_op_size(nor->spi, &op);
153 ret = spi_mem_exec_op(nor->spi, &op);
157 op.addr.val += op.data.nbytes;
158 remaining -= op.data.nbytes;
159 op.data.buf.in += op.data.nbytes;
165 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
168 struct spi_mem_op op =
169 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
170 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
172 SPI_MEM_OP_DATA_OUT(len, buf, 1));
173 size_t remaining = len;
176 /* get transfer protocols. */
177 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
178 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
179 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
181 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
185 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
186 ret = spi_mem_adjust_op_size(nor->spi, &op);
190 ret = spi_mem_exec_op(nor->spi, &op);
194 op.addr.val += op.data.nbytes;
195 remaining -= op.data.nbytes;
196 op.data.buf.out += op.data.nbytes;
203 * Read the status register, returning its value in the location
204 * Return the status register value.
205 * Returns negative if error occurred.
207 static int read_sr(struct spi_nor *nor)
212 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
214 pr_debug("error %d reading SR\n", (int)ret);
222 * Read the flag status register, returning its value in the location
223 * Return the status register value.
224 * Returns negative if error occurred.
226 static int read_fsr(struct spi_nor *nor)
231 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
233 pr_debug("error %d reading FSR\n", ret);
241 * Read configuration register, returning its value in the
242 * location. Return the configuration register value.
243 * Returns negative if error occurred.
245 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
246 static int read_cr(struct spi_nor *nor)
251 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
253 dev_dbg(nor->dev, "error %d reading CR\n", ret);
262 * Write status register 1 byte
263 * Returns negative if error occurred.
265 static int write_sr(struct spi_nor *nor, u8 val)
267 nor->cmd_buf[0] = val;
268 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
272 * Set write enable latch with Write Enable command.
273 * Returns negative if error occurred.
275 static int write_enable(struct spi_nor *nor)
277 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
281 * Send write disable instruction to the chip.
283 static int write_disable(struct spi_nor *nor)
285 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
288 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
293 static int spi_nor_sr_ready(struct spi_nor *nor)
295 int sr = read_sr(nor);
300 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
302 dev_dbg(nor->dev, "Erase Error occurred\n");
304 dev_dbg(nor->dev, "Programming Error occurred\n");
306 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
310 return !(sr & SR_WIP);
313 static int spi_nor_fsr_ready(struct spi_nor *nor)
315 int fsr = read_fsr(nor);
320 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
322 dev_dbg(nor->dev, "Erase operation failed.\n");
324 dev_dbg(nor->dev, "Program operation failed.\n");
326 if (fsr & FSR_PT_ERR)
328 "Attempted to modify a protected sector.\n");
330 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
334 return fsr & FSR_READY;
337 static int spi_nor_ready(struct spi_nor *nor)
341 sr = spi_nor_sr_ready(nor);
344 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
351 * Service routine to read status register until ready, or timeout occurs.
352 * Returns non-zero if error.
354 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
355 unsigned long timeout)
357 unsigned long timebase;
360 timebase = get_timer(0);
362 while (get_timer(timebase) < timeout) {
363 ret = spi_nor_ready(nor);
370 dev_err(nor->dev, "flash operation timed out\n");
375 static int spi_nor_wait_till_ready(struct spi_nor *nor)
377 return spi_nor_wait_till_ready_with_timeout(nor,
378 DEFAULT_READY_WAIT_JIFFIES);
382 * Initiate the erasure of a single sector
384 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
386 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
390 return nor->erase(nor, addr);
393 * Default implementation, if driver doesn't have a specialized HW
396 for (i = nor->addr_width - 1; i >= 0; i--) {
397 buf[i] = addr & 0xff;
401 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
405 * Erase an address range on the nor chip. The address range may extend
406 * one or more erase sectors. Return an error is there is a problem erasing.
408 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
410 struct spi_nor *nor = mtd_to_spi_nor(mtd);
414 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
415 (long long)instr->len);
417 div_u64_rem(instr->len, mtd->erasesize, &rem);
427 ret = spi_nor_erase_sector(nor, addr);
431 addr += mtd->erasesize;
432 len -= mtd->erasesize;
434 ret = spi_nor_wait_till_ready(nor);
445 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
446 /* Write status register and ensure bits in mask match written values */
447 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
452 ret = write_sr(nor, status_new);
456 ret = spi_nor_wait_till_ready(nor);
464 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
467 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
470 struct mtd_info *mtd = &nor->mtd;
471 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
472 int shift = ffs(mask) - 1;
480 pow = ((sr & mask) ^ mask) >> shift;
481 *len = mtd->size >> pow;
482 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
485 *ofs = mtd->size - *len;
490 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
491 * @locked is false); 0 otherwise
493 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
502 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
505 /* Requested range is a sub-range of locked range */
506 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
508 /* Requested range does not overlap with locked range */
509 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
512 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
515 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
518 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
521 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
525 * Lock a region of the flash. Compatible with ST Micro and similar flash.
526 * Supports the block protection bits BP{0,1,2} in the status register
527 * (SR). Does not support these features found in newer SR bitfields:
528 * - SEC: sector/block protect - only handle SEC=0 (block protect)
529 * - CMP: complement protect - only support CMP=0 (range is not complemented)
531 * Support for the following is provided conditionally for some flash:
532 * - TB: top/bottom protect
534 * Sample table portion for 8MB flash (Winbond w25q64fw):
536 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
537 * --------------------------------------------------------------------------
538 * X | X | 0 | 0 | 0 | NONE | NONE
539 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
540 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
541 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
542 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
543 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
544 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
545 * X | X | 1 | 1 | 1 | 8 MB | ALL
546 * ------|-------|-------|-------|-------|---------------|-------------------
547 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
548 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
549 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
550 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
551 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
552 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
554 * Returns negative on errors, 0 on success.
556 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
558 struct mtd_info *mtd = &nor->mtd;
559 int status_old, status_new;
560 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
561 u8 shift = ffs(mask) - 1, pow, val;
563 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
566 status_old = read_sr(nor);
570 /* If nothing in our range is unlocked, we don't need to do anything */
571 if (stm_is_locked_sr(nor, ofs, len, status_old))
574 /* If anything below us is unlocked, we can't use 'bottom' protection */
575 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
576 can_be_bottom = false;
578 /* If anything above us is unlocked, we can't use 'top' protection */
579 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
583 if (!can_be_bottom && !can_be_top)
586 /* Prefer top, if both are valid */
587 use_top = can_be_top;
589 /* lock_len: length of region that should end up locked */
591 lock_len = mtd->size - ofs;
593 lock_len = ofs + len;
596 * Need smallest pow such that:
598 * 1 / (2^pow) <= (len / size)
600 * so (assuming power-of-2 size) we do:
602 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
604 pow = ilog2(mtd->size) - ilog2(lock_len);
605 val = mask - (pow << shift);
608 /* Don't "lock" with no region! */
612 status_new = (status_old & ~mask & ~SR_TB) | val;
614 /* Disallow further writes if WP pin is asserted */
615 status_new |= SR_SRWD;
620 /* Don't bother if they're the same */
621 if (status_new == status_old)
624 /* Only modify protection if it will not unlock other areas */
625 if ((status_new & mask) < (status_old & mask))
628 return write_sr_and_check(nor, status_new, mask);
632 * Unlock a region of the flash. See stm_lock() for more info
634 * Returns negative on errors, 0 on success.
636 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
638 struct mtd_info *mtd = &nor->mtd;
639 int status_old, status_new;
640 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
641 u8 shift = ffs(mask) - 1, pow, val;
643 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
646 status_old = read_sr(nor);
650 /* If nothing in our range is locked, we don't need to do anything */
651 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
654 /* If anything below us is locked, we can't use 'top' protection */
655 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
658 /* If anything above us is locked, we can't use 'bottom' protection */
659 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
661 can_be_bottom = false;
663 if (!can_be_bottom && !can_be_top)
666 /* Prefer top, if both are valid */
667 use_top = can_be_top;
669 /* lock_len: length of region that should remain locked */
671 lock_len = mtd->size - (ofs + len);
676 * Need largest pow such that:
678 * 1 / (2^pow) >= (len / size)
680 * so (assuming power-of-2 size) we do:
682 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
684 pow = ilog2(mtd->size) - order_base_2(lock_len);
686 val = 0; /* fully unlocked */
688 val = mask - (pow << shift);
689 /* Some power-of-two sizes are not supported */
694 status_new = (status_old & ~mask & ~SR_TB) | val;
696 /* Don't protect status register if we're fully unlocked */
698 status_new &= ~SR_SRWD;
703 /* Don't bother if they're the same */
704 if (status_new == status_old)
707 /* Only modify protection if it will not lock other areas */
708 if ((status_new & mask) > (status_old & mask))
711 return write_sr_and_check(nor, status_new, mask);
715 * Check if a region of the flash is (completely) locked. See stm_lock() for
718 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
719 * negative on errors.
721 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
725 status = read_sr(nor);
729 return stm_is_locked_sr(nor, ofs, len, status);
731 #endif /* CONFIG_SPI_FLASH_STMICRO */
733 /* Used when the "_ext_id" is two bytes at most */
734 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
736 ((_jedec_id) >> 16) & 0xff, \
737 ((_jedec_id) >> 8) & 0xff, \
738 (_jedec_id) & 0xff, \
739 ((_ext_id) >> 8) & 0xff, \
742 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
743 .sector_size = (_sector_size), \
744 .n_sectors = (_n_sectors), \
748 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
750 ((_jedec_id) >> 16) & 0xff, \
751 ((_jedec_id) >> 8) & 0xff, \
752 (_jedec_id) & 0xff, \
753 ((_ext_id) >> 16) & 0xff, \
754 ((_ext_id) >> 8) & 0xff, \
758 .sector_size = (_sector_size), \
759 .n_sectors = (_n_sectors), \
763 /* NOTE: double check command sets and memory organization when you add
764 * more nor chips. This current list focusses on newer chips, which
765 * have been converging on command sets which including JEDEC ID.
767 * All newly added entries should describe *hardware* and should use SECT_4K
768 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
769 * scenarios excluding small sectors there is config option that can be
770 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
771 * For historical (and compatibility) reasons (before we got above config) some
772 * old entries may be missing 4K flag.
774 const struct flash_info spi_nor_ids[] = {
775 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
776 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
777 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
778 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
780 { "at45db011d", INFO(0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
781 { "at45db021d", INFO(0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
782 { "at45db041d", INFO(0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
783 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
784 { "at45db161d", INFO(0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
785 { "at45db321d", INFO(0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
786 { "at45db641d", INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
787 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
789 #ifdef CONFIG_SPI_FLASH_EON /* EON */
791 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
792 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
793 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
794 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
796 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
799 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
800 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
801 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
804 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
805 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
806 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
809 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
810 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
811 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
814 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
815 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
816 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
819 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
821 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
822 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
823 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 0) },
824 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 0) },
825 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
826 SECT_4K | SPI_NOR_DUAL_READ) },
827 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
828 SECT_4K | SPI_NOR_DUAL_READ) },
829 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
830 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
831 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
832 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
833 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
834 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
836 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
838 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
839 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
840 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
841 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
842 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
843 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
844 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
845 { "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32, SECT_4K) },
846 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
847 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
848 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
849 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
850 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
851 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
852 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
853 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
854 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
855 { "mx25l1633e", INFO(0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
858 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
860 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
861 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
862 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
863 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
864 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
865 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
866 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
867 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
868 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
869 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
870 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
871 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
872 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
873 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
875 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
876 /* Spansion/Cypress -- single (large) sector size only, at least
877 * for the chips listed here (without boot sectors).
879 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
880 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
881 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
882 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
883 { "s25fl512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
884 { "s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
885 { "s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
886 { "s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
887 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
888 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
889 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
890 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
891 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
892 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
893 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
894 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
895 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
896 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
897 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
898 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
899 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
901 #ifdef CONFIG_SPI_FLASH_SST /* SST */
902 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
903 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
904 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
905 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
906 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
907 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
908 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
909 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
910 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
911 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
912 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
913 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
914 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
915 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
916 { "sst26wf016", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K) },
917 { "sst26wf032", INFO(0xbf2622, 0, 64 * 1024, 64, SECT_4K) },
918 { "sst26wf064", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) },
920 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
921 /* ST Microelectronics -- newer production may have feature updates */
922 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
923 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
924 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
925 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
926 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
927 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
928 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
929 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
930 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
931 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
932 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
934 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
935 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
936 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
937 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
938 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
939 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
940 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
941 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
943 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
944 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
945 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
947 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
948 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
949 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
950 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
951 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
953 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
954 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
955 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
958 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
959 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
960 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
962 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
963 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
965 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
966 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
967 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
970 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
971 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
972 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
974 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
975 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
976 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
977 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
978 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
979 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
981 #ifdef CONFIG_SPI_FLASH_XMC
982 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
983 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
984 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
989 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
992 u8 id[SPI_NOR_MAX_ID_LEN];
993 const struct flash_info *info;
995 if (!ARRAY_SIZE(spi_nor_ids))
996 return ERR_PTR(-ENODEV);
998 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1000 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1001 return ERR_PTR(tmp);
1004 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1005 info = &spi_nor_ids[tmp];
1007 if (!memcmp(info->id, id, info->id_len))
1008 return &spi_nor_ids[tmp];
1011 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1012 id[0], id[1], id[2]);
1013 return ERR_PTR(-ENODEV);
1016 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1017 size_t *retlen, u_char *buf)
1019 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1022 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1027 ret = nor->read(nor, addr, len, buf);
1029 /* We shouldn't see 0-length reads */
1047 #ifdef CONFIG_SPI_FLASH_SST
1048 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1049 size_t *retlen, const u_char *buf)
1051 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1055 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1059 nor->sst_write_second = false;
1062 /* Start write from odd address. */
1064 nor->program_opcode = SPINOR_OP_BP;
1066 /* write one byte. */
1067 ret = nor->write(nor, to, 1, buf);
1070 ret = spi_nor_wait_till_ready(nor);
1076 /* Write out most of the data here. */
1077 for (; actual < len - 1; actual += 2) {
1078 nor->program_opcode = SPINOR_OP_AAI_WP;
1080 /* write two bytes. */
1081 ret = nor->write(nor, to, 2, buf + actual);
1084 ret = spi_nor_wait_till_ready(nor);
1088 nor->sst_write_second = true;
1090 nor->sst_write_second = false;
1093 ret = spi_nor_wait_till_ready(nor);
1097 /* Write out trailing byte if it exists. */
1098 if (actual != len) {
1101 nor->program_opcode = SPINOR_OP_BP;
1102 ret = nor->write(nor, to, 1, buf + actual);
1105 ret = spi_nor_wait_till_ready(nor);
1117 * Write an address range to the nor chip. Data must be written in
1118 * FLASH_PAGESIZE chunks. The address range may be any size provided
1119 * it is within the physical boundaries.
1121 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1122 size_t *retlen, const u_char *buf)
1124 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1125 size_t page_offset, page_remain, i;
1128 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1130 for (i = 0; i < len; ) {
1132 loff_t addr = to + i;
1135 * If page_size is a power of two, the offset can be quickly
1136 * calculated with an AND operation. On the other cases we
1137 * need to do a modulus operation (more expensive).
1138 * Power of two numbers have only one bit set and we can use
1139 * the instruction hweight32 to detect if we need to do a
1140 * modulus (do_div()) or not.
1142 if (hweight32(nor->page_size) == 1) {
1143 page_offset = addr & (nor->page_size - 1);
1147 page_offset = do_div(aux, nor->page_size);
1149 /* the size of data remaining on the first page */
1150 page_remain = min_t(size_t,
1151 nor->page_size - page_offset, len - i);
1154 ret = nor->write(nor, addr, page_remain, buf + i);
1159 ret = spi_nor_wait_till_ready(nor);
1164 if (written != page_remain) {
1174 #ifdef CONFIG_SPI_FLASH_MACRONIX
1176 * macronix_quad_enable() - set QE bit in Status Register.
1177 * @nor: pointer to a 'struct spi_nor'
1179 * Set the Quad Enable (QE) bit in the Status Register.
1181 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1183 * Return: 0 on success, -errno otherwise.
1185 static int macronix_quad_enable(struct spi_nor *nor)
1192 if (val & SR_QUAD_EN_MX)
1197 write_sr(nor, val | SR_QUAD_EN_MX);
1199 ret = spi_nor_wait_till_ready(nor);
1204 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1205 dev_err(nor->dev, "Macronix Quad bit not set\n");
1213 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1215 * Write status Register and configuration register with 2 bytes
1216 * The first byte will be written to the status register, while the
1217 * second byte will be written to the configuration register.
1218 * Return negative if error occurred.
1220 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1226 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1229 "error while writing configuration register\n");
1233 ret = spi_nor_wait_till_ready(nor);
1236 "timeout while writing configuration register\n");
1244 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1245 * @nor: pointer to a 'struct spi_nor'
1247 * Set the Quad Enable (QE) bit in the Configuration Register.
1248 * This function should be used with QSPI memories supporting the Read
1249 * Configuration Register (35h) instruction.
1251 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1254 * Return: 0 on success, -errno otherwise.
1256 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1261 /* Check current Quad Enable bit value. */
1264 dev_dbg(dev, "error while reading configuration register\n");
1268 if (ret & CR_QUAD_EN_SPAN)
1271 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1273 /* Keep the current value of the Status Register. */
1276 dev_dbg(dev, "error while reading status register\n");
1281 ret = write_sr_cr(nor, sr_cr);
1285 /* Read back and check it. */
1287 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1288 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1294 #endif /* CONFIG_SPI_FLASH_SPANSION */
1296 struct spi_nor_read_command {
1300 enum spi_nor_protocol proto;
1303 struct spi_nor_pp_command {
1305 enum spi_nor_protocol proto;
1308 enum spi_nor_read_command_index {
1311 SNOR_CMD_READ_1_1_1_DTR,
1314 SNOR_CMD_READ_1_1_2,
1315 SNOR_CMD_READ_1_2_2,
1316 SNOR_CMD_READ_2_2_2,
1317 SNOR_CMD_READ_1_2_2_DTR,
1320 SNOR_CMD_READ_1_1_4,
1321 SNOR_CMD_READ_1_4_4,
1322 SNOR_CMD_READ_4_4_4,
1323 SNOR_CMD_READ_1_4_4_DTR,
1326 SNOR_CMD_READ_1_1_8,
1327 SNOR_CMD_READ_1_8_8,
1328 SNOR_CMD_READ_8_8_8,
1329 SNOR_CMD_READ_1_8_8_DTR,
1334 enum spi_nor_pp_command_index {
1350 struct spi_nor_flash_parameter {
1354 struct spi_nor_hwcaps hwcaps;
1355 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1356 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1358 int (*quad_enable)(struct spi_nor *nor);
1362 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1366 enum spi_nor_protocol proto)
1368 read->num_mode_clocks = num_mode_clocks;
1369 read->num_wait_states = num_wait_states;
1370 read->opcode = opcode;
1371 read->proto = proto;
1375 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1377 enum spi_nor_protocol proto)
1379 pp->opcode = opcode;
1383 static int spi_nor_init_params(struct spi_nor *nor,
1384 const struct flash_info *info,
1385 struct spi_nor_flash_parameter *params)
1387 /* Set legacy flash parameters as default. */
1388 memset(params, 0, sizeof(*params));
1390 /* Set SPI NOR sizes. */
1391 params->size = info->sector_size * info->n_sectors;
1392 params->page_size = info->page_size;
1394 /* (Fast) Read settings. */
1395 params->hwcaps.mask |= SNOR_HWCAPS_READ;
1396 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
1397 0, 0, SPINOR_OP_READ,
1400 if (!(info->flags & SPI_NOR_NO_FR)) {
1401 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
1402 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
1403 0, 8, SPINOR_OP_READ_FAST,
1407 if (info->flags & SPI_NOR_DUAL_READ) {
1408 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
1409 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
1410 0, 8, SPINOR_OP_READ_1_1_2,
1414 if (info->flags & SPI_NOR_QUAD_READ) {
1415 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
1416 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
1417 0, 8, SPINOR_OP_READ_1_1_4,
1421 /* Page Program settings. */
1422 params->hwcaps.mask |= SNOR_HWCAPS_PP;
1423 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
1424 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
1426 if (info->flags & SPI_NOR_QUAD_READ) {
1427 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
1428 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
1429 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
1432 /* Select the procedure to set the Quad Enable bit. */
1433 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
1434 SNOR_HWCAPS_PP_QUAD)) {
1435 switch (JEDEC_MFR(info)) {
1436 #ifdef CONFIG_SPI_FLASH_MACRONIX
1437 case SNOR_MFR_MACRONIX:
1438 params->quad_enable = macronix_quad_enable;
1442 case SNOR_MFR_MICRON:
1446 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1447 /* Kept only for backward compatibility purpose. */
1448 params->quad_enable = spansion_read_cr_quad_enable;
1455 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
1459 for (i = 0; i < size; i++)
1460 if (table[i][0] == (int)hwcaps)
1466 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
1468 static const int hwcaps_read2cmd[][2] = {
1469 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
1470 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
1471 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
1472 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
1473 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
1474 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
1475 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
1476 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
1477 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
1478 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
1479 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
1480 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
1481 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
1482 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
1483 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
1486 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
1487 ARRAY_SIZE(hwcaps_read2cmd));
1490 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
1492 static const int hwcaps_pp2cmd[][2] = {
1493 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
1494 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
1495 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
1496 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
1497 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
1498 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
1499 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
1502 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
1503 ARRAY_SIZE(hwcaps_pp2cmd));
1506 static int spi_nor_select_read(struct spi_nor *nor,
1507 const struct spi_nor_flash_parameter *params,
1510 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
1511 const struct spi_nor_read_command *read;
1516 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
1520 read = ¶ms->reads[cmd];
1521 nor->read_opcode = read->opcode;
1522 nor->read_proto = read->proto;
1525 * In the spi-nor framework, we don't need to make the difference
1526 * between mode clock cycles and wait state clock cycles.
1527 * Indeed, the value of the mode clock cycles is used by a QSPI
1528 * flash memory to know whether it should enter or leave its 0-4-4
1529 * (Continuous Read / XIP) mode.
1530 * eXecution In Place is out of the scope of the mtd sub-system.
1531 * Hence we choose to merge both mode and wait state clock cycles
1532 * into the so called dummy clock cycles.
1534 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
1538 static int spi_nor_select_pp(struct spi_nor *nor,
1539 const struct spi_nor_flash_parameter *params,
1542 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
1543 const struct spi_nor_pp_command *pp;
1548 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
1552 pp = ¶ms->page_programs[cmd];
1553 nor->program_opcode = pp->opcode;
1554 nor->write_proto = pp->proto;
1558 static int spi_nor_select_erase(struct spi_nor *nor,
1559 const struct flash_info *info)
1561 struct mtd_info *mtd = &nor->mtd;
1563 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1564 /* prefer "small sector" erase if possible */
1565 if (info->flags & SECT_4K) {
1566 nor->erase_opcode = SPINOR_OP_BE_4K;
1567 mtd->erasesize = 4096;
1568 } else if (info->flags & SECT_4K_PMC) {
1569 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1570 mtd->erasesize = 4096;
1574 nor->erase_opcode = SPINOR_OP_SE;
1575 mtd->erasesize = info->sector_size;
1580 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
1581 const struct spi_nor_flash_parameter *params,
1582 const struct spi_nor_hwcaps *hwcaps)
1584 u32 ignored_mask, shared_mask;
1585 bool enable_quad_io;
1589 * Keep only the hardware capabilities supported by both the SPI
1590 * controller and the SPI flash memory.
1592 shared_mask = hwcaps->mask & params->hwcaps.mask;
1594 /* SPI n-n-n protocols are not supported yet. */
1595 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
1596 SNOR_HWCAPS_READ_4_4_4 |
1597 SNOR_HWCAPS_READ_8_8_8 |
1598 SNOR_HWCAPS_PP_4_4_4 |
1599 SNOR_HWCAPS_PP_8_8_8);
1600 if (shared_mask & ignored_mask) {
1602 "SPI n-n-n protocols are not supported yet.\n");
1603 shared_mask &= ~ignored_mask;
1606 /* Select the (Fast) Read command. */
1607 err = spi_nor_select_read(nor, params, shared_mask);
1610 "can't select read settings supported by both the SPI controller and memory.\n");
1614 /* Select the Page Program command. */
1615 err = spi_nor_select_pp(nor, params, shared_mask);
1618 "can't select write settings supported by both the SPI controller and memory.\n");
1622 /* Select the Sector Erase command. */
1623 err = spi_nor_select_erase(nor, info);
1626 "can't select erase settings supported by both the SPI controller and memory.\n");
1630 /* Enable Quad I/O if needed. */
1631 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
1632 spi_nor_get_protocol_width(nor->write_proto) == 4);
1633 if (enable_quad_io && params->quad_enable)
1634 nor->quad_enable = params->quad_enable;
1636 nor->quad_enable = NULL;
1641 static int spi_nor_init(struct spi_nor *nor)
1646 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1647 * with the software protection bits set
1649 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
1650 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
1651 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
1652 nor->info->flags & SPI_NOR_HAS_LOCK) {
1655 spi_nor_wait_till_ready(nor);
1658 if (nor->quad_enable) {
1659 err = nor->quad_enable(nor);
1661 dev_dbg(nor->dev, "quad mode not supported\n");
1669 int spi_nor_scan(struct spi_nor *nor)
1671 struct spi_nor_flash_parameter params;
1672 const struct flash_info *info = NULL;
1673 struct mtd_info *mtd = &nor->mtd;
1674 struct spi_nor_hwcaps hwcaps = {
1675 .mask = SNOR_HWCAPS_READ |
1676 SNOR_HWCAPS_READ_FAST |
1679 struct spi_slave *spi = nor->spi;
1682 /* Reset SPI protocol for all commands. */
1683 nor->reg_proto = SNOR_PROTO_1_1_1;
1684 nor->read_proto = SNOR_PROTO_1_1_1;
1685 nor->write_proto = SNOR_PROTO_1_1_1;
1686 nor->read = spi_nor_read_data;
1687 nor->write = spi_nor_write_data;
1688 nor->read_reg = spi_nor_read_reg;
1689 nor->write_reg = spi_nor_write_reg;
1691 if (spi->mode & SPI_RX_QUAD) {
1692 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
1694 if (spi->mode & SPI_TX_QUAD)
1695 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
1696 SNOR_HWCAPS_PP_1_1_4 |
1697 SNOR_HWCAPS_PP_1_4_4);
1698 } else if (spi->mode & SPI_RX_DUAL) {
1699 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
1701 if (spi->mode & SPI_TX_DUAL)
1702 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
1705 info = spi_nor_read_id(nor);
1706 if (IS_ERR_OR_NULL(info))
1709 ret = spi_nor_init_params(nor, info, ¶ms);
1714 mtd->name = info->name;
1716 mtd->type = MTD_NORFLASH;
1718 mtd->flags = MTD_CAP_NORFLASH;
1719 mtd->size = params.size;
1720 mtd->_erase = spi_nor_erase;
1721 mtd->_read = spi_nor_read;
1723 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
1724 /* NOR protection support for STmicro/Micron chips and similar */
1725 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
1726 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1727 JEDEC_MFR(info) == SNOR_MFR_SST ||
1728 info->flags & SPI_NOR_HAS_LOCK) {
1729 nor->flash_lock = stm_lock;
1730 nor->flash_unlock = stm_unlock;
1731 nor->flash_is_locked = stm_is_locked;
1735 #ifdef CONFIG_SPI_FLASH_SST
1736 /* sst nor chips use AAI word program */
1737 if (info->flags & SST_WRITE)
1738 mtd->_write = sst_write;
1741 mtd->_write = spi_nor_write;
1743 if (info->flags & USE_FSR)
1744 nor->flags |= SNOR_F_USE_FSR;
1745 if (info->flags & SPI_NOR_HAS_TB)
1746 nor->flags |= SNOR_F_HAS_SR_TB;
1747 if (info->flags & NO_CHIP_ERASE)
1748 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
1749 if (info->flags & USE_CLSR)
1750 nor->flags |= SNOR_F_USE_CLSR;
1752 if (info->flags & SPI_NOR_NO_ERASE)
1753 mtd->flags |= MTD_NO_ERASE;
1755 nor->page_size = params.page_size;
1756 mtd->writebufsize = nor->page_size;
1758 /* Some devices cannot do fast-read, no matter what DT tells us */
1759 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
1760 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
1763 * Configure the SPI memory:
1764 * - select op codes for (Fast) Read, Page Program and Sector Erase.
1765 * - set the number of dummy cycles (mode cycles + wait states).
1766 * - set the SPI protocols for register and memory accesses.
1767 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
1769 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
1773 if (info->addr_width) {
1774 nor->addr_width = info->addr_width;
1776 nor->addr_width = 3;
1779 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
1780 dev_dbg(dev, "address width is too large: %u\n",
1785 /* Send all the required SPI flash commands to initialize device */
1787 ret = spi_nor_init(nor);
1791 nor->name = mtd->name;
1792 nor->size = mtd->size;
1793 nor->erase_size = mtd->erasesize;
1794 nor->sector_size = mtd->erasesize;
1796 #ifndef CONFIG_SPL_BUILD
1797 printf("SF: Detected %s with page size ", nor->name);
1798 print_size(nor->page_size, ", erase size ");
1799 print_size(nor->erase_size, ", total ");
1800 print_size(nor->size, "");