1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
16 #include <dm/device_compat.h>
17 #include <dm/devres.h>
18 #include <linux/bitops.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/math64.h>
23 #include <linux/sizes.h>
24 #include <linux/bitfield.h>
25 #include <linux/delay.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/spi-nor.h>
32 #include "sf_internal.h"
34 /* Define max times to check status register before we give up. */
37 * For everything but full-chip erase; probably could be much smaller, but kept
38 * around for safety for now
41 #define HZ CONFIG_SYS_HZ
43 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
45 #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
47 struct sfdp_parameter_header {
51 u8 length; /* in double words */
52 u8 parameter_table_pointer[3]; /* byte address */
56 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
57 #define SFDP_PARAM_HEADER_PTP(p) \
58 (((p)->parameter_table_pointer[2] << 16) | \
59 ((p)->parameter_table_pointer[1] << 8) | \
60 ((p)->parameter_table_pointer[0] << 0))
62 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
63 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
64 #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
65 #define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */
67 #define SFDP_SIGNATURE 0x50444653U
68 #define SFDP_JESD216_MAJOR 1
69 #define SFDP_JESD216_MINOR 0
70 #define SFDP_JESD216A_MINOR 5
71 #define SFDP_JESD216B_MINOR 6
74 u32 signature; /* Ox50444653U <=> "SFDP" */
77 u8 nph; /* 0-base number of parameter headers */
80 /* Basic Flash Parameter Table. */
81 struct sfdp_parameter_header bfpt_header;
84 /* Basic Flash Parameter Table */
87 * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs.
88 * They are indexed from 1 but C arrays are indexed from 0.
90 #define BFPT_DWORD(i) ((i) - 1)
91 #define BFPT_DWORD_MAX 20
93 /* The first version of JESB216 defined only 9 DWORDs. */
94 #define BFPT_DWORD_MAX_JESD216 9
95 #define BFPT_DWORD_MAX_JESD216B 16
98 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
99 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
100 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
101 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
102 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
103 #define BFPT_DWORD1_DTR BIT(19)
104 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
105 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
106 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
109 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
110 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
113 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
114 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
119 * (from JESD216 rev B)
120 * Quad Enable Requirements (QER):
121 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
122 * reads based on instruction. DQ3/HOLD# functions are hold during
124 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
125 * two data bytes where bit 1 of the second byte is one.
127 * Writing only one byte to the status register has the side-effect of
128 * clearing status register 2, including the QE bit. The 100b code is
129 * used if writing one byte to the status register does not modify
131 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
132 * one data byte where bit 6 is one.
134 * - 011b: QE is bit 7 of status register 2. It is set via Write status
135 * register 2 instruction 3Eh with one data byte where bit 7 is one.
137 * The status register 2 is read using instruction 3Fh.
138 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
139 * two data bytes where bit 1 of the second byte is one.
141 * In contrast to the 001b code, writing one byte to the status
142 * register does not modify status register 2.
143 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
144 * Read Status instruction 05h. Status register2 is read using
145 * instruction 35h. QE is set via Writ Status instruction 01h with
146 * two data bytes where bit 1 of the second byte is one.
149 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
150 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
151 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
152 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
153 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
154 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
155 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
157 #define BFPT_DWORD16_SOFT_RST BIT(12)
159 #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29)
160 #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */
161 #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */
162 #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */
163 #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
165 /* xSPI Profile 1.0 table (from JESD216D.01). */
166 #define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8)
167 #define PROFILE1_DWORD1_RDSR_DUMMY BIT(28)
168 #define PROFILE1_DWORD1_RDSR_ADDR_BYTES BIT(29)
169 #define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7)
170 #define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27)
171 #define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17)
172 #define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)
173 #define PROFILE1_DUMMY_DEFAULT 20
176 u32 dwords[BFPT_DWORD_MAX];
180 * struct spi_nor_fixups - SPI NOR fixup hooks
181 * @default_init: called after default flash parameters init. Used to tweak
182 * flash parameters when information provided by the flash_info
183 * table is incomplete or wrong.
184 * @post_bfpt: called after the BFPT table has been parsed
185 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
186 * that do not support RDSFDP). Typically used to tweak various
187 * parameters that could not be extracted by other means (i.e.
188 * when information provided by the SFDP/flash_info tables are
189 * incomplete or wrong).
191 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
192 * table is broken or not available.
194 struct spi_nor_fixups {
195 void (*default_init)(struct spi_nor *nor);
196 int (*post_bfpt)(struct spi_nor *nor,
197 const struct sfdp_parameter_header *bfpt_header,
198 const struct sfdp_bfpt *bfpt,
199 struct spi_nor_flash_parameter *params);
200 void (*post_sfdp)(struct spi_nor *nor,
201 struct spi_nor_flash_parameter *params);
204 #define SPI_NOR_SRST_SLEEP_LEN 200
207 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
209 * @nor: pointer to a 'struct spi_nor'
210 * @op: pointer to the 'struct spi_mem_op' whose properties
211 * need to be initialized.
213 * Right now, only "repeat" and "invert" are supported.
215 * Return: The opcode extension.
217 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
218 const struct spi_mem_op *op)
220 switch (nor->cmd_ext_type) {
221 case SPI_NOR_EXT_INVERT:
222 return ~op->cmd.opcode;
224 case SPI_NOR_EXT_REPEAT:
225 return op->cmd.opcode;
228 dev_dbg(nor->dev, "Unknown command extension type\n");
234 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
235 * @nor: pointer to a 'struct spi_nor'
236 * @op: pointer to the 'struct spi_mem_op' whose properties
237 * need to be initialized.
238 * @proto: the protocol from which the properties need to be set.
240 static void spi_nor_setup_op(const struct spi_nor *nor,
241 struct spi_mem_op *op,
242 const enum spi_nor_protocol proto)
246 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
249 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
251 if (op->dummy.nbytes)
252 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
255 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
257 if (spi_nor_protocol_is_dtr(proto)) {
259 * spi-mem supports mixed DTR modes, but right now we can only
260 * have all phases either DTR or STR. IOW, spi-mem can have
261 * something like 4S-4D-4D, but spi-nor can't. So, set all 4
262 * phases to either DTR or STR.
264 op->cmd.dtr = op->addr.dtr = op->dummy.dtr =
267 /* 2 bytes per clock cycle in DTR mode. */
268 op->dummy.nbytes *= 2;
270 ext = spi_nor_get_cmd_ext(nor, op);
271 op->cmd.opcode = (op->cmd.opcode << 8) | ext;
276 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
279 if (op->data.dir == SPI_MEM_DATA_IN)
280 op->data.buf.in = buf;
282 op->data.buf.out = buf;
283 return spi_mem_exec_op(nor->spi, op);
286 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
288 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 0),
291 SPI_MEM_OP_DATA_IN(len, NULL, 0));
294 spi_nor_setup_op(nor, &op, nor->reg_proto);
296 ret = spi_nor_read_write_reg(nor, &op, val);
298 dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
303 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
305 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),
308 SPI_MEM_OP_DATA_OUT(len, NULL, 0));
310 spi_nor_setup_op(nor, &op, nor->reg_proto);
313 op.data.dir = SPI_MEM_NO_DATA;
315 return spi_nor_read_write_reg(nor, &op, buf);
318 #ifdef CONFIG_SPI_FLASH_SPANSION
319 static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy,
322 struct spi_mem_op op =
323 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1),
324 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
325 SPI_MEM_OP_DUMMY(dummy / 8, 1),
326 SPI_MEM_OP_DATA_IN(1, NULL, 1));
328 return spi_nor_read_write_reg(nor, &op, val);
331 static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val)
333 struct spi_mem_op op =
334 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1),
335 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
337 SPI_MEM_OP_DATA_OUT(1, NULL, 1));
339 return spi_nor_read_write_reg(nor, &op, &val);
343 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
346 struct spi_mem_op op =
347 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
348 SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
349 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
350 SPI_MEM_OP_DATA_IN(len, buf, 0));
351 size_t remaining = len;
354 spi_nor_setup_op(nor, &op, nor->read_proto);
356 /* convert the dummy cycles to the number of bytes */
357 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
358 if (spi_nor_protocol_is_dtr(nor->read_proto))
359 op.dummy.nbytes *= 2;
362 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
363 ret = spi_mem_adjust_op_size(nor->spi, &op);
367 ret = spi_mem_exec_op(nor->spi, &op);
371 op.addr.val += op.data.nbytes;
372 remaining -= op.data.nbytes;
373 op.data.buf.in += op.data.nbytes;
379 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
382 struct spi_mem_op op =
383 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
384 SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
386 SPI_MEM_OP_DATA_OUT(len, buf, 0));
389 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
392 spi_nor_setup_op(nor, &op, nor->write_proto);
394 ret = spi_mem_adjust_op_size(nor->spi, &op);
397 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
399 ret = spi_mem_exec_op(nor->spi, &op);
403 return op.data.nbytes;
407 * Read the status register, returning its value in the location
408 * Return the status register value.
409 * Returns negative if error occurred.
411 static int read_sr(struct spi_nor *nor)
413 struct spi_mem_op op;
416 u8 addr_nbytes, dummy;
418 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
419 addr_nbytes = nor->rdsr_addr_nbytes;
420 dummy = nor->rdsr_dummy;
426 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0),
427 SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
428 SPI_MEM_OP_DUMMY(dummy, 0),
429 SPI_MEM_OP_DATA_IN(1, NULL, 0));
431 spi_nor_setup_op(nor, &op, nor->reg_proto);
434 * We don't want to read only one byte in DTR mode. So, read 2 and then
435 * discard the second byte.
437 if (spi_nor_protocol_is_dtr(nor->reg_proto))
440 ret = spi_nor_read_write_reg(nor, &op, val);
442 pr_debug("error %d reading SR\n", (int)ret);
450 * Read the flag status register, returning its value in the location
451 * Return the status register value.
452 * Returns negative if error occurred.
454 static int read_fsr(struct spi_nor *nor)
456 struct spi_mem_op op;
459 u8 addr_nbytes, dummy;
461 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
462 addr_nbytes = nor->rdsr_addr_nbytes;
463 dummy = nor->rdsr_dummy;
469 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
470 SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
471 SPI_MEM_OP_DUMMY(dummy, 0),
472 SPI_MEM_OP_DATA_IN(1, NULL, 0));
474 spi_nor_setup_op(nor, &op, nor->reg_proto);
477 * We don't want to read only one byte in DTR mode. So, read 2 and then
478 * discard the second byte.
480 if (spi_nor_protocol_is_dtr(nor->reg_proto))
483 ret = spi_nor_read_write_reg(nor, &op, val);
485 pr_debug("error %d reading FSR\n", ret);
493 * Read configuration register, returning its value in the
494 * location. Return the configuration register value.
495 * Returns negative if error occurred.
497 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
498 static int read_cr(struct spi_nor *nor)
503 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
505 dev_dbg(nor->dev, "error %d reading CR\n", ret);
514 * Write status register 1 byte
515 * Returns negative if error occurred.
517 static int write_sr(struct spi_nor *nor, u8 val)
519 nor->cmd_buf[0] = val;
520 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
524 * Set write enable latch with Write Enable command.
525 * Returns negative if error occurred.
527 static int write_enable(struct spi_nor *nor)
529 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
533 * Send write disable instruction to the chip.
535 static int write_disable(struct spi_nor *nor)
537 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
540 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
545 #ifndef CONFIG_SPI_FLASH_BAR
546 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
550 for (i = 0; i < size; i++)
551 if (table[i][0] == opcode)
554 /* No conversion found, keep input op code. */
558 static u8 spi_nor_convert_3to4_read(u8 opcode)
560 static const u8 spi_nor_3to4_read[][2] = {
561 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
562 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
563 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
564 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
565 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
566 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
567 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
568 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
570 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
571 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
572 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
575 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
576 ARRAY_SIZE(spi_nor_3to4_read));
579 static u8 spi_nor_convert_3to4_program(u8 opcode)
581 static const u8 spi_nor_3to4_program[][2] = {
582 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
583 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
584 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
585 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
586 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
589 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
590 ARRAY_SIZE(spi_nor_3to4_program));
593 static u8 spi_nor_convert_3to4_erase(u8 opcode)
595 static const u8 spi_nor_3to4_erase[][2] = {
596 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
597 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
598 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
601 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
602 ARRAY_SIZE(spi_nor_3to4_erase));
605 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
606 const struct flash_info *info)
608 /* Do some manufacturer fixups first */
609 switch (JEDEC_MFR(info)) {
610 case SNOR_MFR_SPANSION:
611 /* No small sector erase for 4-byte command set */
612 nor->erase_opcode = SPINOR_OP_SE;
613 nor->mtd.erasesize = info->sector_size;
620 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
621 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
622 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
624 #endif /* !CONFIG_SPI_FLASH_BAR */
626 /* Enable/disable 4-byte addressing mode. */
627 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
631 bool need_wren = false;
634 switch (JEDEC_MFR(info)) {
636 case SNOR_MFR_MICRON:
637 /* Some Micron need WREN command; all will accept it */
640 case SNOR_MFR_MACRONIX:
641 case SNOR_MFR_WINBOND:
645 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
646 status = nor->write_reg(nor, cmd, NULL, 0);
650 if (!status && !enable &&
651 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
653 * On Winbond W25Q256FV, leaving 4byte mode causes
654 * the Extended Address Register to be set to 1, so all
655 * 3-byte-address reads come from the second 16M.
656 * We must clear the register to enable normal behavior.
660 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
667 nor->cmd_buf[0] = enable << 7;
668 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
672 static int spi_nor_sr_ready(struct spi_nor *nor)
674 int sr = read_sr(nor);
679 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
681 dev_dbg(nor->dev, "Erase Error occurred\n");
683 dev_dbg(nor->dev, "Programming Error occurred\n");
685 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
689 return !(sr & SR_WIP);
692 static int spi_nor_fsr_ready(struct spi_nor *nor)
694 int fsr = read_fsr(nor);
699 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
701 dev_err(nor->dev, "Erase operation failed.\n");
703 dev_err(nor->dev, "Program operation failed.\n");
705 if (fsr & FSR_PT_ERR)
707 "Attempted to modify a protected sector.\n");
709 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
713 return fsr & FSR_READY;
716 static int spi_nor_ready(struct spi_nor *nor)
720 sr = spi_nor_sr_ready(nor);
723 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
730 * Service routine to read status register until ready, or timeout occurs.
731 * Returns non-zero if error.
733 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
734 unsigned long timeout)
736 unsigned long timebase;
739 timebase = get_timer(0);
741 while (get_timer(timebase) < timeout) {
742 ret = spi_nor_ready(nor);
749 dev_err(nor->dev, "flash operation timed out\n");
754 static int spi_nor_wait_till_ready(struct spi_nor *nor)
756 return spi_nor_wait_till_ready_with_timeout(nor,
757 DEFAULT_READY_WAIT_JIFFIES);
760 #ifdef CONFIG_SPI_FLASH_BAR
762 * This "clean_bar" is necessary in a situation when one was accessing
763 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
765 * After it the BA24 bit shall be cleared to allow access to correct
766 * memory region after SW reset (by calling "reset" command).
768 * Otherwise, the BA24 bit may be left set and then after reset, the
769 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
771 static int clean_bar(struct spi_nor *nor)
773 u8 cmd, bank_sel = 0;
775 if (nor->bank_curr == 0)
777 cmd = nor->bank_write_cmd;
781 return nor->write_reg(nor, cmd, &bank_sel, 1);
784 static int write_bar(struct spi_nor *nor, u32 offset)
789 bank_sel = offset / SZ_16M;
790 if (bank_sel == nor->bank_curr)
793 cmd = nor->bank_write_cmd;
795 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
797 debug("SF: fail to write bank register\n");
802 nor->bank_curr = bank_sel;
803 return nor->bank_curr;
806 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
811 switch (JEDEC_MFR(info)) {
812 case SNOR_MFR_SPANSION:
813 nor->bank_read_cmd = SPINOR_OP_BRRD;
814 nor->bank_write_cmd = SPINOR_OP_BRWR;
817 nor->bank_read_cmd = SPINOR_OP_RDEAR;
818 nor->bank_write_cmd = SPINOR_OP_WREAR;
821 ret = nor->read_reg(nor, nor->bank_read_cmd,
824 debug("SF: fail to read bank addr register\n");
827 nor->bank_curr = curr_bank;
834 * Initiate the erasure of a single sector. Returns the number of bytes erased
835 * on success, a negative error code on error.
837 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
839 struct spi_mem_op op =
840 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
841 SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
846 spi_nor_setup_op(nor, &op, nor->write_proto);
849 return nor->erase(nor, addr);
852 * Default implementation, if driver doesn't have a specialized HW
855 ret = spi_mem_exec_op(nor->spi, &op);
859 return nor->mtd.erasesize;
863 * Erase an address range on the nor chip. The address range may extend
864 * one or more erase sectors. Return an error is there is a problem erasing.
866 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
868 struct spi_nor *nor = mtd_to_spi_nor(mtd);
872 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
873 (long long)instr->len);
878 div_u64_rem(instr->len, mtd->erasesize, &rem);
887 #ifdef CONFIG_SPI_FLASH_BAR
888 ret = write_bar(nor, addr);
894 ret = spi_nor_erase_sector(nor, addr);
901 ret = spi_nor_wait_till_ready(nor);
907 #ifdef CONFIG_SPI_FLASH_BAR
908 ret = clean_bar(nor);
915 #ifdef CONFIG_SPI_FLASH_S28HS512T
917 * spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress
919 * @nor: pointer to a 'struct spi_nor'
920 * @addr: address of the sector to erase
921 * @opcode_4k: opcode for 4K sector erase
922 * @ovlsz_top: size of overlaid portion at the top address
923 * @ovlsz_btm: size of overlaid portion at the bottom address
925 * Erase an address range on the nor chip that can contain 4KB sectors overlaid
926 * on top and/or bottom. The appropriate erase opcode and size are chosen by
927 * address to erase and size of overlaid portion.
929 * Return: number of bytes erased on success, -errno otherwise.
931 static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr,
932 u8 opcode_4k, u32 ovlsz_top,
935 struct spi_mem_op op =
936 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
937 SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
940 struct mtd_info *mtd = &nor->mtd;
945 if (op.addr.val < ovlsz_btm ||
946 op.addr.val >= mtd->size - ovlsz_top) {
947 op.cmd.opcode = opcode_4k;
950 /* Non-overlaid portion in the normal sector at the bottom */
951 } else if (op.addr.val == ovlsz_btm) {
952 op.cmd.opcode = nor->erase_opcode;
953 erasesize = mtd->erasesize - ovlsz_btm;
955 /* Non-overlaid portion in the normal sector at the top */
956 } else if (op.addr.val == mtd->size - mtd->erasesize) {
957 op.cmd.opcode = nor->erase_opcode;
958 erasesize = mtd->erasesize - ovlsz_top;
962 op.cmd.opcode = nor->erase_opcode;
963 erasesize = mtd->erasesize;
966 spi_nor_setup_op(nor, &op, nor->write_proto);
968 ret = spi_mem_exec_op(nor->spi, &op);
976 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
977 /* Write status register and ensure bits in mask match written values */
978 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
983 ret = write_sr(nor, status_new);
987 ret = spi_nor_wait_till_ready(nor);
995 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
998 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
1001 struct mtd_info *mtd = &nor->mtd;
1002 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1003 int shift = ffs(mask) - 1;
1011 pow = ((sr & mask) ^ mask) >> shift;
1012 *len = mtd->size >> pow;
1013 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
1016 *ofs = mtd->size - *len;
1021 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
1022 * @locked is false); 0 otherwise
1024 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
1033 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
1036 /* Requested range is a sub-range of locked range */
1037 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
1039 /* Requested range does not overlap with locked range */
1040 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
1043 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1046 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
1049 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1052 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
1056 * Lock a region of the flash. Compatible with ST Micro and similar flash.
1057 * Supports the block protection bits BP{0,1,2} in the status register
1058 * (SR). Does not support these features found in newer SR bitfields:
1059 * - SEC: sector/block protect - only handle SEC=0 (block protect)
1060 * - CMP: complement protect - only support CMP=0 (range is not complemented)
1062 * Support for the following is provided conditionally for some flash:
1063 * - TB: top/bottom protect
1065 * Sample table portion for 8MB flash (Winbond w25q64fw):
1067 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
1068 * --------------------------------------------------------------------------
1069 * X | X | 0 | 0 | 0 | NONE | NONE
1070 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
1071 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
1072 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
1073 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
1074 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
1075 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
1076 * X | X | 1 | 1 | 1 | 8 MB | ALL
1077 * ------|-------|-------|-------|-------|---------------|-------------------
1078 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
1079 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
1080 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
1081 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
1082 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
1083 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
1085 * Returns negative on errors, 0 on success.
1087 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1089 struct mtd_info *mtd = &nor->mtd;
1090 int status_old, status_new;
1091 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1092 u8 shift = ffs(mask) - 1, pow, val;
1094 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1097 status_old = read_sr(nor);
1101 /* If nothing in our range is unlocked, we don't need to do anything */
1102 if (stm_is_locked_sr(nor, ofs, len, status_old))
1105 /* If anything below us is unlocked, we can't use 'bottom' protection */
1106 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
1107 can_be_bottom = false;
1109 /* If anything above us is unlocked, we can't use 'top' protection */
1110 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1114 if (!can_be_bottom && !can_be_top)
1117 /* Prefer top, if both are valid */
1118 use_top = can_be_top;
1120 /* lock_len: length of region that should end up locked */
1122 lock_len = mtd->size - ofs;
1124 lock_len = ofs + len;
1127 * Need smallest pow such that:
1129 * 1 / (2^pow) <= (len / size)
1131 * so (assuming power-of-2 size) we do:
1133 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
1135 pow = ilog2(mtd->size) - ilog2(lock_len);
1136 val = mask - (pow << shift);
1139 /* Don't "lock" with no region! */
1143 status_new = (status_old & ~mask & ~SR_TB) | val;
1145 /* Disallow further writes if WP pin is asserted */
1146 status_new |= SR_SRWD;
1149 status_new |= SR_TB;
1151 /* Don't bother if they're the same */
1152 if (status_new == status_old)
1155 /* Only modify protection if it will not unlock other areas */
1156 if ((status_new & mask) < (status_old & mask))
1159 return write_sr_and_check(nor, status_new, mask);
1163 * Unlock a region of the flash. See stm_lock() for more info
1165 * Returns negative on errors, 0 on success.
1167 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1169 struct mtd_info *mtd = &nor->mtd;
1170 int status_old, status_new;
1171 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1172 u8 shift = ffs(mask) - 1, pow, val;
1174 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1177 status_old = read_sr(nor);
1181 /* If nothing in our range is locked, we don't need to do anything */
1182 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
1185 /* If anything below us is locked, we can't use 'top' protection */
1186 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
1189 /* If anything above us is locked, we can't use 'bottom' protection */
1190 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1192 can_be_bottom = false;
1194 if (!can_be_bottom && !can_be_top)
1197 /* Prefer top, if both are valid */
1198 use_top = can_be_top;
1200 /* lock_len: length of region that should remain locked */
1202 lock_len = mtd->size - (ofs + len);
1207 * Need largest pow such that:
1209 * 1 / (2^pow) >= (len / size)
1211 * so (assuming power-of-2 size) we do:
1213 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
1215 pow = ilog2(mtd->size) - order_base_2(lock_len);
1216 if (lock_len == 0) {
1217 val = 0; /* fully unlocked */
1219 val = mask - (pow << shift);
1220 /* Some power-of-two sizes are not supported */
1225 status_new = (status_old & ~mask & ~SR_TB) | val;
1227 /* Don't protect status register if we're fully unlocked */
1229 status_new &= ~SR_SRWD;
1232 status_new |= SR_TB;
1234 /* Don't bother if they're the same */
1235 if (status_new == status_old)
1238 /* Only modify protection if it will not lock other areas */
1239 if ((status_new & mask) > (status_old & mask))
1242 return write_sr_and_check(nor, status_new, mask);
1246 * Check if a region of the flash is (completely) locked. See stm_lock() for
1249 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1250 * negative on errors.
1252 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1256 status = read_sr(nor);
1260 return stm_is_locked_sr(nor, ofs, len, status);
1262 #endif /* CONFIG_SPI_FLASH_STMICRO */
1264 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1267 u8 id[SPI_NOR_MAX_ID_LEN];
1268 const struct flash_info *info;
1270 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1272 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1273 return ERR_PTR(tmp);
1277 for (; info->name; info++) {
1279 if (!memcmp(info->id, id, info->id_len))
1284 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1285 id[0], id[1], id[2]);
1286 return ERR_PTR(-ENODEV);
1289 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1290 size_t *retlen, u_char *buf)
1292 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1295 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1299 size_t read_len = len;
1301 #ifdef CONFIG_SPI_FLASH_BAR
1304 ret = write_bar(nor, addr);
1306 return log_ret(ret);
1307 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
1309 if (len < remain_len)
1312 read_len = remain_len;
1315 ret = nor->read(nor, addr, read_len, buf);
1317 /* We shouldn't see 0-length reads */
1332 #ifdef CONFIG_SPI_FLASH_BAR
1333 ret = clean_bar(nor);
1338 #ifdef CONFIG_SPI_FLASH_SST
1340 * sst26 flash series has its own block protection implementation:
1341 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
1342 * 1x - 32 KByte blocks - write protection bits
1343 * rest - 64 KByte blocks - write protection bits
1344 * 1x - 32 KByte blocks - write protection bits
1345 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
1347 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
1348 * will be treated as single block.
1350 #define SST26_BPR_8K_NUM 4
1351 #define SST26_MAX_BPR_REG_LEN (18 + 1)
1352 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
1360 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
1363 case SST26_CTL_LOCK:
1364 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
1366 case SST26_CTL_UNLOCK:
1367 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
1369 case SST26_CTL_CHECK:
1370 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
1377 * Lock, unlock or check lock status of the flash region of the flash (depending
1378 * on the lock_ctl value)
1380 static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
1382 struct mtd_info *mtd = &nor->mtd;
1383 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
1384 bool lower_64k = false, upper_64k = false;
1385 u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
1388 /* Check length and offset for 64k alignment */
1389 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
1390 dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
1394 if (ofs + len > mtd->size) {
1395 dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
1396 ofs, len, mtd->size);
1400 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
1401 if (mtd->size != SZ_2M &&
1402 mtd->size != SZ_4M &&
1406 bpr_size = 2 + (mtd->size / SZ_64K / 8);
1408 ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
1410 dev_err(nor->dev, "fail to read block-protection register\n");
1414 rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
1415 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
1417 upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
1418 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
1420 /* Lower bits in block-protection register are about 64k region */
1421 bpr_ptr = lptr_64k / SZ_64K - 1;
1423 /* Process 64K blocks region */
1424 while (lptr_64k < rptr_64k) {
1425 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1432 /* 32K and 8K region bits in BPR are after 64k region bits */
1433 bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
1435 /* Process lower 32K block region */
1437 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1442 /* Process upper 32K block region */
1444 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1449 /* Process lower 8K block regions */
1450 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1452 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1455 /* In 8K area BPR has both read and write protection bits */
1459 /* Process upper 8K block regions */
1460 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1462 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1465 /* In 8K area BPR has both read and write protection bits */
1469 /* If we check region status we don't need to write BPR back */
1470 if (ctl == SST26_CTL_CHECK)
1473 ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
1475 dev_err(nor->dev, "fail to write block-protection register\n");
1482 static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1484 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
1487 static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1489 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
1493 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
1494 * and negative on errors.
1496 static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1499 * is_locked function is used for check before reading or erasing flash
1500 * region, so offset and length might be not 64k allighned, so adjust
1501 * them to be 64k allighned as sst26_lock_ctl works only with 64k
1502 * allighned regions.
1504 ofs -= ofs & (SZ_64K - 1);
1505 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
1507 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
1510 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
1511 size_t *retlen, const u_char *buf)
1516 for (actual = 0; actual < len; actual++) {
1517 nor->program_opcode = SPINOR_OP_BP;
1520 /* write one byte. */
1521 ret = nor->write(nor, to, 1, buf + actual);
1524 ret = spi_nor_wait_till_ready(nor);
1535 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1536 size_t *retlen, const u_char *buf)
1538 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1539 struct spi_slave *spi = nor->spi;
1543 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1544 if (spi->mode & SPI_TX_BYTE)
1545 return sst_write_byteprogram(nor, to, len, retlen, buf);
1549 nor->sst_write_second = false;
1552 /* Start write from odd address. */
1554 nor->program_opcode = SPINOR_OP_BP;
1556 /* write one byte. */
1557 ret = nor->write(nor, to, 1, buf);
1560 ret = spi_nor_wait_till_ready(nor);
1566 /* Write out most of the data here. */
1567 for (; actual < len - 1; actual += 2) {
1568 nor->program_opcode = SPINOR_OP_AAI_WP;
1570 /* write two bytes. */
1571 ret = nor->write(nor, to, 2, buf + actual);
1574 ret = spi_nor_wait_till_ready(nor);
1578 nor->sst_write_second = true;
1580 nor->sst_write_second = false;
1583 ret = spi_nor_wait_till_ready(nor);
1587 /* Write out trailing byte if it exists. */
1588 if (actual != len) {
1591 nor->program_opcode = SPINOR_OP_BP;
1592 ret = nor->write(nor, to, 1, buf + actual);
1595 ret = spi_nor_wait_till_ready(nor);
1607 * Write an address range to the nor chip. Data must be written in
1608 * FLASH_PAGESIZE chunks. The address range may be any size provided
1609 * it is within the physical boundaries.
1611 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1612 size_t *retlen, const u_char *buf)
1614 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1615 size_t page_offset, page_remain, i;
1618 #ifdef CONFIG_SPI_FLASH_SST
1619 /* sst nor chips use AAI word program */
1620 if (nor->info->flags & SST_WRITE)
1621 return sst_write(mtd, to, len, retlen, buf);
1624 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1629 for (i = 0; i < len; ) {
1631 loff_t addr = to + i;
1635 * If page_size is a power of two, the offset can be quickly
1636 * calculated with an AND operation. On the other cases we
1637 * need to do a modulus operation (more expensive).
1639 if (is_power_of_2(nor->page_size)) {
1640 page_offset = addr & (nor->page_size - 1);
1644 page_offset = do_div(aux, nor->page_size);
1646 /* the size of data remaining on the first page */
1647 page_remain = min_t(size_t,
1648 nor->page_size - page_offset, len - i);
1650 #ifdef CONFIG_SPI_FLASH_BAR
1651 ret = write_bar(nor, addr);
1656 ret = nor->write(nor, addr, page_remain, buf + i);
1661 ret = spi_nor_wait_till_ready(nor);
1669 #ifdef CONFIG_SPI_FLASH_BAR
1670 ret = clean_bar(nor);
1675 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
1677 * macronix_quad_enable() - set QE bit in Status Register.
1678 * @nor: pointer to a 'struct spi_nor'
1680 * Set the Quad Enable (QE) bit in the Status Register.
1682 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1684 * Return: 0 on success, -errno otherwise.
1686 static int macronix_quad_enable(struct spi_nor *nor)
1693 if (val & SR_QUAD_EN_MX)
1698 write_sr(nor, val | SR_QUAD_EN_MX);
1700 ret = spi_nor_wait_till_ready(nor);
1705 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1706 dev_err(nor->dev, "Macronix Quad bit not set\n");
1714 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1716 * Write status Register and configuration register with 2 bytes
1717 * The first byte will be written to the status register, while the
1718 * second byte will be written to the configuration register.
1719 * Return negative if error occurred.
1721 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1727 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1730 "error while writing configuration register\n");
1734 ret = spi_nor_wait_till_ready(nor);
1737 "timeout while writing configuration register\n");
1745 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1746 * @nor: pointer to a 'struct spi_nor'
1748 * Set the Quad Enable (QE) bit in the Configuration Register.
1749 * This function should be used with QSPI memories supporting the Read
1750 * Configuration Register (35h) instruction.
1752 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1755 * Return: 0 on success, -errno otherwise.
1757 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1762 /* Check current Quad Enable bit value. */
1766 "error while reading configuration register\n");
1770 if (ret & CR_QUAD_EN_SPAN)
1773 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1775 /* Keep the current value of the Status Register. */
1778 dev_dbg(nor->dev, "error while reading status register\n");
1783 ret = write_sr_cr(nor, sr_cr);
1787 /* Read back and check it. */
1789 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1790 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1797 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1799 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1800 * @nor: pointer to a 'struct spi_nor'
1802 * Set the Quad Enable (QE) bit in the Configuration Register.
1803 * This function should be used with QSPI memories not supporting the Read
1804 * Configuration Register (35h) instruction.
1806 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1809 * Return: 0 on success, -errno otherwise.
1811 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1816 /* Keep the current value of the Status Register. */
1819 dev_dbg(nor->dev, "error while reading status register\n");
1823 sr_cr[1] = CR_QUAD_EN_SPAN;
1825 return write_sr_cr(nor, sr_cr);
1828 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1829 #endif /* CONFIG_SPI_FLASH_SPANSION */
1832 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1836 enum spi_nor_protocol proto)
1838 read->num_mode_clocks = num_mode_clocks;
1839 read->num_wait_states = num_wait_states;
1840 read->opcode = opcode;
1841 read->proto = proto;
1845 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1847 enum spi_nor_protocol proto)
1849 pp->opcode = opcode;
1853 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1855 * Serial Flash Discoverable Parameters (SFDP) parsing.
1859 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1860 * @nor: pointer to a 'struct spi_nor'
1861 * @addr: offset in the SFDP area to start reading data from
1862 * @len: number of bytes to read
1863 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1865 * Whatever the actual numbers of bytes for address and dummy cycles are
1866 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1867 * followed by a 3-byte address and 8 dummy clock cycles.
1869 * Return: 0 on success, -errno otherwise.
1871 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1872 size_t len, void *buf)
1874 u8 addr_width, read_opcode, read_dummy;
1877 read_opcode = nor->read_opcode;
1878 addr_width = nor->addr_width;
1879 read_dummy = nor->read_dummy;
1881 nor->read_opcode = SPINOR_OP_RDSFDP;
1882 nor->addr_width = 3;
1883 nor->read_dummy = 8;
1886 ret = nor->read(nor, addr, len, (u8 *)buf);
1887 if (!ret || ret > len) {
1901 nor->read_opcode = read_opcode;
1902 nor->addr_width = addr_width;
1903 nor->read_dummy = read_dummy;
1908 /* Fast Read settings. */
1911 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1913 enum spi_nor_protocol proto)
1915 read->num_mode_clocks = (half >> 5) & 0x07;
1916 read->num_wait_states = (half >> 0) & 0x1f;
1917 read->opcode = (half >> 8) & 0xff;
1918 read->proto = proto;
1921 struct sfdp_bfpt_read {
1922 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1926 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1927 * whether the Fast Read x-y-z command is supported.
1929 u32 supported_dword;
1933 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1934 * encodes the op code, the number of mode clocks and the number of wait
1935 * states to be used by Fast Read x-y-z command.
1940 /* The SPI protocol for this Fast Read x-y-z command. */
1941 enum spi_nor_protocol proto;
1944 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1945 /* Fast Read 1-1-2 */
1947 SNOR_HWCAPS_READ_1_1_2,
1948 BFPT_DWORD(1), BIT(16), /* Supported bit */
1949 BFPT_DWORD(4), 0, /* Settings */
1953 /* Fast Read 1-2-2 */
1955 SNOR_HWCAPS_READ_1_2_2,
1956 BFPT_DWORD(1), BIT(20), /* Supported bit */
1957 BFPT_DWORD(4), 16, /* Settings */
1961 /* Fast Read 2-2-2 */
1963 SNOR_HWCAPS_READ_2_2_2,
1964 BFPT_DWORD(5), BIT(0), /* Supported bit */
1965 BFPT_DWORD(6), 16, /* Settings */
1969 /* Fast Read 1-1-4 */
1971 SNOR_HWCAPS_READ_1_1_4,
1972 BFPT_DWORD(1), BIT(22), /* Supported bit */
1973 BFPT_DWORD(3), 16, /* Settings */
1977 /* Fast Read 1-4-4 */
1979 SNOR_HWCAPS_READ_1_4_4,
1980 BFPT_DWORD(1), BIT(21), /* Supported bit */
1981 BFPT_DWORD(3), 0, /* Settings */
1985 /* Fast Read 4-4-4 */
1987 SNOR_HWCAPS_READ_4_4_4,
1988 BFPT_DWORD(5), BIT(4), /* Supported bit */
1989 BFPT_DWORD(7), 16, /* Settings */
1994 struct sfdp_bfpt_erase {
1996 * The half-word at offset <shift> in DWORD <dwoard> encodes the
1997 * op code and erase sector size to be used by Sector Erase commands.
2003 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
2004 /* Erase Type 1 in DWORD8 bits[15:0] */
2007 /* Erase Type 2 in DWORD8 bits[31:16] */
2008 {BFPT_DWORD(8), 16},
2010 /* Erase Type 3 in DWORD9 bits[15:0] */
2013 /* Erase Type 4 in DWORD9 bits[31:16] */
2014 {BFPT_DWORD(9), 16},
2017 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
2020 spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2021 const struct sfdp_parameter_header *bfpt_header,
2022 const struct sfdp_bfpt *bfpt,
2023 struct spi_nor_flash_parameter *params)
2025 if (nor->fixups && nor->fixups->post_bfpt)
2026 return nor->fixups->post_bfpt(nor, bfpt_header, bfpt, params);
2032 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
2033 * @nor: pointer to a 'struct spi_nor'
2034 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
2035 * the Basic Flash Parameter Table length and version
2036 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2039 * The Basic Flash Parameter Table is the main and only mandatory table as
2040 * defined by the SFDP (JESD216) specification.
2041 * It provides us with the total size (memory density) of the data array and
2042 * the number of address bytes for Fast Read, Page Program and Sector Erase
2044 * For Fast READ commands, it also gives the number of mode clock cycles and
2045 * wait states (regrouped in the number of dummy clock cycles) for each
2046 * supported instruction op code.
2047 * For Page Program, the page size is now available since JESD216 rev A, however
2048 * the supported instruction op codes are still not provided.
2049 * For Sector Erase commands, this table stores the supported instruction op
2050 * codes and the associated sector sizes.
2051 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
2052 * rev A. The QER bits encode the manufacturer dependent procedure to be
2053 * executed to set the Quad Enable (QE) bit in some internal register of the
2054 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
2055 * sending any Quad SPI command to the memory. Actually, setting the QE bit
2056 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
2057 * and IO3 hence enabling 4 (Quad) I/O lines.
2059 * Return: 0 on success, -errno otherwise.
2061 static int spi_nor_parse_bfpt(struct spi_nor *nor,
2062 const struct sfdp_parameter_header *bfpt_header,
2063 struct spi_nor_flash_parameter *params)
2065 struct mtd_info *mtd = &nor->mtd;
2066 struct sfdp_bfpt bfpt;
2072 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
2073 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
2076 /* Read the Basic Flash Parameter Table. */
2077 len = min_t(size_t, sizeof(bfpt),
2078 bfpt_header->length * sizeof(u32));
2079 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2080 memset(&bfpt, 0, sizeof(bfpt));
2081 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
2085 /* Fix endianness of the BFPT DWORDs. */
2086 for (i = 0; i < BFPT_DWORD_MAX; i++)
2087 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
2089 /* Number of address bytes. */
2090 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
2091 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
2092 nor->addr_width = 3;
2095 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
2096 nor->addr_width = 4;
2103 /* Flash Memory Density (in bits). */
2104 params->size = bfpt.dwords[BFPT_DWORD(2)];
2105 if (params->size & BIT(31)) {
2106 params->size &= ~BIT(31);
2109 * Prevent overflows on params->size. Anyway, a NOR of 2^64
2110 * bits is unlikely to exist so this error probably means
2111 * the BFPT we are reading is corrupted/wrong.
2113 if (params->size > 63)
2116 params->size = 1ULL << params->size;
2120 params->size >>= 3; /* Convert to bytes. */
2122 /* Fast Read settings. */
2123 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
2124 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
2125 struct spi_nor_read_command *read;
2127 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
2128 params->hwcaps.mask &= ~rd->hwcaps;
2132 params->hwcaps.mask |= rd->hwcaps;
2133 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
2134 read = ¶ms->reads[cmd];
2135 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
2136 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
2139 /* Sector Erase settings. */
2140 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
2141 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
2145 half = bfpt.dwords[er->dword] >> er->shift;
2146 erasesize = half & 0xff;
2148 /* erasesize == 0 means this Erase Type is not supported. */
2152 erasesize = 1U << erasesize;
2153 opcode = (half >> 8) & 0xff;
2154 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2155 if (erasesize == SZ_4K) {
2156 nor->erase_opcode = opcode;
2157 mtd->erasesize = erasesize;
2161 if (!mtd->erasesize || mtd->erasesize < erasesize) {
2162 nor->erase_opcode = opcode;
2163 mtd->erasesize = erasesize;
2167 /* Stop here if not JESD216 rev A or later. */
2168 if (bfpt_header->length == BFPT_DWORD_MAX_JESD216)
2169 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2172 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2173 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2174 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2175 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2176 params->page_size = 1U << params->page_size;
2178 /* Quad Enable Requirements. */
2179 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2180 case BFPT_DWORD15_QER_NONE:
2181 params->quad_enable = NULL;
2183 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2184 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2185 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2186 params->quad_enable = spansion_no_read_cr_quad_enable;
2189 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
2190 case BFPT_DWORD15_QER_SR1_BIT6:
2191 params->quad_enable = macronix_quad_enable;
2194 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2195 case BFPT_DWORD15_QER_SR2_BIT1:
2196 params->quad_enable = spansion_read_cr_quad_enable;
2200 dev_dbg(nor->dev, "BFPT QER reserved value used\n");
2204 /* Soft Reset support. */
2205 if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SOFT_RST)
2206 nor->flags |= SNOR_F_SOFT_RESET;
2208 /* Stop here if JESD216 rev B. */
2209 if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B)
2210 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2213 /* 8D-8D-8D command extension. */
2214 switch (bfpt.dwords[BFPT_DWORD(18)] & BFPT_DWORD18_CMD_EXT_MASK) {
2215 case BFPT_DWORD18_CMD_EXT_REP:
2216 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
2219 case BFPT_DWORD18_CMD_EXT_INV:
2220 nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
2223 case BFPT_DWORD18_CMD_EXT_RES:
2226 case BFPT_DWORD18_CMD_EXT_16B:
2227 dev_err(nor->dev, "16-bit opcodes not supported\n");
2231 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
2235 * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
2237 * @nor: pointer to a 'struct spi_nor'.
2238 * @param_header: pointer to the SFDP parameter header.
2240 * Return: 0 on success, -errno otherwise.
2243 spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
2244 const struct sfdp_parameter_header *param_header)
2250 size = param_header->length * sizeof(u32);
2251 addr = SFDP_PARAM_HEADER_PTP(param_header);
2253 nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
2254 if (!nor->manufacturer_sfdp)
2257 ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
2263 * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
2264 * @nor: pointer to a 'struct spi_nor'
2265 * @profile1_header: pointer to the 'struct sfdp_parameter_header' describing
2266 * the 4-Byte Address Instruction Table length and version.
2267 * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
2269 * Return: 0 on success, -errno otherwise.
2271 static int spi_nor_parse_profile1(struct spi_nor *nor,
2272 const struct sfdp_parameter_header *profile1_header,
2273 struct spi_nor_flash_parameter *params)
2275 u32 *table, opcode, addr;
2280 len = profile1_header->length * sizeof(*table);
2281 table = kmalloc(len, GFP_KERNEL);
2285 addr = SFDP_PARAM_HEADER_PTP(profile1_header);
2286 ret = spi_nor_read_sfdp(nor, addr, len, table);
2290 /* Fix endianness of the table DWORDs. */
2291 for (i = 0; i < profile1_header->length; i++)
2292 table[i] = le32_to_cpu(table[i]);
2294 /* Get 8D-8D-8D fast read opcode and dummy cycles. */
2295 opcode = FIELD_GET(PROFILE1_DWORD1_RD_FAST_CMD, table[0]);
2298 * We don't know what speed the controller is running at. Find the
2299 * dummy cycles for the fastest frequency the flash can run at to be
2300 * sure we are never short of dummy cycles. A value of 0 means the
2301 * frequency is not supported.
2303 * Default to PROFILE1_DUMMY_DEFAULT if we don't find anything, and let
2304 * flashes set the correct value if needed in their fixup hooks.
2306 dummy = FIELD_GET(PROFILE1_DWORD4_DUMMY_200MHZ, table[3]);
2308 dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_166MHZ, table[4]);
2310 dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_133MHZ, table[4]);
2312 dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_100MHZ, table[4]);
2314 dummy = PROFILE1_DUMMY_DEFAULT;
2316 /* Round up to an even value to avoid tripping controllers up. */
2317 dummy = ROUND_UP_TO(dummy, 2);
2319 /* Update the fast read settings. */
2320 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
2322 SNOR_PROTO_8_8_8_DTR);
2325 * Set the Read Status Register dummy cycles and dummy address bytes.
2327 if (table[0] & PROFILE1_DWORD1_RDSR_DUMMY)
2328 params->rdsr_dummy = 8;
2330 params->rdsr_dummy = 4;
2332 if (table[0] & PROFILE1_DWORD1_RDSR_ADDR_BYTES)
2333 params->rdsr_addr_nbytes = 4;
2335 params->rdsr_addr_nbytes = 0;
2343 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2344 * @nor: pointer to a 'struct spi_nor'
2345 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2348 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2349 * specification. This is a standard which tends to supported by almost all
2350 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2351 * runtime the main parameters needed to perform basic SPI flash operations such
2352 * as Fast Read, Page Program or Sector Erase commands.
2354 * Return: 0 on success, -errno otherwise.
2356 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2357 struct spi_nor_flash_parameter *params)
2359 const struct sfdp_parameter_header *param_header, *bfpt_header;
2360 struct sfdp_parameter_header *param_headers = NULL;
2361 struct sfdp_header header;
2365 /* Get the SFDP header. */
2366 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2370 /* Check the SFDP header version. */
2371 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2372 header.major != SFDP_JESD216_MAJOR)
2376 * Verify that the first and only mandatory parameter header is a
2377 * Basic Flash Parameter Table header as specified in JESD216.
2379 bfpt_header = &header.bfpt_header;
2380 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2381 bfpt_header->major != SFDP_JESD216_MAJOR)
2385 * Allocate memory then read all parameter headers with a single
2386 * Read SFDP command. These parameter headers will actually be parsed
2387 * twice: a first time to get the latest revision of the basic flash
2388 * parameter table, then a second time to handle the supported optional
2390 * Hence we read the parameter headers once for all to reduce the
2391 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2392 * because we don't need to keep these parameter headers: the allocated
2393 * memory is always released with kfree() before exiting this function.
2396 psize = header.nph * sizeof(*param_headers);
2398 param_headers = kmalloc(psize, GFP_KERNEL);
2402 err = spi_nor_read_sfdp(nor, sizeof(header),
2403 psize, param_headers);
2406 "failed to read SFDP parameter headers\n");
2412 * Check other parameter headers to get the latest revision of
2413 * the basic flash parameter table.
2415 for (i = 0; i < header.nph; i++) {
2416 param_header = ¶m_headers[i];
2418 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2419 param_header->major == SFDP_JESD216_MAJOR &&
2420 (param_header->minor > bfpt_header->minor ||
2421 (param_header->minor == bfpt_header->minor &&
2422 param_header->length > bfpt_header->length)))
2423 bfpt_header = param_header;
2426 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2430 /* Parse other parameter headers. */
2431 for (i = 0; i < header.nph; i++) {
2432 param_header = ¶m_headers[i];
2434 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2435 case SFDP_SECTOR_MAP_ID:
2437 "non-uniform erase sector maps are not supported yet.\n");
2441 err = spi_nor_parse_microchip_sfdp(nor, param_header);
2444 case SFDP_PROFILE1_ID:
2445 err = spi_nor_parse_profile1(nor, param_header, params);
2454 "Failed to parse optional parameter table: %04x\n",
2455 SFDP_PARAM_HEADER_ID(param_header));
2457 * Let's not drop all information we extracted so far
2458 * if optional table parsers fail. In case of failing,
2459 * each optional parser is responsible to roll back to
2460 * the previously known spi_nor data.
2467 kfree(param_headers);
2471 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2472 struct spi_nor_flash_parameter *params)
2476 #endif /* SPI_FLASH_SFDP_SUPPORT */
2479 * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
2480 * after SFDP has been parsed (is also called for SPI NORs that do not
2482 * @nor: pointer to a 'struct spi_nor'
2484 * Typically used to tweak various parameters that could not be extracted by
2485 * other means (i.e. when information provided by the SFDP/flash_info tables
2486 * are incomplete or wrong).
2488 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor,
2489 struct spi_nor_flash_parameter *params)
2491 if (nor->fixups && nor->fixups->post_sfdp)
2492 nor->fixups->post_sfdp(nor, params);
2495 static void spi_nor_default_init_fixups(struct spi_nor *nor)
2497 if (nor->fixups && nor->fixups->default_init)
2498 nor->fixups->default_init(nor);
2501 static int spi_nor_init_params(struct spi_nor *nor,
2502 const struct flash_info *info,
2503 struct spi_nor_flash_parameter *params)
2505 /* Set legacy flash parameters as default. */
2506 memset(params, 0, sizeof(*params));
2508 /* Set SPI NOR sizes. */
2509 params->size = info->sector_size * info->n_sectors;
2510 params->page_size = info->page_size;
2512 /* (Fast) Read settings. */
2513 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2514 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2515 0, 0, SPINOR_OP_READ,
2518 if (!(info->flags & SPI_NOR_NO_FR)) {
2519 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2520 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2521 0, 8, SPINOR_OP_READ_FAST,
2525 if (info->flags & SPI_NOR_DUAL_READ) {
2526 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2527 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2528 0, 8, SPINOR_OP_READ_1_1_2,
2532 if (info->flags & SPI_NOR_QUAD_READ) {
2533 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2534 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2535 0, 8, SPINOR_OP_READ_1_1_4,
2539 if (info->flags & SPI_NOR_OCTAL_READ) {
2540 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2541 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
2542 0, 8, SPINOR_OP_READ_1_1_8,
2546 if (info->flags & SPI_NOR_OCTAL_DTR_READ) {
2547 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2548 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
2549 0, 20, SPINOR_OP_READ_FAST,
2550 SNOR_PROTO_8_8_8_DTR);
2553 /* Page Program settings. */
2554 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2555 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2556 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2559 * Since xSPI Page Program opcode is backward compatible with
2560 * Legacy SPI, use Legacy SPI opcode there as well.
2562 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2563 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2565 if (info->flags & SPI_NOR_QUAD_READ) {
2566 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2567 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2568 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2571 /* Select the procedure to set the Quad Enable bit. */
2572 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2573 SNOR_HWCAPS_PP_QUAD)) {
2574 switch (JEDEC_MFR(info)) {
2575 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
2576 case SNOR_MFR_MACRONIX:
2578 params->quad_enable = macronix_quad_enable;
2582 case SNOR_MFR_MICRON:
2586 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2587 /* Kept only for backward compatibility purpose. */
2588 params->quad_enable = spansion_read_cr_quad_enable;
2594 spi_nor_default_init_fixups(nor);
2596 /* Override the parameters with data read from SFDP tables. */
2597 nor->addr_width = 0;
2598 nor->mtd.erasesize = 0;
2599 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2600 SPI_NOR_OCTAL_DTR_READ)) &&
2601 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2602 struct spi_nor_flash_parameter sfdp_params;
2604 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2605 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2606 nor->addr_width = 0;
2607 nor->mtd.erasesize = 0;
2609 memcpy(params, &sfdp_params, sizeof(*params));
2613 spi_nor_post_sfdp_fixups(nor, params);
2618 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2622 for (i = 0; i < size; i++)
2623 if (table[i][0] == (int)hwcaps)
2629 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2631 static const int hwcaps_read2cmd[][2] = {
2632 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2633 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2634 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2635 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2636 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2637 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2638 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2639 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2640 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2641 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2642 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2643 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2644 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2645 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2646 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2647 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },
2650 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2651 ARRAY_SIZE(hwcaps_read2cmd));
2654 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2656 static const int hwcaps_pp2cmd[][2] = {
2657 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2658 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2659 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2660 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2661 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2662 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2663 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2664 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },
2667 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2668 ARRAY_SIZE(hwcaps_pp2cmd));
2671 #ifdef CONFIG_SPI_FLASH_SMART_HWCAPS
2673 * spi_nor_check_op - check if the operation is supported by controller
2674 * @nor: pointer to a 'struct spi_nor'
2675 * @op: pointer to op template to be checked
2677 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2679 static int spi_nor_check_op(struct spi_nor *nor,
2680 struct spi_mem_op *op)
2683 * First test with 4 address bytes. The opcode itself might be a 3B
2684 * addressing opcode but we don't care, because SPI controller
2685 * implementation should not check the opcode, but just the sequence.
2687 op->addr.nbytes = 4;
2688 if (!spi_mem_supports_op(nor->spi, op)) {
2689 if (nor->mtd.size > SZ_16M)
2692 /* If flash size <= 16MB, 3 address bytes are sufficient */
2693 op->addr.nbytes = 3;
2694 if (!spi_mem_supports_op(nor->spi, op))
2702 * spi_nor_check_readop - check if the read op is supported by controller
2703 * @nor: pointer to a 'struct spi_nor'
2704 * @read: pointer to op template to be checked
2706 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2708 static int spi_nor_check_readop(struct spi_nor *nor,
2709 const struct spi_nor_read_command *read)
2711 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0),
2712 SPI_MEM_OP_ADDR(3, 0, 0),
2713 SPI_MEM_OP_DUMMY(1, 0),
2714 SPI_MEM_OP_DATA_IN(2, NULL, 0));
2716 spi_nor_setup_op(nor, &op, read->proto);
2718 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2719 op.dummy.buswidth / 8;
2720 if (spi_nor_protocol_is_dtr(nor->read_proto))
2721 op.dummy.nbytes *= 2;
2723 return spi_nor_check_op(nor, &op);
2727 * spi_nor_check_pp - check if the page program op is supported by controller
2728 * @nor: pointer to a 'struct spi_nor'
2729 * @pp: pointer to op template to be checked
2731 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2733 static int spi_nor_check_pp(struct spi_nor *nor,
2734 const struct spi_nor_pp_command *pp)
2736 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0),
2737 SPI_MEM_OP_ADDR(3, 0, 0),
2738 SPI_MEM_OP_NO_DUMMY,
2739 SPI_MEM_OP_DATA_OUT(2, NULL, 0));
2741 spi_nor_setup_op(nor, &op, pp->proto);
2743 return spi_nor_check_op(nor, &op);
2747 * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
2748 * controller capabilities
2749 * @nor: pointer to a 'struct spi_nor'
2750 * @params: pointer to the 'struct spi_nor_flash_parameter'
2751 * representing SPI NOR flash capabilities
2752 * @hwcaps: pointer to resulting capabilities after adjusting
2753 * according to controller and flash's capability
2755 * Discard caps based on what the SPI controller actually supports (using
2756 * spi_mem_supports_op()).
2759 spi_nor_adjust_hwcaps(struct spi_nor *nor,
2760 const struct spi_nor_flash_parameter *params,
2766 * Enable all caps by default. We will mask them after checking what's
2767 * really supported using spi_mem_supports_op().
2769 *hwcaps = SNOR_HWCAPS_ALL;
2771 /* X-X-X modes are not supported yet, mask them all. */
2772 *hwcaps &= ~SNOR_HWCAPS_X_X_X;
2775 * If the reset line is broken, we do not want to enter a stateful
2778 if (nor->flags & SNOR_F_BROKEN_RESET)
2779 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
2781 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2784 if (!(*hwcaps & BIT(cap)))
2787 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2789 spi_nor_check_readop(nor, ¶ms->reads[rdidx]))
2790 *hwcaps &= ~BIT(cap);
2792 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2796 if (spi_nor_check_pp(nor, ¶ms->page_programs[ppidx]))
2797 *hwcaps &= ~BIT(cap);
2802 * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
2803 * controller capabilities
2804 * @nor: pointer to a 'struct spi_nor'
2805 * @params: pointer to the 'struct spi_nor_flash_parameter'
2806 * representing SPI NOR flash capabilities
2807 * @hwcaps: pointer to resulting capabilities after adjusting
2808 * according to controller and flash's capability
2810 * Select caps based on what the SPI controller and SPI flash both support.
2813 spi_nor_adjust_hwcaps(struct spi_nor *nor,
2814 const struct spi_nor_flash_parameter *params,
2817 struct spi_slave *spi = nor->spi;
2818 u32 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2819 SNOR_HWCAPS_READ_4_4_4 |
2820 SNOR_HWCAPS_READ_8_8_8 |
2821 SNOR_HWCAPS_PP_4_4_4 |
2822 SNOR_HWCAPS_PP_8_8_8);
2823 u32 spi_hwcaps = (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |
2826 /* Get the hardware capabilities the SPI controller supports. */
2827 if (spi->mode & SPI_RX_OCTAL) {
2828 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_8;
2830 if (spi->mode & SPI_TX_OCTAL)
2831 spi_hwcaps |= (SNOR_HWCAPS_READ_1_8_8 |
2832 SNOR_HWCAPS_PP_1_1_8 |
2833 SNOR_HWCAPS_PP_1_8_8);
2834 } else if (spi->mode & SPI_RX_QUAD) {
2835 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_4;
2837 if (spi->mode & SPI_TX_QUAD)
2838 spi_hwcaps |= (SNOR_HWCAPS_READ_1_4_4 |
2839 SNOR_HWCAPS_PP_1_1_4 |
2840 SNOR_HWCAPS_PP_1_4_4);
2841 } else if (spi->mode & SPI_RX_DUAL) {
2842 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_2;
2844 if (spi->mode & SPI_TX_DUAL)
2845 spi_hwcaps |= SNOR_HWCAPS_READ_1_2_2;
2849 * Keep only the hardware capabilities supported by both the SPI
2850 * controller and the SPI flash memory.
2852 *hwcaps = spi_hwcaps & params->hwcaps.mask;
2853 if (*hwcaps & ignored_mask) {
2855 "SPI n-n-n protocols are not supported yet.\n");
2856 *hwcaps &= ~ignored_mask;
2859 #endif /* CONFIG_SPI_FLASH_SMART_HWCAPS */
2861 static int spi_nor_select_read(struct spi_nor *nor,
2862 const struct spi_nor_flash_parameter *params,
2865 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2866 const struct spi_nor_read_command *read;
2871 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2875 read = ¶ms->reads[cmd];
2876 nor->read_opcode = read->opcode;
2877 nor->read_proto = read->proto;
2880 * In the spi-nor framework, we don't need to make the difference
2881 * between mode clock cycles and wait state clock cycles.
2882 * Indeed, the value of the mode clock cycles is used by a QSPI
2883 * flash memory to know whether it should enter or leave its 0-4-4
2884 * (Continuous Read / XIP) mode.
2885 * eXecution In Place is out of the scope of the mtd sub-system.
2886 * Hence we choose to merge both mode and wait state clock cycles
2887 * into the so called dummy clock cycles.
2889 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2893 static int spi_nor_select_pp(struct spi_nor *nor,
2894 const struct spi_nor_flash_parameter *params,
2897 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2898 const struct spi_nor_pp_command *pp;
2903 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2907 pp = ¶ms->page_programs[cmd];
2908 nor->program_opcode = pp->opcode;
2909 nor->write_proto = pp->proto;
2913 static int spi_nor_select_erase(struct spi_nor *nor,
2914 const struct flash_info *info)
2916 struct mtd_info *mtd = &nor->mtd;
2918 /* Do nothing if already configured from SFDP. */
2922 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2923 /* prefer "small sector" erase if possible */
2924 if (info->flags & SECT_4K) {
2925 nor->erase_opcode = SPINOR_OP_BE_4K;
2926 mtd->erasesize = 4096;
2927 } else if (info->flags & SECT_4K_PMC) {
2928 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2929 mtd->erasesize = 4096;
2933 nor->erase_opcode = SPINOR_OP_SE;
2934 mtd->erasesize = info->sector_size;
2939 static int spi_nor_default_setup(struct spi_nor *nor,
2940 const struct flash_info *info,
2941 const struct spi_nor_flash_parameter *params)
2944 bool enable_quad_io;
2947 spi_nor_adjust_hwcaps(nor, params, &shared_mask);
2949 /* Select the (Fast) Read command. */
2950 err = spi_nor_select_read(nor, params, shared_mask);
2953 "can't select read settings supported by both the SPI controller and memory.\n");
2957 /* Select the Page Program command. */
2958 err = spi_nor_select_pp(nor, params, shared_mask);
2961 "can't select write settings supported by both the SPI controller and memory.\n");
2965 /* Select the Sector Erase command. */
2966 err = spi_nor_select_erase(nor, info);
2969 "can't select erase settings supported by both the SPI controller and memory.\n");
2973 /* Enable Quad I/O if needed. */
2974 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2975 spi_nor_get_protocol_width(nor->write_proto) == 4);
2976 if (enable_quad_io && params->quad_enable)
2977 nor->quad_enable = params->quad_enable;
2979 nor->quad_enable = NULL;
2984 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2985 const struct spi_nor_flash_parameter *params)
2990 return nor->setup(nor, info, params);
2993 #ifdef CONFIG_SPI_FLASH_S28HS512T
2995 * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
2996 * @nor: pointer to a 'struct spi_nor'
2998 * This also sets the memory access latency cycles to 24 to allow the flash to
2999 * run at up to 200MHz.
3001 * Return: 0 on success, -errno otherwise.
3003 static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
3005 struct spi_mem_op op;
3010 /* Use 24 dummy cycles for memory array reads. */
3011 ret = write_enable(nor);
3015 buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
3016 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
3017 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1),
3018 SPI_MEM_OP_NO_DUMMY,
3019 SPI_MEM_OP_DATA_OUT(1, &buf, 1));
3020 ret = spi_mem_exec_op(nor->spi, &op);
3023 "failed to set default memory latency value: %d\n",
3027 ret = spi_nor_wait_till_ready(nor);
3031 nor->read_dummy = 24;
3033 /* Set the octal and DTR enable bits. */
3034 ret = write_enable(nor);
3038 buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
3039 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
3040 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1),
3041 SPI_MEM_OP_NO_DUMMY,
3042 SPI_MEM_OP_DATA_OUT(1, &buf, 1));
3043 ret = spi_mem_exec_op(nor->spi, &op);
3045 dev_warn(nor->dev, "Failed to enable octal DTR mode\n");
3052 static int s28hs512t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
3054 /* Factory default configuration: 32 x 4 KiB sectors at bottom. */
3055 return spansion_erase_non_uniform(nor, addr, SPINOR_OP_S28_SE_4K,
3059 static int s28hs512t_setup(struct spi_nor *nor, const struct flash_info *info,
3060 const struct spi_nor_flash_parameter *params)
3062 struct spi_mem_op op;
3067 ret = spi_nor_wait_till_ready(nor);
3072 * Check CFR3V to check if non-uniform sector mode is selected. If it
3073 * is, set the erase hook to the non-uniform erase procedure.
3075 op = (struct spi_mem_op)
3076 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
3077 SPI_MEM_OP_ADDR(addr_width,
3078 SPINOR_REG_CYPRESS_CFR3V, 1),
3079 SPI_MEM_OP_NO_DUMMY,
3080 SPI_MEM_OP_DATA_IN(1, &buf, 1));
3082 ret = spi_mem_exec_op(nor->spi, &op);
3086 if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT))
3087 nor->erase = s28hs512t_erase_non_uniform;
3089 return spi_nor_default_setup(nor, info, params);
3092 static void s28hs512t_default_init(struct spi_nor *nor)
3094 nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
3095 nor->setup = s28hs512t_setup;
3098 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor,
3099 struct spi_nor_flash_parameter *params)
3102 * On older versions of the flash the xSPI Profile 1.0 table has the
3103 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
3105 if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
3106 params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
3107 SPINOR_OP_CYPRESS_RD_FAST;
3109 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
3111 /* This flash is also missing the 4-byte Page Program opcode bit. */
3112 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
3113 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
3115 * Since xSPI Page Program opcode is backward compatible with
3116 * Legacy SPI, use Legacy SPI opcode there as well.
3118 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
3119 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
3122 * The xSPI Profile 1.0 table advertises the number of additional
3123 * address bytes needed for Read Status Register command as 0 but the
3124 * actual value for that is 4.
3126 params->rdsr_addr_nbytes = 4;
3129 static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
3130 const struct sfdp_parameter_header *bfpt_header,
3131 const struct sfdp_bfpt *bfpt,
3132 struct spi_nor_flash_parameter *params)
3134 struct spi_mem_op op;
3140 * The BFPT table advertises a 512B page size but the page size is
3141 * actually configurable (with the default being 256B). Read from
3142 * CFR3V[4] and set the correct size.
3144 op = (struct spi_mem_op)
3145 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
3146 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR3V, 1),
3147 SPI_MEM_OP_NO_DUMMY,
3148 SPI_MEM_OP_DATA_IN(1, &buf, 1));
3149 ret = spi_mem_exec_op(nor->spi, &op);
3153 if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
3154 params->page_size = 512;
3156 params->page_size = 256;
3159 * The BFPT advertises that it supports 4k erases, and the datasheet
3160 * says the same. But 4k erases did not work when testing. So, use 256k
3163 nor->erase_opcode = SPINOR_OP_SE_4B;
3164 nor->mtd.erasesize = 0x40000;
3169 static struct spi_nor_fixups s28hs512t_fixups = {
3170 .default_init = s28hs512t_default_init,
3171 .post_sfdp = s28hs512t_post_sfdp_fixup,
3172 .post_bfpt = s28hs512t_post_bfpt_fixup,
3174 #endif /* CONFIG_SPI_FLASH_S28HS512T */
3176 #ifdef CONFIG_SPI_FLASH_MT35XU
3177 static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
3179 struct spi_mem_op op;
3184 /* Set dummy cycles for Fast Read to the default of 20. */
3185 ret = write_enable(nor);
3190 op = (struct spi_mem_op)
3191 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
3192 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR1V, 1),
3193 SPI_MEM_OP_NO_DUMMY,
3194 SPI_MEM_OP_DATA_OUT(1, &buf, 1));
3195 ret = spi_mem_exec_op(nor->spi, &op);
3199 ret = spi_nor_wait_till_ready(nor);
3203 nor->read_dummy = 20;
3205 ret = write_enable(nor);
3209 buf = SPINOR_MT_OCT_DTR;
3210 op = (struct spi_mem_op)
3211 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
3212 SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR0V, 1),
3213 SPI_MEM_OP_NO_DUMMY,
3214 SPI_MEM_OP_DATA_OUT(1, &buf, 1));
3215 ret = spi_mem_exec_op(nor->spi, &op);
3217 dev_err(nor->dev, "Failed to enable octal DTR mode\n");
3224 static void mt35xu512aba_default_init(struct spi_nor *nor)
3226 nor->octal_dtr_enable = spi_nor_micron_octal_dtr_enable;
3229 static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor,
3230 struct spi_nor_flash_parameter *params)
3232 /* Set the Fast Read settings. */
3233 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
3234 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
3235 0, 20, SPINOR_OP_MT_DTR_RD,
3236 SNOR_PROTO_8_8_8_DTR);
3238 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
3240 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
3241 params->rdsr_dummy = 8;
3242 params->rdsr_addr_nbytes = 0;
3245 * The BFPT quad enable field is set to a reserved value so the quad
3246 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
3249 params->quad_enable = NULL;
3252 static struct spi_nor_fixups mt35xu512aba_fixups = {
3253 .default_init = mt35xu512aba_default_init,
3254 .post_sfdp = mt35xu512aba_post_sfdp_fixup,
3256 #endif /* CONFIG_SPI_FLASH_MT35XU */
3258 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
3259 * @nor: pointer to a 'struct spi_nor'
3261 * Return: 0 on success, -errno otherwise.
3263 static int spi_nor_octal_dtr_enable(struct spi_nor *nor)
3267 if (!nor->octal_dtr_enable)
3270 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
3271 nor->write_proto == SNOR_PROTO_8_8_8_DTR))
3274 ret = nor->octal_dtr_enable(nor);
3278 nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
3283 static int spi_nor_init(struct spi_nor *nor)
3287 err = spi_nor_octal_dtr_enable(nor);
3289 dev_dbg(nor->dev, "Octal DTR mode not supported\n");
3294 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
3295 * with the software protection bits set
3297 if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) &&
3298 (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
3299 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
3300 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
3301 nor->info->flags & SPI_NOR_HAS_LOCK)) {
3304 spi_nor_wait_till_ready(nor);
3307 if (nor->quad_enable) {
3308 err = nor->quad_enable(nor);
3310 dev_dbg(nor->dev, "quad mode not supported\n");
3315 if (nor->addr_width == 4 &&
3316 !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) &&
3317 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
3318 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
3320 * If the RESET# pin isn't hooked up properly, or the system
3321 * otherwise doesn't perform a reset command in the boot
3322 * sequence, it's impossible to 100% protect against unexpected
3323 * reboots (e.g., crashes). Warn the user (or hopefully, system
3324 * designer) that this is bad.
3326 if (nor->flags & SNOR_F_BROKEN_RESET)
3327 debug("enabling reset hack; may not recover from unexpected reboots\n");
3328 set_4byte(nor, nor->info, 1);
3334 #ifdef CONFIG_SPI_FLASH_SOFT_RESET
3336 * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence
3337 * @nor: the spi_nor structure
3339 * This function can be used to switch from Octal DTR mode to legacy mode on a
3340 * flash that supports it. The soft reset is executed in Octal DTR mode.
3342 * Return: 0 for success, -errno for failure.
3344 static int spi_nor_soft_reset(struct spi_nor *nor)
3346 struct spi_mem_op op;
3348 enum spi_nor_cmd_ext ext;
3350 ext = nor->cmd_ext_type;
3351 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
3353 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
3354 SPI_MEM_OP_NO_DUMMY,
3356 SPI_MEM_OP_NO_DATA);
3357 spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
3358 ret = spi_mem_exec_op(nor->spi, &op);
3360 dev_warn(nor->dev, "Software reset enable failed: %d\n", ret);
3364 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0),
3365 SPI_MEM_OP_NO_DUMMY,
3367 SPI_MEM_OP_NO_DATA);
3368 spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
3369 ret = spi_mem_exec_op(nor->spi, &op);
3371 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
3376 * Software Reset is not instant, and the delay varies from flash to
3377 * flash. Looking at a few flashes, most range somewhere below 100
3378 * microseconds. So, wait for 200ms just to be sure.
3380 udelay(SPI_NOR_SRST_SLEEP_LEN);
3383 nor->cmd_ext_type = ext;
3386 #endif /* CONFIG_SPI_FLASH_SOFT_RESET */
3388 int spi_nor_remove(struct spi_nor *nor)
3390 #ifdef CONFIG_SPI_FLASH_SOFT_RESET
3391 if (nor->info->flags & SPI_NOR_OCTAL_DTR_READ &&
3392 nor->flags & SNOR_F_SOFT_RESET)
3393 return spi_nor_soft_reset(nor);
3399 void spi_nor_set_fixups(struct spi_nor *nor)
3401 #ifdef CONFIG_SPI_FLASH_S28HS512T
3402 if (!strcmp(nor->info->name, "s28hs512t"))
3403 nor->fixups = &s28hs512t_fixups;
3406 #ifdef CONFIG_SPI_FLASH_MT35XU
3407 if (!strcmp(nor->info->name, "mt35xu512aba"))
3408 nor->fixups = &mt35xu512aba_fixups;
3412 int spi_nor_scan(struct spi_nor *nor)
3414 struct spi_nor_flash_parameter params;
3415 const struct flash_info *info = NULL;
3416 struct mtd_info *mtd = &nor->mtd;
3417 struct spi_slave *spi = nor->spi;
3420 /* Reset SPI protocol for all commands. */
3421 nor->reg_proto = SNOR_PROTO_1_1_1;
3422 nor->read_proto = SNOR_PROTO_1_1_1;
3423 nor->write_proto = SNOR_PROTO_1_1_1;
3424 nor->read = spi_nor_read_data;
3425 nor->write = spi_nor_write_data;
3426 nor->read_reg = spi_nor_read_reg;
3427 nor->write_reg = spi_nor_write_reg;
3429 nor->setup = spi_nor_default_setup;
3431 #ifdef CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT
3433 * When the flash is handed to us in a stateful mode like 8D-8D-8D, it
3434 * is difficult to detect the mode the flash is in. One option is to
3435 * read SFDP in all modes and see which one gives the correct "SFDP"
3436 * signature, but not all flashes support SFDP in 8D-8D-8D mode.
3438 * Further, even if you detect the mode of the flash via SFDP, you
3439 * still have the problem of actually reading the ID. The Read ID
3440 * command is not standardized across flash vendors. Flashes can have
3441 * different dummy cycles needed for reading the ID. Some flashes even
3442 * expect a 4-byte dummy address with the Read ID command. All this
3443 * information cannot be obtained from the SFDP table.
3445 * So, perform a Software Reset sequence before reading the ID and
3446 * initializing the flash. A Soft Reset will bring back the flash in
3447 * its default protocol mode assuming no non-volatile configuration was
3448 * set. This will let us detect the flash even if ROM hands it to us in
3451 * To accommodate cases where there is more than one flash on a board,
3452 * and only one of them needs a soft reset, failure to reset is not
3453 * made fatal, and we still try to read ID if possible.
3455 spi_nor_soft_reset(nor);
3456 #endif /* CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT */
3458 info = spi_nor_read_id(nor);
3459 if (IS_ERR_OR_NULL(info))
3463 spi_nor_set_fixups(nor);
3465 /* Parse the Serial Flash Discoverable Parameters table. */
3466 ret = spi_nor_init_params(nor, info, ¶ms);
3471 mtd->name = info->name;
3472 mtd->dev = nor->dev;
3474 mtd->type = MTD_NORFLASH;
3476 mtd->flags = MTD_CAP_NORFLASH;
3477 mtd->size = params.size;
3478 mtd->_erase = spi_nor_erase;
3479 mtd->_read = spi_nor_read;
3480 mtd->_write = spi_nor_write;
3482 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
3483 /* NOR protection support for STmicro/Micron chips and similar */
3484 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
3485 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
3486 JEDEC_MFR(info) == SNOR_MFR_SST ||
3487 info->flags & SPI_NOR_HAS_LOCK) {
3488 nor->flash_lock = stm_lock;
3489 nor->flash_unlock = stm_unlock;
3490 nor->flash_is_locked = stm_is_locked;
3494 #ifdef CONFIG_SPI_FLASH_SST
3496 * sst26 series block protection implementation differs from other
3499 if (info->flags & SPI_NOR_HAS_SST26LOCK) {
3500 nor->flash_lock = sst26_lock;
3501 nor->flash_unlock = sst26_unlock;
3502 nor->flash_is_locked = sst26_is_locked;
3506 if (info->flags & USE_FSR)
3507 nor->flags |= SNOR_F_USE_FSR;
3508 if (info->flags & SPI_NOR_HAS_TB)
3509 nor->flags |= SNOR_F_HAS_SR_TB;
3510 if (info->flags & NO_CHIP_ERASE)
3511 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
3512 if (info->flags & USE_CLSR)
3513 nor->flags |= SNOR_F_USE_CLSR;
3515 if (info->flags & SPI_NOR_NO_ERASE)
3516 mtd->flags |= MTD_NO_ERASE;
3518 nor->page_size = params.page_size;
3519 mtd->writebufsize = nor->page_size;
3521 /* Some devices cannot do fast-read, no matter what DT tells us */
3522 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
3523 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
3526 * Configure the SPI memory:
3527 * - select op codes for (Fast) Read, Page Program and Sector Erase.
3528 * - set the number of dummy cycles (mode cycles + wait states).
3529 * - set the SPI protocols for register and memory accesses.
3530 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
3532 ret = spi_nor_setup(nor, info, ¶ms);
3536 if (spi_nor_protocol_is_dtr(nor->read_proto)) {
3537 /* Always use 4-byte addresses in DTR mode. */
3538 nor->addr_width = 4;
3539 } else if (nor->addr_width) {
3540 /* already configured from SFDP */
3541 } else if (info->addr_width) {
3542 nor->addr_width = info->addr_width;
3544 nor->addr_width = 3;
3547 if (nor->addr_width == 3 && mtd->size > SZ_16M) {
3548 #ifndef CONFIG_SPI_FLASH_BAR
3549 /* enable 4-byte addressing if the device exceeds 16MiB */
3550 nor->addr_width = 4;
3551 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
3552 info->flags & SPI_NOR_4B_OPCODES)
3553 spi_nor_set_4byte_opcodes(nor, info);
3555 /* Configure the BAR - discover bank cmds and read current bank */
3556 nor->addr_width = 3;
3557 ret = read_bar(nor, info);
3563 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
3564 dev_dbg(nor->dev, "address width is too large: %u\n",
3569 /* Send all the required SPI flash commands to initialize device */
3570 ret = spi_nor_init(nor);
3574 nor->rdsr_dummy = params.rdsr_dummy;
3575 nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes;
3576 nor->name = mtd->name;
3577 nor->size = mtd->size;
3578 nor->erase_size = mtd->erasesize;
3579 nor->sector_size = mtd->erasesize;
3581 #ifndef CONFIG_SPL_BUILD
3582 printf("SF: Detected %s with page size ", nor->name);
3583 print_size(nor->page_size, ", erase size ");
3584 print_size(nor->erase_size, ", total ");
3585 print_size(nor->size, "");
3592 /* U-Boot specific functions, need to extend MTD to support these */
3593 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
3595 int sr = read_sr(nor);
3600 return (sr >> 2) & 7;