1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
16 #include <dm/device_compat.h>
17 #include <dm/devres.h>
18 #include <linux/bitops.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/math64.h>
23 #include <linux/sizes.h>
25 #include <linux/mtd/mtd.h>
26 #include <linux/mtd/spi-nor.h>
30 #include "sf_internal.h"
32 /* Define max times to check status register before we give up. */
35 * For everything but full-chip erase; probably could be much smaller, but kept
36 * around for safety for now
39 #define HZ CONFIG_SYS_HZ
41 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
43 struct sfdp_parameter_header {
47 u8 length; /* in double words */
48 u8 parameter_table_pointer[3]; /* byte address */
52 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
53 #define SFDP_PARAM_HEADER_PTP(p) \
54 (((p)->parameter_table_pointer[2] << 16) | \
55 ((p)->parameter_table_pointer[1] << 8) | \
56 ((p)->parameter_table_pointer[0] << 0))
58 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
59 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
60 #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
62 #define SFDP_SIGNATURE 0x50444653U
63 #define SFDP_JESD216_MAJOR 1
64 #define SFDP_JESD216_MINOR 0
65 #define SFDP_JESD216A_MINOR 5
66 #define SFDP_JESD216B_MINOR 6
69 u32 signature; /* Ox50444653U <=> "SFDP" */
72 u8 nph; /* 0-base number of parameter headers */
75 /* Basic Flash Parameter Table. */
76 struct sfdp_parameter_header bfpt_header;
79 /* Basic Flash Parameter Table */
82 * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs.
83 * They are indexed from 1 but C arrays are indexed from 0.
85 #define BFPT_DWORD(i) ((i) - 1)
86 #define BFPT_DWORD_MAX 20
88 /* The first version of JESB216 defined only 9 DWORDs. */
89 #define BFPT_DWORD_MAX_JESD216 9
90 #define BFPT_DWORD_MAX_JESD216B 16
93 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
94 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
95 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
96 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
97 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
98 #define BFPT_DWORD1_DTR BIT(19)
99 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
100 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
101 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
104 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
105 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
108 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
109 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
114 * (from JESD216 rev B)
115 * Quad Enable Requirements (QER):
116 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
117 * reads based on instruction. DQ3/HOLD# functions are hold during
119 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
120 * two data bytes where bit 1 of the second byte is one.
122 * Writing only one byte to the status register has the side-effect of
123 * clearing status register 2, including the QE bit. The 100b code is
124 * used if writing one byte to the status register does not modify
126 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
127 * one data byte where bit 6 is one.
129 * - 011b: QE is bit 7 of status register 2. It is set via Write status
130 * register 2 instruction 3Eh with one data byte where bit 7 is one.
132 * The status register 2 is read using instruction 3Fh.
133 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
134 * two data bytes where bit 1 of the second byte is one.
136 * In contrast to the 001b code, writing one byte to the status
137 * register does not modify status register 2.
138 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
139 * Read Status instruction 05h. Status register2 is read using
140 * instruction 35h. QE is set via Writ Status instruction 01h with
141 * two data bytes where bit 1 of the second byte is one.
144 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
145 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
146 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
147 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
148 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
149 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
150 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
153 u32 dwords[BFPT_DWORD_MAX];
157 * struct spi_nor_fixups - SPI NOR fixup hooks
158 * @default_init: called after default flash parameters init. Used to tweak
159 * flash parameters when information provided by the flash_info
160 * table is incomplete or wrong.
161 * @post_bfpt: called after the BFPT table has been parsed
162 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
163 * that do not support RDSFDP). Typically used to tweak various
164 * parameters that could not be extracted by other means (i.e.
165 * when information provided by the SFDP/flash_info tables are
166 * incomplete or wrong).
168 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
169 * table is broken or not available.
171 struct spi_nor_fixups {
172 void (*default_init)(struct spi_nor *nor);
173 int (*post_bfpt)(struct spi_nor *nor,
174 const struct sfdp_parameter_header *bfpt_header,
175 const struct sfdp_bfpt *bfpt,
176 struct spi_nor_flash_parameter *params);
177 void (*post_sfdp)(struct spi_nor *nor,
178 struct spi_nor_flash_parameter *params);
182 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
184 * @nor: pointer to a 'struct spi_nor'
185 * @op: pointer to the 'struct spi_mem_op' whose properties
186 * need to be initialized.
188 * Right now, only "repeat" and "invert" are supported.
190 * Return: The opcode extension.
192 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
193 const struct spi_mem_op *op)
195 switch (nor->cmd_ext_type) {
196 case SPI_NOR_EXT_INVERT:
197 return ~op->cmd.opcode;
199 case SPI_NOR_EXT_REPEAT:
200 return op->cmd.opcode;
203 dev_dbg(nor->dev, "Unknown command extension type\n");
209 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
210 * @nor: pointer to a 'struct spi_nor'
211 * @op: pointer to the 'struct spi_mem_op' whose properties
212 * need to be initialized.
213 * @proto: the protocol from which the properties need to be set.
215 static void spi_nor_setup_op(const struct spi_nor *nor,
216 struct spi_mem_op *op,
217 const enum spi_nor_protocol proto)
221 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
224 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
226 if (op->dummy.nbytes)
227 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
230 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
232 if (spi_nor_protocol_is_dtr(proto)) {
234 * spi-mem supports mixed DTR modes, but right now we can only
235 * have all phases either DTR or STR. IOW, spi-mem can have
236 * something like 4S-4D-4D, but spi-nor can't. So, set all 4
237 * phases to either DTR or STR.
239 op->cmd.dtr = op->addr.dtr = op->dummy.dtr =
242 /* 2 bytes per clock cycle in DTR mode. */
243 op->dummy.nbytes *= 2;
245 ext = spi_nor_get_cmd_ext(nor, op);
246 op->cmd.opcode = (op->cmd.opcode << 8) | ext;
251 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
254 if (op->data.dir == SPI_MEM_DATA_IN)
255 op->data.buf.in = buf;
257 op->data.buf.out = buf;
258 return spi_mem_exec_op(nor->spi, op);
261 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
263 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 0),
266 SPI_MEM_OP_DATA_IN(len, NULL, 0));
269 spi_nor_setup_op(nor, &op, nor->reg_proto);
271 ret = spi_nor_read_write_reg(nor, &op, val);
273 dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
278 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
280 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),
283 SPI_MEM_OP_DATA_OUT(len, NULL, 0));
285 spi_nor_setup_op(nor, &op, nor->reg_proto);
288 op.data.dir = SPI_MEM_NO_DATA;
290 return spi_nor_read_write_reg(nor, &op, buf);
293 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
296 struct spi_mem_op op =
297 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
298 SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
299 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
300 SPI_MEM_OP_DATA_IN(len, buf, 0));
301 size_t remaining = len;
304 spi_nor_setup_op(nor, &op, nor->read_proto);
306 /* convert the dummy cycles to the number of bytes */
307 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
308 if (spi_nor_protocol_is_dtr(nor->read_proto))
309 op.dummy.nbytes *= 2;
312 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
313 ret = spi_mem_adjust_op_size(nor->spi, &op);
317 ret = spi_mem_exec_op(nor->spi, &op);
321 op.addr.val += op.data.nbytes;
322 remaining -= op.data.nbytes;
323 op.data.buf.in += op.data.nbytes;
329 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
332 struct spi_mem_op op =
333 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
334 SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
336 SPI_MEM_OP_DATA_OUT(len, buf, 0));
339 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
342 spi_nor_setup_op(nor, &op, nor->write_proto);
344 ret = spi_mem_adjust_op_size(nor->spi, &op);
347 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
349 ret = spi_mem_exec_op(nor->spi, &op);
353 return op.data.nbytes;
357 * Read the status register, returning its value in the location
358 * Return the status register value.
359 * Returns negative if error occurred.
361 static int read_sr(struct spi_nor *nor)
366 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
368 pr_debug("error %d reading SR\n", (int)ret);
376 * Read the flag status register, returning its value in the location
377 * Return the status register value.
378 * Returns negative if error occurred.
380 static int read_fsr(struct spi_nor *nor)
385 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
387 pr_debug("error %d reading FSR\n", ret);
395 * Read configuration register, returning its value in the
396 * location. Return the configuration register value.
397 * Returns negative if error occurred.
399 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
400 static int read_cr(struct spi_nor *nor)
405 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
407 dev_dbg(nor->dev, "error %d reading CR\n", ret);
416 * Write status register 1 byte
417 * Returns negative if error occurred.
419 static int write_sr(struct spi_nor *nor, u8 val)
421 nor->cmd_buf[0] = val;
422 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
426 * Set write enable latch with Write Enable command.
427 * Returns negative if error occurred.
429 static int write_enable(struct spi_nor *nor)
431 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
435 * Send write disable instruction to the chip.
437 static int write_disable(struct spi_nor *nor)
439 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
442 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
447 #ifndef CONFIG_SPI_FLASH_BAR
448 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
452 for (i = 0; i < size; i++)
453 if (table[i][0] == opcode)
456 /* No conversion found, keep input op code. */
460 static u8 spi_nor_convert_3to4_read(u8 opcode)
462 static const u8 spi_nor_3to4_read[][2] = {
463 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
464 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
465 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
466 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
467 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
468 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
469 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
470 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
472 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
473 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
474 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
477 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
478 ARRAY_SIZE(spi_nor_3to4_read));
481 static u8 spi_nor_convert_3to4_program(u8 opcode)
483 static const u8 spi_nor_3to4_program[][2] = {
484 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
485 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
486 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
487 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
488 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
491 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
492 ARRAY_SIZE(spi_nor_3to4_program));
495 static u8 spi_nor_convert_3to4_erase(u8 opcode)
497 static const u8 spi_nor_3to4_erase[][2] = {
498 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
499 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
500 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
503 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
504 ARRAY_SIZE(spi_nor_3to4_erase));
507 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
508 const struct flash_info *info)
510 /* Do some manufacturer fixups first */
511 switch (JEDEC_MFR(info)) {
512 case SNOR_MFR_SPANSION:
513 /* No small sector erase for 4-byte command set */
514 nor->erase_opcode = SPINOR_OP_SE;
515 nor->mtd.erasesize = info->sector_size;
522 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
523 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
524 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
526 #endif /* !CONFIG_SPI_FLASH_BAR */
528 /* Enable/disable 4-byte addressing mode. */
529 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
533 bool need_wren = false;
536 switch (JEDEC_MFR(info)) {
538 case SNOR_MFR_MICRON:
539 /* Some Micron need WREN command; all will accept it */
542 case SNOR_MFR_MACRONIX:
543 case SNOR_MFR_WINBOND:
547 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
548 status = nor->write_reg(nor, cmd, NULL, 0);
552 if (!status && !enable &&
553 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
555 * On Winbond W25Q256FV, leaving 4byte mode causes
556 * the Extended Address Register to be set to 1, so all
557 * 3-byte-address reads come from the second 16M.
558 * We must clear the register to enable normal behavior.
562 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
569 nor->cmd_buf[0] = enable << 7;
570 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
574 static int spi_nor_sr_ready(struct spi_nor *nor)
576 int sr = read_sr(nor);
581 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
583 dev_dbg(nor->dev, "Erase Error occurred\n");
585 dev_dbg(nor->dev, "Programming Error occurred\n");
587 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
591 return !(sr & SR_WIP);
594 static int spi_nor_fsr_ready(struct spi_nor *nor)
596 int fsr = read_fsr(nor);
601 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
603 dev_err(nor->dev, "Erase operation failed.\n");
605 dev_err(nor->dev, "Program operation failed.\n");
607 if (fsr & FSR_PT_ERR)
609 "Attempted to modify a protected sector.\n");
611 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
615 return fsr & FSR_READY;
618 static int spi_nor_ready(struct spi_nor *nor)
622 sr = spi_nor_sr_ready(nor);
625 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
632 * Service routine to read status register until ready, or timeout occurs.
633 * Returns non-zero if error.
635 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
636 unsigned long timeout)
638 unsigned long timebase;
641 timebase = get_timer(0);
643 while (get_timer(timebase) < timeout) {
644 ret = spi_nor_ready(nor);
651 dev_err(nor->dev, "flash operation timed out\n");
656 static int spi_nor_wait_till_ready(struct spi_nor *nor)
658 return spi_nor_wait_till_ready_with_timeout(nor,
659 DEFAULT_READY_WAIT_JIFFIES);
662 #ifdef CONFIG_SPI_FLASH_BAR
664 * This "clean_bar" is necessary in a situation when one was accessing
665 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
667 * After it the BA24 bit shall be cleared to allow access to correct
668 * memory region after SW reset (by calling "reset" command).
670 * Otherwise, the BA24 bit may be left set and then after reset, the
671 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
673 static int clean_bar(struct spi_nor *nor)
675 u8 cmd, bank_sel = 0;
677 if (nor->bank_curr == 0)
679 cmd = nor->bank_write_cmd;
683 return nor->write_reg(nor, cmd, &bank_sel, 1);
686 static int write_bar(struct spi_nor *nor, u32 offset)
691 bank_sel = offset / SZ_16M;
692 if (bank_sel == nor->bank_curr)
695 cmd = nor->bank_write_cmd;
697 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
699 debug("SF: fail to write bank register\n");
704 nor->bank_curr = bank_sel;
705 return nor->bank_curr;
708 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
713 switch (JEDEC_MFR(info)) {
714 case SNOR_MFR_SPANSION:
715 nor->bank_read_cmd = SPINOR_OP_BRRD;
716 nor->bank_write_cmd = SPINOR_OP_BRWR;
719 nor->bank_read_cmd = SPINOR_OP_RDEAR;
720 nor->bank_write_cmd = SPINOR_OP_WREAR;
723 ret = nor->read_reg(nor, nor->bank_read_cmd,
726 debug("SF: fail to read bank addr register\n");
729 nor->bank_curr = curr_bank;
736 * Initiate the erasure of a single sector
738 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
740 struct spi_mem_op op =
741 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
742 SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
746 spi_nor_setup_op(nor, &op, nor->write_proto);
749 return nor->erase(nor, addr);
752 * Default implementation, if driver doesn't have a specialized HW
755 return spi_mem_exec_op(nor->spi, &op);
759 * Erase an address range on the nor chip. The address range may extend
760 * one or more erase sectors. Return an error is there is a problem erasing.
762 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
764 struct spi_nor *nor = mtd_to_spi_nor(mtd);
768 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
769 (long long)instr->len);
774 div_u64_rem(instr->len, mtd->erasesize, &rem);
783 #ifdef CONFIG_SPI_FLASH_BAR
784 ret = write_bar(nor, addr);
790 ret = spi_nor_erase_sector(nor, addr);
794 addr += mtd->erasesize;
795 len -= mtd->erasesize;
797 ret = spi_nor_wait_till_ready(nor);
803 #ifdef CONFIG_SPI_FLASH_BAR
804 ret = clean_bar(nor);
811 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
812 /* Write status register and ensure bits in mask match written values */
813 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
818 ret = write_sr(nor, status_new);
822 ret = spi_nor_wait_till_ready(nor);
830 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
833 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
836 struct mtd_info *mtd = &nor->mtd;
837 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
838 int shift = ffs(mask) - 1;
846 pow = ((sr & mask) ^ mask) >> shift;
847 *len = mtd->size >> pow;
848 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
851 *ofs = mtd->size - *len;
856 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
857 * @locked is false); 0 otherwise
859 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
868 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
871 /* Requested range is a sub-range of locked range */
872 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
874 /* Requested range does not overlap with locked range */
875 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
878 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
881 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
884 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
887 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
891 * Lock a region of the flash. Compatible with ST Micro and similar flash.
892 * Supports the block protection bits BP{0,1,2} in the status register
893 * (SR). Does not support these features found in newer SR bitfields:
894 * - SEC: sector/block protect - only handle SEC=0 (block protect)
895 * - CMP: complement protect - only support CMP=0 (range is not complemented)
897 * Support for the following is provided conditionally for some flash:
898 * - TB: top/bottom protect
900 * Sample table portion for 8MB flash (Winbond w25q64fw):
902 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
903 * --------------------------------------------------------------------------
904 * X | X | 0 | 0 | 0 | NONE | NONE
905 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
906 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
907 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
908 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
909 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
910 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
911 * X | X | 1 | 1 | 1 | 8 MB | ALL
912 * ------|-------|-------|-------|-------|---------------|-------------------
913 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
914 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
915 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
916 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
917 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
918 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
920 * Returns negative on errors, 0 on success.
922 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
924 struct mtd_info *mtd = &nor->mtd;
925 int status_old, status_new;
926 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
927 u8 shift = ffs(mask) - 1, pow, val;
929 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
932 status_old = read_sr(nor);
936 /* If nothing in our range is unlocked, we don't need to do anything */
937 if (stm_is_locked_sr(nor, ofs, len, status_old))
940 /* If anything below us is unlocked, we can't use 'bottom' protection */
941 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
942 can_be_bottom = false;
944 /* If anything above us is unlocked, we can't use 'top' protection */
945 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
949 if (!can_be_bottom && !can_be_top)
952 /* Prefer top, if both are valid */
953 use_top = can_be_top;
955 /* lock_len: length of region that should end up locked */
957 lock_len = mtd->size - ofs;
959 lock_len = ofs + len;
962 * Need smallest pow such that:
964 * 1 / (2^pow) <= (len / size)
966 * so (assuming power-of-2 size) we do:
968 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
970 pow = ilog2(mtd->size) - ilog2(lock_len);
971 val = mask - (pow << shift);
974 /* Don't "lock" with no region! */
978 status_new = (status_old & ~mask & ~SR_TB) | val;
980 /* Disallow further writes if WP pin is asserted */
981 status_new |= SR_SRWD;
986 /* Don't bother if they're the same */
987 if (status_new == status_old)
990 /* Only modify protection if it will not unlock other areas */
991 if ((status_new & mask) < (status_old & mask))
994 return write_sr_and_check(nor, status_new, mask);
998 * Unlock a region of the flash. See stm_lock() for more info
1000 * Returns negative on errors, 0 on success.
1002 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1004 struct mtd_info *mtd = &nor->mtd;
1005 int status_old, status_new;
1006 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1007 u8 shift = ffs(mask) - 1, pow, val;
1009 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1012 status_old = read_sr(nor);
1016 /* If nothing in our range is locked, we don't need to do anything */
1017 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
1020 /* If anything below us is locked, we can't use 'top' protection */
1021 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
1024 /* If anything above us is locked, we can't use 'bottom' protection */
1025 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1027 can_be_bottom = false;
1029 if (!can_be_bottom && !can_be_top)
1032 /* Prefer top, if both are valid */
1033 use_top = can_be_top;
1035 /* lock_len: length of region that should remain locked */
1037 lock_len = mtd->size - (ofs + len);
1042 * Need largest pow such that:
1044 * 1 / (2^pow) >= (len / size)
1046 * so (assuming power-of-2 size) we do:
1048 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
1050 pow = ilog2(mtd->size) - order_base_2(lock_len);
1051 if (lock_len == 0) {
1052 val = 0; /* fully unlocked */
1054 val = mask - (pow << shift);
1055 /* Some power-of-two sizes are not supported */
1060 status_new = (status_old & ~mask & ~SR_TB) | val;
1062 /* Don't protect status register if we're fully unlocked */
1064 status_new &= ~SR_SRWD;
1067 status_new |= SR_TB;
1069 /* Don't bother if they're the same */
1070 if (status_new == status_old)
1073 /* Only modify protection if it will not lock other areas */
1074 if ((status_new & mask) > (status_old & mask))
1077 return write_sr_and_check(nor, status_new, mask);
1081 * Check if a region of the flash is (completely) locked. See stm_lock() for
1084 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1085 * negative on errors.
1087 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1091 status = read_sr(nor);
1095 return stm_is_locked_sr(nor, ofs, len, status);
1097 #endif /* CONFIG_SPI_FLASH_STMICRO */
1099 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1102 u8 id[SPI_NOR_MAX_ID_LEN];
1103 const struct flash_info *info;
1105 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1107 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1108 return ERR_PTR(tmp);
1112 for (; info->name; info++) {
1114 if (!memcmp(info->id, id, info->id_len))
1119 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1120 id[0], id[1], id[2]);
1121 return ERR_PTR(-ENODEV);
1124 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1125 size_t *retlen, u_char *buf)
1127 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1130 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1134 size_t read_len = len;
1136 #ifdef CONFIG_SPI_FLASH_BAR
1139 ret = write_bar(nor, addr);
1141 return log_ret(ret);
1142 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
1144 if (len < remain_len)
1147 read_len = remain_len;
1150 ret = nor->read(nor, addr, read_len, buf);
1152 /* We shouldn't see 0-length reads */
1167 #ifdef CONFIG_SPI_FLASH_BAR
1168 ret = clean_bar(nor);
1173 #ifdef CONFIG_SPI_FLASH_SST
1175 * sst26 flash series has its own block protection implementation:
1176 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
1177 * 1x - 32 KByte blocks - write protection bits
1178 * rest - 64 KByte blocks - write protection bits
1179 * 1x - 32 KByte blocks - write protection bits
1180 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
1182 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
1183 * will be treated as single block.
1185 #define SST26_BPR_8K_NUM 4
1186 #define SST26_MAX_BPR_REG_LEN (18 + 1)
1187 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
1195 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
1198 case SST26_CTL_LOCK:
1199 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
1201 case SST26_CTL_UNLOCK:
1202 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
1204 case SST26_CTL_CHECK:
1205 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
1212 * Lock, unlock or check lock status of the flash region of the flash (depending
1213 * on the lock_ctl value)
1215 static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
1217 struct mtd_info *mtd = &nor->mtd;
1218 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
1219 bool lower_64k = false, upper_64k = false;
1220 u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
1223 /* Check length and offset for 64k alignment */
1224 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
1225 dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
1229 if (ofs + len > mtd->size) {
1230 dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
1231 ofs, len, mtd->size);
1235 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
1236 if (mtd->size != SZ_2M &&
1237 mtd->size != SZ_4M &&
1241 bpr_size = 2 + (mtd->size / SZ_64K / 8);
1243 ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
1245 dev_err(nor->dev, "fail to read block-protection register\n");
1249 rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
1250 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
1252 upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
1253 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
1255 /* Lower bits in block-protection register are about 64k region */
1256 bpr_ptr = lptr_64k / SZ_64K - 1;
1258 /* Process 64K blocks region */
1259 while (lptr_64k < rptr_64k) {
1260 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1267 /* 32K and 8K region bits in BPR are after 64k region bits */
1268 bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
1270 /* Process lower 32K block region */
1272 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1277 /* Process upper 32K block region */
1279 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1284 /* Process lower 8K block regions */
1285 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1287 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1290 /* In 8K area BPR has both read and write protection bits */
1294 /* Process upper 8K block regions */
1295 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1297 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1300 /* In 8K area BPR has both read and write protection bits */
1304 /* If we check region status we don't need to write BPR back */
1305 if (ctl == SST26_CTL_CHECK)
1308 ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
1310 dev_err(nor->dev, "fail to write block-protection register\n");
1317 static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1319 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
1322 static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1324 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
1328 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
1329 * and negative on errors.
1331 static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1334 * is_locked function is used for check before reading or erasing flash
1335 * region, so offset and length might be not 64k allighned, so adjust
1336 * them to be 64k allighned as sst26_lock_ctl works only with 64k
1337 * allighned regions.
1339 ofs -= ofs & (SZ_64K - 1);
1340 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
1342 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
1345 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
1346 size_t *retlen, const u_char *buf)
1351 for (actual = 0; actual < len; actual++) {
1352 nor->program_opcode = SPINOR_OP_BP;
1355 /* write one byte. */
1356 ret = nor->write(nor, to, 1, buf + actual);
1359 ret = spi_nor_wait_till_ready(nor);
1370 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1371 size_t *retlen, const u_char *buf)
1373 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1374 struct spi_slave *spi = nor->spi;
1378 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1379 if (spi->mode & SPI_TX_BYTE)
1380 return sst_write_byteprogram(nor, to, len, retlen, buf);
1384 nor->sst_write_second = false;
1387 /* Start write from odd address. */
1389 nor->program_opcode = SPINOR_OP_BP;
1391 /* write one byte. */
1392 ret = nor->write(nor, to, 1, buf);
1395 ret = spi_nor_wait_till_ready(nor);
1401 /* Write out most of the data here. */
1402 for (; actual < len - 1; actual += 2) {
1403 nor->program_opcode = SPINOR_OP_AAI_WP;
1405 /* write two bytes. */
1406 ret = nor->write(nor, to, 2, buf + actual);
1409 ret = spi_nor_wait_till_ready(nor);
1413 nor->sst_write_second = true;
1415 nor->sst_write_second = false;
1418 ret = spi_nor_wait_till_ready(nor);
1422 /* Write out trailing byte if it exists. */
1423 if (actual != len) {
1426 nor->program_opcode = SPINOR_OP_BP;
1427 ret = nor->write(nor, to, 1, buf + actual);
1430 ret = spi_nor_wait_till_ready(nor);
1442 * Write an address range to the nor chip. Data must be written in
1443 * FLASH_PAGESIZE chunks. The address range may be any size provided
1444 * it is within the physical boundaries.
1446 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1447 size_t *retlen, const u_char *buf)
1449 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1450 size_t page_offset, page_remain, i;
1453 #ifdef CONFIG_SPI_FLASH_SST
1454 /* sst nor chips use AAI word program */
1455 if (nor->info->flags & SST_WRITE)
1456 return sst_write(mtd, to, len, retlen, buf);
1459 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1464 for (i = 0; i < len; ) {
1466 loff_t addr = to + i;
1470 * If page_size is a power of two, the offset can be quickly
1471 * calculated with an AND operation. On the other cases we
1472 * need to do a modulus operation (more expensive).
1474 if (is_power_of_2(nor->page_size)) {
1475 page_offset = addr & (nor->page_size - 1);
1479 page_offset = do_div(aux, nor->page_size);
1481 /* the size of data remaining on the first page */
1482 page_remain = min_t(size_t,
1483 nor->page_size - page_offset, len - i);
1485 #ifdef CONFIG_SPI_FLASH_BAR
1486 ret = write_bar(nor, addr);
1491 ret = nor->write(nor, addr, page_remain, buf + i);
1496 ret = spi_nor_wait_till_ready(nor);
1504 #ifdef CONFIG_SPI_FLASH_BAR
1505 ret = clean_bar(nor);
1510 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
1512 * macronix_quad_enable() - set QE bit in Status Register.
1513 * @nor: pointer to a 'struct spi_nor'
1515 * Set the Quad Enable (QE) bit in the Status Register.
1517 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1519 * Return: 0 on success, -errno otherwise.
1521 static int macronix_quad_enable(struct spi_nor *nor)
1528 if (val & SR_QUAD_EN_MX)
1533 write_sr(nor, val | SR_QUAD_EN_MX);
1535 ret = spi_nor_wait_till_ready(nor);
1540 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1541 dev_err(nor->dev, "Macronix Quad bit not set\n");
1549 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1551 * Write status Register and configuration register with 2 bytes
1552 * The first byte will be written to the status register, while the
1553 * second byte will be written to the configuration register.
1554 * Return negative if error occurred.
1556 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1562 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1565 "error while writing configuration register\n");
1569 ret = spi_nor_wait_till_ready(nor);
1572 "timeout while writing configuration register\n");
1580 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1581 * @nor: pointer to a 'struct spi_nor'
1583 * Set the Quad Enable (QE) bit in the Configuration Register.
1584 * This function should be used with QSPI memories supporting the Read
1585 * Configuration Register (35h) instruction.
1587 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1590 * Return: 0 on success, -errno otherwise.
1592 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1597 /* Check current Quad Enable bit value. */
1601 "error while reading configuration register\n");
1605 if (ret & CR_QUAD_EN_SPAN)
1608 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1610 /* Keep the current value of the Status Register. */
1613 dev_dbg(nor->dev, "error while reading status register\n");
1618 ret = write_sr_cr(nor, sr_cr);
1622 /* Read back and check it. */
1624 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1625 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1632 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1634 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1635 * @nor: pointer to a 'struct spi_nor'
1637 * Set the Quad Enable (QE) bit in the Configuration Register.
1638 * This function should be used with QSPI memories not supporting the Read
1639 * Configuration Register (35h) instruction.
1641 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1644 * Return: 0 on success, -errno otherwise.
1646 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1651 /* Keep the current value of the Status Register. */
1654 dev_dbg(nor->dev, "error while reading status register\n");
1658 sr_cr[1] = CR_QUAD_EN_SPAN;
1660 return write_sr_cr(nor, sr_cr);
1663 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1664 #endif /* CONFIG_SPI_FLASH_SPANSION */
1667 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1671 enum spi_nor_protocol proto)
1673 read->num_mode_clocks = num_mode_clocks;
1674 read->num_wait_states = num_wait_states;
1675 read->opcode = opcode;
1676 read->proto = proto;
1680 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1682 enum spi_nor_protocol proto)
1684 pp->opcode = opcode;
1688 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1690 * Serial Flash Discoverable Parameters (SFDP) parsing.
1694 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1695 * @nor: pointer to a 'struct spi_nor'
1696 * @addr: offset in the SFDP area to start reading data from
1697 * @len: number of bytes to read
1698 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1700 * Whatever the actual numbers of bytes for address and dummy cycles are
1701 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1702 * followed by a 3-byte address and 8 dummy clock cycles.
1704 * Return: 0 on success, -errno otherwise.
1706 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1707 size_t len, void *buf)
1709 u8 addr_width, read_opcode, read_dummy;
1712 read_opcode = nor->read_opcode;
1713 addr_width = nor->addr_width;
1714 read_dummy = nor->read_dummy;
1716 nor->read_opcode = SPINOR_OP_RDSFDP;
1717 nor->addr_width = 3;
1718 nor->read_dummy = 8;
1721 ret = nor->read(nor, addr, len, (u8 *)buf);
1722 if (!ret || ret > len) {
1736 nor->read_opcode = read_opcode;
1737 nor->addr_width = addr_width;
1738 nor->read_dummy = read_dummy;
1743 /* Fast Read settings. */
1746 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1748 enum spi_nor_protocol proto)
1750 read->num_mode_clocks = (half >> 5) & 0x07;
1751 read->num_wait_states = (half >> 0) & 0x1f;
1752 read->opcode = (half >> 8) & 0xff;
1753 read->proto = proto;
1756 struct sfdp_bfpt_read {
1757 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1761 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1762 * whether the Fast Read x-y-z command is supported.
1764 u32 supported_dword;
1768 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1769 * encodes the op code, the number of mode clocks and the number of wait
1770 * states to be used by Fast Read x-y-z command.
1775 /* The SPI protocol for this Fast Read x-y-z command. */
1776 enum spi_nor_protocol proto;
1779 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1780 /* Fast Read 1-1-2 */
1782 SNOR_HWCAPS_READ_1_1_2,
1783 BFPT_DWORD(1), BIT(16), /* Supported bit */
1784 BFPT_DWORD(4), 0, /* Settings */
1788 /* Fast Read 1-2-2 */
1790 SNOR_HWCAPS_READ_1_2_2,
1791 BFPT_DWORD(1), BIT(20), /* Supported bit */
1792 BFPT_DWORD(4), 16, /* Settings */
1796 /* Fast Read 2-2-2 */
1798 SNOR_HWCAPS_READ_2_2_2,
1799 BFPT_DWORD(5), BIT(0), /* Supported bit */
1800 BFPT_DWORD(6), 16, /* Settings */
1804 /* Fast Read 1-1-4 */
1806 SNOR_HWCAPS_READ_1_1_4,
1807 BFPT_DWORD(1), BIT(22), /* Supported bit */
1808 BFPT_DWORD(3), 16, /* Settings */
1812 /* Fast Read 1-4-4 */
1814 SNOR_HWCAPS_READ_1_4_4,
1815 BFPT_DWORD(1), BIT(21), /* Supported bit */
1816 BFPT_DWORD(3), 0, /* Settings */
1820 /* Fast Read 4-4-4 */
1822 SNOR_HWCAPS_READ_4_4_4,
1823 BFPT_DWORD(5), BIT(4), /* Supported bit */
1824 BFPT_DWORD(7), 16, /* Settings */
1829 struct sfdp_bfpt_erase {
1831 * The half-word at offset <shift> in DWORD <dwoard> encodes the
1832 * op code and erase sector size to be used by Sector Erase commands.
1838 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
1839 /* Erase Type 1 in DWORD8 bits[15:0] */
1842 /* Erase Type 2 in DWORD8 bits[31:16] */
1843 {BFPT_DWORD(8), 16},
1845 /* Erase Type 3 in DWORD9 bits[15:0] */
1848 /* Erase Type 4 in DWORD9 bits[31:16] */
1849 {BFPT_DWORD(9), 16},
1852 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
1855 spi_nor_post_bfpt_fixups(struct spi_nor *nor,
1856 const struct sfdp_parameter_header *bfpt_header,
1857 const struct sfdp_bfpt *bfpt,
1858 struct spi_nor_flash_parameter *params)
1860 if (nor->fixups && nor->fixups->post_bfpt)
1861 return nor->fixups->post_bfpt(nor, bfpt_header, bfpt, params);
1867 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
1868 * @nor: pointer to a 'struct spi_nor'
1869 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
1870 * the Basic Flash Parameter Table length and version
1871 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1874 * The Basic Flash Parameter Table is the main and only mandatory table as
1875 * defined by the SFDP (JESD216) specification.
1876 * It provides us with the total size (memory density) of the data array and
1877 * the number of address bytes for Fast Read, Page Program and Sector Erase
1879 * For Fast READ commands, it also gives the number of mode clock cycles and
1880 * wait states (regrouped in the number of dummy clock cycles) for each
1881 * supported instruction op code.
1882 * For Page Program, the page size is now available since JESD216 rev A, however
1883 * the supported instruction op codes are still not provided.
1884 * For Sector Erase commands, this table stores the supported instruction op
1885 * codes and the associated sector sizes.
1886 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
1887 * rev A. The QER bits encode the manufacturer dependent procedure to be
1888 * executed to set the Quad Enable (QE) bit in some internal register of the
1889 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
1890 * sending any Quad SPI command to the memory. Actually, setting the QE bit
1891 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
1892 * and IO3 hence enabling 4 (Quad) I/O lines.
1894 * Return: 0 on success, -errno otherwise.
1896 static int spi_nor_parse_bfpt(struct spi_nor *nor,
1897 const struct sfdp_parameter_header *bfpt_header,
1898 struct spi_nor_flash_parameter *params)
1900 struct mtd_info *mtd = &nor->mtd;
1901 struct sfdp_bfpt bfpt;
1907 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
1908 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
1911 /* Read the Basic Flash Parameter Table. */
1912 len = min_t(size_t, sizeof(bfpt),
1913 bfpt_header->length * sizeof(u32));
1914 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
1915 memset(&bfpt, 0, sizeof(bfpt));
1916 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
1920 /* Fix endianness of the BFPT DWORDs. */
1921 for (i = 0; i < BFPT_DWORD_MAX; i++)
1922 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
1924 /* Number of address bytes. */
1925 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
1926 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
1927 nor->addr_width = 3;
1930 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
1931 nor->addr_width = 4;
1938 /* Flash Memory Density (in bits). */
1939 params->size = bfpt.dwords[BFPT_DWORD(2)];
1940 if (params->size & BIT(31)) {
1941 params->size &= ~BIT(31);
1944 * Prevent overflows on params->size. Anyway, a NOR of 2^64
1945 * bits is unlikely to exist so this error probably means
1946 * the BFPT we are reading is corrupted/wrong.
1948 if (params->size > 63)
1951 params->size = 1ULL << params->size;
1955 params->size >>= 3; /* Convert to bytes. */
1957 /* Fast Read settings. */
1958 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
1959 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
1960 struct spi_nor_read_command *read;
1962 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
1963 params->hwcaps.mask &= ~rd->hwcaps;
1967 params->hwcaps.mask |= rd->hwcaps;
1968 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
1969 read = ¶ms->reads[cmd];
1970 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
1971 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
1974 /* Sector Erase settings. */
1975 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
1976 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
1980 half = bfpt.dwords[er->dword] >> er->shift;
1981 erasesize = half & 0xff;
1983 /* erasesize == 0 means this Erase Type is not supported. */
1987 erasesize = 1U << erasesize;
1988 opcode = (half >> 8) & 0xff;
1989 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1990 if (erasesize == SZ_4K) {
1991 nor->erase_opcode = opcode;
1992 mtd->erasesize = erasesize;
1996 if (!mtd->erasesize || mtd->erasesize < erasesize) {
1997 nor->erase_opcode = opcode;
1998 mtd->erasesize = erasesize;
2002 /* Stop here if not JESD216 rev A or later. */
2003 if (bfpt_header->length == BFPT_DWORD_MAX_JESD216)
2004 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2007 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2008 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2009 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2010 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2011 params->page_size = 1U << params->page_size;
2013 /* Quad Enable Requirements. */
2014 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2015 case BFPT_DWORD15_QER_NONE:
2016 params->quad_enable = NULL;
2018 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2019 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2020 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2021 params->quad_enable = spansion_no_read_cr_quad_enable;
2024 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
2025 case BFPT_DWORD15_QER_SR1_BIT6:
2026 params->quad_enable = macronix_quad_enable;
2029 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2030 case BFPT_DWORD15_QER_SR2_BIT1:
2031 params->quad_enable = spansion_read_cr_quad_enable;
2038 /* Stop here if JESD216 rev B. */
2039 if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B)
2040 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2043 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
2047 * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
2049 * @nor: pointer to a 'struct spi_nor'.
2050 * @param_header: pointer to the SFDP parameter header.
2052 * Return: 0 on success, -errno otherwise.
2055 spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
2056 const struct sfdp_parameter_header *param_header)
2062 size = param_header->length * sizeof(u32);
2063 addr = SFDP_PARAM_HEADER_PTP(param_header);
2065 nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
2066 if (!nor->manufacturer_sfdp)
2069 ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
2075 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2076 * @nor: pointer to a 'struct spi_nor'
2077 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2080 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2081 * specification. This is a standard which tends to supported by almost all
2082 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2083 * runtime the main parameters needed to perform basic SPI flash operations such
2084 * as Fast Read, Page Program or Sector Erase commands.
2086 * Return: 0 on success, -errno otherwise.
2088 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2089 struct spi_nor_flash_parameter *params)
2091 const struct sfdp_parameter_header *param_header, *bfpt_header;
2092 struct sfdp_parameter_header *param_headers = NULL;
2093 struct sfdp_header header;
2097 /* Get the SFDP header. */
2098 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2102 /* Check the SFDP header version. */
2103 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2104 header.major != SFDP_JESD216_MAJOR)
2108 * Verify that the first and only mandatory parameter header is a
2109 * Basic Flash Parameter Table header as specified in JESD216.
2111 bfpt_header = &header.bfpt_header;
2112 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2113 bfpt_header->major != SFDP_JESD216_MAJOR)
2117 * Allocate memory then read all parameter headers with a single
2118 * Read SFDP command. These parameter headers will actually be parsed
2119 * twice: a first time to get the latest revision of the basic flash
2120 * parameter table, then a second time to handle the supported optional
2122 * Hence we read the parameter headers once for all to reduce the
2123 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2124 * because we don't need to keep these parameter headers: the allocated
2125 * memory is always released with kfree() before exiting this function.
2128 psize = header.nph * sizeof(*param_headers);
2130 param_headers = kmalloc(psize, GFP_KERNEL);
2134 err = spi_nor_read_sfdp(nor, sizeof(header),
2135 psize, param_headers);
2138 "failed to read SFDP parameter headers\n");
2144 * Check other parameter headers to get the latest revision of
2145 * the basic flash parameter table.
2147 for (i = 0; i < header.nph; i++) {
2148 param_header = ¶m_headers[i];
2150 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2151 param_header->major == SFDP_JESD216_MAJOR &&
2152 (param_header->minor > bfpt_header->minor ||
2153 (param_header->minor == bfpt_header->minor &&
2154 param_header->length > bfpt_header->length)))
2155 bfpt_header = param_header;
2158 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2162 /* Parse other parameter headers. */
2163 for (i = 0; i < header.nph; i++) {
2164 param_header = ¶m_headers[i];
2166 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2167 case SFDP_SECTOR_MAP_ID:
2169 "non-uniform erase sector maps are not supported yet.\n");
2173 err = spi_nor_parse_microchip_sfdp(nor, param_header);
2182 "Failed to parse optional parameter table: %04x\n",
2183 SFDP_PARAM_HEADER_ID(param_header));
2185 * Let's not drop all information we extracted so far
2186 * if optional table parsers fail. In case of failing,
2187 * each optional parser is responsible to roll back to
2188 * the previously known spi_nor data.
2195 kfree(param_headers);
2199 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2200 struct spi_nor_flash_parameter *params)
2204 #endif /* SPI_FLASH_SFDP_SUPPORT */
2207 * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
2208 * after SFDP has been parsed (is also called for SPI NORs that do not
2210 * @nor: pointer to a 'struct spi_nor'
2212 * Typically used to tweak various parameters that could not be extracted by
2213 * other means (i.e. when information provided by the SFDP/flash_info tables
2214 * are incomplete or wrong).
2216 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor,
2217 struct spi_nor_flash_parameter *params)
2219 if (nor->fixups && nor->fixups->post_sfdp)
2220 nor->fixups->post_sfdp(nor, params);
2223 static void spi_nor_default_init_fixups(struct spi_nor *nor)
2225 if (nor->fixups && nor->fixups->default_init)
2226 nor->fixups->default_init(nor);
2229 static int spi_nor_init_params(struct spi_nor *nor,
2230 const struct flash_info *info,
2231 struct spi_nor_flash_parameter *params)
2233 /* Set legacy flash parameters as default. */
2234 memset(params, 0, sizeof(*params));
2236 /* Set SPI NOR sizes. */
2237 params->size = info->sector_size * info->n_sectors;
2238 params->page_size = info->page_size;
2240 /* (Fast) Read settings. */
2241 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2242 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2243 0, 0, SPINOR_OP_READ,
2246 if (!(info->flags & SPI_NOR_NO_FR)) {
2247 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2248 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2249 0, 8, SPINOR_OP_READ_FAST,
2253 if (info->flags & SPI_NOR_DUAL_READ) {
2254 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2255 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2256 0, 8, SPINOR_OP_READ_1_1_2,
2260 if (info->flags & SPI_NOR_QUAD_READ) {
2261 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2262 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2263 0, 8, SPINOR_OP_READ_1_1_4,
2267 if (info->flags & SPI_NOR_OCTAL_READ) {
2268 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2269 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
2270 0, 8, SPINOR_OP_READ_1_1_8,
2274 if (info->flags & SPI_NOR_OCTAL_DTR_READ) {
2275 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2276 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
2277 0, 20, SPINOR_OP_READ_FAST,
2278 SNOR_PROTO_8_8_8_DTR);
2281 /* Page Program settings. */
2282 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2283 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2284 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2287 * Since xSPI Page Program opcode is backward compatible with
2288 * Legacy SPI, use Legacy SPI opcode there as well.
2290 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2291 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2293 if (info->flags & SPI_NOR_QUAD_READ) {
2294 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2295 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2296 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2299 /* Select the procedure to set the Quad Enable bit. */
2300 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2301 SNOR_HWCAPS_PP_QUAD)) {
2302 switch (JEDEC_MFR(info)) {
2303 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
2304 case SNOR_MFR_MACRONIX:
2306 params->quad_enable = macronix_quad_enable;
2310 case SNOR_MFR_MICRON:
2314 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2315 /* Kept only for backward compatibility purpose. */
2316 params->quad_enable = spansion_read_cr_quad_enable;
2322 spi_nor_default_init_fixups(nor);
2324 /* Override the parameters with data read from SFDP tables. */
2325 nor->addr_width = 0;
2326 nor->mtd.erasesize = 0;
2327 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2328 SPI_NOR_OCTAL_DTR_READ)) &&
2329 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2330 struct spi_nor_flash_parameter sfdp_params;
2332 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2333 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2334 nor->addr_width = 0;
2335 nor->mtd.erasesize = 0;
2337 memcpy(params, &sfdp_params, sizeof(*params));
2341 spi_nor_post_sfdp_fixups(nor, params);
2346 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2350 for (i = 0; i < size; i++)
2351 if (table[i][0] == (int)hwcaps)
2357 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2359 static const int hwcaps_read2cmd[][2] = {
2360 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2361 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2362 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2363 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2364 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2365 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2366 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2367 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2368 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2369 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2370 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2371 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2372 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2373 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2374 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2375 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },
2378 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2379 ARRAY_SIZE(hwcaps_read2cmd));
2382 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2384 static const int hwcaps_pp2cmd[][2] = {
2385 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2386 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2387 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2388 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2389 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2390 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2391 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2392 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },
2395 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2396 ARRAY_SIZE(hwcaps_pp2cmd));
2399 #ifdef CONFIG_SPI_FLASH_SMART_HWCAPS
2401 * spi_nor_check_op - check if the operation is supported by controller
2402 * @nor: pointer to a 'struct spi_nor'
2403 * @op: pointer to op template to be checked
2405 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2407 static int spi_nor_check_op(struct spi_nor *nor,
2408 struct spi_mem_op *op)
2411 * First test with 4 address bytes. The opcode itself might be a 3B
2412 * addressing opcode but we don't care, because SPI controller
2413 * implementation should not check the opcode, but just the sequence.
2415 op->addr.nbytes = 4;
2416 if (!spi_mem_supports_op(nor->spi, op)) {
2417 if (nor->mtd.size > SZ_16M)
2420 /* If flash size <= 16MB, 3 address bytes are sufficient */
2421 op->addr.nbytes = 3;
2422 if (!spi_mem_supports_op(nor->spi, op))
2430 * spi_nor_check_readop - check if the read op is supported by controller
2431 * @nor: pointer to a 'struct spi_nor'
2432 * @read: pointer to op template to be checked
2434 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2436 static int spi_nor_check_readop(struct spi_nor *nor,
2437 const struct spi_nor_read_command *read)
2439 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0),
2440 SPI_MEM_OP_ADDR(3, 0, 0),
2441 SPI_MEM_OP_DUMMY(1, 0),
2442 SPI_MEM_OP_DATA_IN(2, NULL, 0));
2444 spi_nor_setup_op(nor, &op, read->proto);
2446 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2447 op.dummy.buswidth / 8;
2448 if (spi_nor_protocol_is_dtr(nor->read_proto))
2449 op.dummy.nbytes *= 2;
2451 return spi_nor_check_op(nor, &op);
2455 * spi_nor_check_pp - check if the page program op is supported by controller
2456 * @nor: pointer to a 'struct spi_nor'
2457 * @pp: pointer to op template to be checked
2459 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2461 static int spi_nor_check_pp(struct spi_nor *nor,
2462 const struct spi_nor_pp_command *pp)
2464 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0),
2465 SPI_MEM_OP_ADDR(3, 0, 0),
2466 SPI_MEM_OP_NO_DUMMY,
2467 SPI_MEM_OP_DATA_OUT(2, NULL, 0));
2469 spi_nor_setup_op(nor, &op, pp->proto);
2471 return spi_nor_check_op(nor, &op);
2475 * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
2476 * controller capabilities
2477 * @nor: pointer to a 'struct spi_nor'
2478 * @params: pointer to the 'struct spi_nor_flash_parameter'
2479 * representing SPI NOR flash capabilities
2480 * @hwcaps: pointer to resulting capabilities after adjusting
2481 * according to controller and flash's capability
2483 * Discard caps based on what the SPI controller actually supports (using
2484 * spi_mem_supports_op()).
2487 spi_nor_adjust_hwcaps(struct spi_nor *nor,
2488 const struct spi_nor_flash_parameter *params,
2494 * Enable all caps by default. We will mask them after checking what's
2495 * really supported using spi_mem_supports_op().
2497 *hwcaps = SNOR_HWCAPS_ALL;
2499 /* X-X-X modes are not supported yet, mask them all. */
2500 *hwcaps &= ~SNOR_HWCAPS_X_X_X;
2503 * If the reset line is broken, we do not want to enter a stateful
2506 if (nor->flags & SNOR_F_BROKEN_RESET)
2507 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
2509 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2512 if (!(*hwcaps & BIT(cap)))
2515 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2517 spi_nor_check_readop(nor, ¶ms->reads[rdidx]))
2518 *hwcaps &= ~BIT(cap);
2520 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2524 if (spi_nor_check_pp(nor, ¶ms->page_programs[ppidx]))
2525 *hwcaps &= ~BIT(cap);
2530 * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
2531 * controller capabilities
2532 * @nor: pointer to a 'struct spi_nor'
2533 * @params: pointer to the 'struct spi_nor_flash_parameter'
2534 * representing SPI NOR flash capabilities
2535 * @hwcaps: pointer to resulting capabilities after adjusting
2536 * according to controller and flash's capability
2538 * Select caps based on what the SPI controller and SPI flash both support.
2541 spi_nor_adjust_hwcaps(struct spi_nor *nor,
2542 const struct spi_nor_flash_parameter *params,
2545 struct spi_slave *spi = nor->spi;
2546 u32 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2547 SNOR_HWCAPS_READ_4_4_4 |
2548 SNOR_HWCAPS_READ_8_8_8 |
2549 SNOR_HWCAPS_PP_4_4_4 |
2550 SNOR_HWCAPS_PP_8_8_8);
2551 u32 spi_hwcaps = (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |
2554 /* Get the hardware capabilities the SPI controller supports. */
2555 if (spi->mode & SPI_RX_OCTAL) {
2556 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_8;
2558 if (spi->mode & SPI_TX_OCTAL)
2559 spi_hwcaps |= (SNOR_HWCAPS_READ_1_8_8 |
2560 SNOR_HWCAPS_PP_1_1_8 |
2561 SNOR_HWCAPS_PP_1_8_8);
2562 } else if (spi->mode & SPI_RX_QUAD) {
2563 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_4;
2565 if (spi->mode & SPI_TX_QUAD)
2566 spi_hwcaps |= (SNOR_HWCAPS_READ_1_4_4 |
2567 SNOR_HWCAPS_PP_1_1_4 |
2568 SNOR_HWCAPS_PP_1_4_4);
2569 } else if (spi->mode & SPI_RX_DUAL) {
2570 spi_hwcaps |= SNOR_HWCAPS_READ_1_1_2;
2572 if (spi->mode & SPI_TX_DUAL)
2573 spi_hwcaps |= SNOR_HWCAPS_READ_1_2_2;
2577 * Keep only the hardware capabilities supported by both the SPI
2578 * controller and the SPI flash memory.
2580 *hwcaps = spi_hwcaps & params->hwcaps.mask;
2581 if (*hwcaps & ignored_mask) {
2583 "SPI n-n-n protocols are not supported yet.\n");
2584 *hwcaps &= ~ignored_mask;
2587 #endif /* CONFIG_SPI_FLASH_SMART_HWCAPS */
2589 static int spi_nor_select_read(struct spi_nor *nor,
2590 const struct spi_nor_flash_parameter *params,
2593 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2594 const struct spi_nor_read_command *read;
2599 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2603 read = ¶ms->reads[cmd];
2604 nor->read_opcode = read->opcode;
2605 nor->read_proto = read->proto;
2608 * In the spi-nor framework, we don't need to make the difference
2609 * between mode clock cycles and wait state clock cycles.
2610 * Indeed, the value of the mode clock cycles is used by a QSPI
2611 * flash memory to know whether it should enter or leave its 0-4-4
2612 * (Continuous Read / XIP) mode.
2613 * eXecution In Place is out of the scope of the mtd sub-system.
2614 * Hence we choose to merge both mode and wait state clock cycles
2615 * into the so called dummy clock cycles.
2617 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2621 static int spi_nor_select_pp(struct spi_nor *nor,
2622 const struct spi_nor_flash_parameter *params,
2625 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2626 const struct spi_nor_pp_command *pp;
2631 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2635 pp = ¶ms->page_programs[cmd];
2636 nor->program_opcode = pp->opcode;
2637 nor->write_proto = pp->proto;
2641 static int spi_nor_select_erase(struct spi_nor *nor,
2642 const struct flash_info *info)
2644 struct mtd_info *mtd = &nor->mtd;
2646 /* Do nothing if already configured from SFDP. */
2650 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2651 /* prefer "small sector" erase if possible */
2652 if (info->flags & SECT_4K) {
2653 nor->erase_opcode = SPINOR_OP_BE_4K;
2654 mtd->erasesize = 4096;
2655 } else if (info->flags & SECT_4K_PMC) {
2656 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2657 mtd->erasesize = 4096;
2661 nor->erase_opcode = SPINOR_OP_SE;
2662 mtd->erasesize = info->sector_size;
2667 static int spi_nor_default_setup(struct spi_nor *nor,
2668 const struct flash_info *info,
2669 const struct spi_nor_flash_parameter *params)
2672 bool enable_quad_io;
2675 spi_nor_adjust_hwcaps(nor, params, &shared_mask);
2677 /* Select the (Fast) Read command. */
2678 err = spi_nor_select_read(nor, params, shared_mask);
2681 "can't select read settings supported by both the SPI controller and memory.\n");
2685 /* Select the Page Program command. */
2686 err = spi_nor_select_pp(nor, params, shared_mask);
2689 "can't select write settings supported by both the SPI controller and memory.\n");
2693 /* Select the Sector Erase command. */
2694 err = spi_nor_select_erase(nor, info);
2697 "can't select erase settings supported by both the SPI controller and memory.\n");
2701 /* Enable Quad I/O if needed. */
2702 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2703 spi_nor_get_protocol_width(nor->write_proto) == 4);
2704 if (enable_quad_io && params->quad_enable)
2705 nor->quad_enable = params->quad_enable;
2707 nor->quad_enable = NULL;
2712 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2713 const struct spi_nor_flash_parameter *params)
2718 return nor->setup(nor, info, params);
2721 static int spi_nor_init(struct spi_nor *nor)
2726 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2727 * with the software protection bits set
2729 if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) &&
2730 (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2731 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2732 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2733 nor->info->flags & SPI_NOR_HAS_LOCK)) {
2736 spi_nor_wait_till_ready(nor);
2739 if (nor->quad_enable) {
2740 err = nor->quad_enable(nor);
2742 dev_dbg(nor->dev, "quad mode not supported\n");
2747 if (nor->addr_width == 4 &&
2748 !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) &&
2749 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2750 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
2752 * If the RESET# pin isn't hooked up properly, or the system
2753 * otherwise doesn't perform a reset command in the boot
2754 * sequence, it's impossible to 100% protect against unexpected
2755 * reboots (e.g., crashes). Warn the user (or hopefully, system
2756 * designer) that this is bad.
2758 if (nor->flags & SNOR_F_BROKEN_RESET)
2759 debug("enabling reset hack; may not recover from unexpected reboots\n");
2760 set_4byte(nor, nor->info, 1);
2766 void spi_nor_set_fixups(struct spi_nor *nor)
2770 int spi_nor_scan(struct spi_nor *nor)
2772 struct spi_nor_flash_parameter params;
2773 const struct flash_info *info = NULL;
2774 struct mtd_info *mtd = &nor->mtd;
2775 struct spi_slave *spi = nor->spi;
2778 /* Reset SPI protocol for all commands. */
2779 nor->reg_proto = SNOR_PROTO_1_1_1;
2780 nor->read_proto = SNOR_PROTO_1_1_1;
2781 nor->write_proto = SNOR_PROTO_1_1_1;
2782 nor->read = spi_nor_read_data;
2783 nor->write = spi_nor_write_data;
2784 nor->read_reg = spi_nor_read_reg;
2785 nor->write_reg = spi_nor_write_reg;
2787 nor->setup = spi_nor_default_setup;
2789 info = spi_nor_read_id(nor);
2790 if (IS_ERR_OR_NULL(info))
2794 spi_nor_set_fixups(nor);
2796 /* Parse the Serial Flash Discoverable Parameters table. */
2797 ret = spi_nor_init_params(nor, info, ¶ms);
2802 mtd->name = info->name;
2803 mtd->dev = nor->dev;
2805 mtd->type = MTD_NORFLASH;
2807 mtd->flags = MTD_CAP_NORFLASH;
2808 mtd->size = params.size;
2809 mtd->_erase = spi_nor_erase;
2810 mtd->_read = spi_nor_read;
2811 mtd->_write = spi_nor_write;
2813 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
2814 /* NOR protection support for STmicro/Micron chips and similar */
2815 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
2816 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2817 JEDEC_MFR(info) == SNOR_MFR_SST ||
2818 info->flags & SPI_NOR_HAS_LOCK) {
2819 nor->flash_lock = stm_lock;
2820 nor->flash_unlock = stm_unlock;
2821 nor->flash_is_locked = stm_is_locked;
2825 #ifdef CONFIG_SPI_FLASH_SST
2827 * sst26 series block protection implementation differs from other
2830 if (info->flags & SPI_NOR_HAS_SST26LOCK) {
2831 nor->flash_lock = sst26_lock;
2832 nor->flash_unlock = sst26_unlock;
2833 nor->flash_is_locked = sst26_is_locked;
2837 if (info->flags & USE_FSR)
2838 nor->flags |= SNOR_F_USE_FSR;
2839 if (info->flags & SPI_NOR_HAS_TB)
2840 nor->flags |= SNOR_F_HAS_SR_TB;
2841 if (info->flags & NO_CHIP_ERASE)
2842 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2843 if (info->flags & USE_CLSR)
2844 nor->flags |= SNOR_F_USE_CLSR;
2846 if (info->flags & SPI_NOR_NO_ERASE)
2847 mtd->flags |= MTD_NO_ERASE;
2849 nor->page_size = params.page_size;
2850 mtd->writebufsize = nor->page_size;
2852 /* Some devices cannot do fast-read, no matter what DT tells us */
2853 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
2854 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2857 * Configure the SPI memory:
2858 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2859 * - set the number of dummy cycles (mode cycles + wait states).
2860 * - set the SPI protocols for register and memory accesses.
2861 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2863 ret = spi_nor_setup(nor, info, ¶ms);
2867 if (spi_nor_protocol_is_dtr(nor->read_proto)) {
2868 /* Always use 4-byte addresses in DTR mode. */
2869 nor->addr_width = 4;
2870 } else if (nor->addr_width) {
2871 /* already configured from SFDP */
2872 } else if (info->addr_width) {
2873 nor->addr_width = info->addr_width;
2875 nor->addr_width = 3;
2878 if (nor->addr_width == 3 && mtd->size > SZ_16M) {
2879 #ifndef CONFIG_SPI_FLASH_BAR
2880 /* enable 4-byte addressing if the device exceeds 16MiB */
2881 nor->addr_width = 4;
2882 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2883 info->flags & SPI_NOR_4B_OPCODES)
2884 spi_nor_set_4byte_opcodes(nor, info);
2886 /* Configure the BAR - discover bank cmds and read current bank */
2887 nor->addr_width = 3;
2888 ret = read_bar(nor, info);
2894 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2895 dev_dbg(nor->dev, "address width is too large: %u\n",
2900 /* Send all the required SPI flash commands to initialize device */
2901 ret = spi_nor_init(nor);
2905 nor->name = mtd->name;
2906 nor->size = mtd->size;
2907 nor->erase_size = mtd->erasesize;
2908 nor->sector_size = mtd->erasesize;
2910 #ifndef CONFIG_SPL_BUILD
2911 printf("SF: Detected %s with page size ", nor->name);
2912 print_size(nor->page_size, ", erase size ");
2913 print_size(nor->erase_size, ", total ");
2914 print_size(nor->size, "");
2921 /* U-Boot specific functions, need to extend MTD to support these */
2922 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
2924 int sr = read_sr(nor);
2929 return (sr >> 2) & 7;