drivers/mtd/spi/sf_ops.c

   1 /*
   2  * SPI flash operations
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
   6  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <spi_flash.h>
  15 #include <watchdog.h>
  16
  17 #include "sf_internal.h"
  18
  19 static void spi_flash_addr(u32 addr, u8 *cmd)
  20 {
  21         /* cmd[0] is actual command */
  22         cmd[1] = addr >> 16;
  23         cmd[2] = addr >> 8;
  24         cmd[3] = addr >> 0;
  25 }
  26
  27 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
  28 {
  29         u8 cmd;
  30         int ret;
  31
  32         cmd = CMD_WRITE_STATUS;
  33         ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
  34         if (ret < 0) {
  35                 debug("SF: fail to write status register\n");
  36                 return ret;
  37         }
  38
  39         return 0;
  40 }
  41
  42 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  43 static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
  44 {
  45         u8 data[2];
  46         u8 cmd;
  47         int ret;
  48
  49         cmd = CMD_READ_STATUS;
  50         ret = spi_flash_read_common(flash, &cmd, 1, &data[0], 1);
  51         if (ret < 0) {
  52                 debug("SF: fail to read status register\n");
  53                 return ret;
  54         }
  55
  56         cmd = CMD_WRITE_STATUS;
  57         data[1] = cr;
  58         ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
  59         if (ret) {
  60                 debug("SF: fail to write config register\n");
  61                 return ret;
  62         }
  63
  64         return 0;
  65 }
  66
  67 int spi_flash_set_qeb_winspan(struct spi_flash *flash)
  68 {
  69         u8 qeb_status;
  70         u8 cmd;
  71         int ret;
  72
  73         cmd = CMD_READ_CONFIG;
  74         ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
  75         if (ret < 0) {
  76                 debug("SF: fail to read config register\n");
  77                 return ret;
  78         }
  79
  80         if (qeb_status & STATUS_QEB_WINSPAN) {
  81                 debug("SF: Quad enable bit is already set\n");
  82         } else {
  83                 ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
  84                 if (ret < 0)
  85                         return ret;
  86         }
  87
  88         return ret;
  89 }
  90 #endif
  91
  92 #ifdef CONFIG_SPI_FLASH_BAR
  93 static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
  94 {
  95         u8 cmd;
  96         int ret;
  97
  98         if (flash->bank_curr == bank_sel) {
  99                 debug("SF: not require to enable bank%d\n", bank_sel);
 100                 return 0;
 101         }
 102
 103         cmd = flash->bank_write_cmd;
 104         ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
 105         if (ret < 0) {
 106                 debug("SF: fail to write bank register\n");
 107                 return ret;
 108         }
 109         flash->bank_curr = bank_sel;
 110
 111         return 0;
 112 }
 113
 114 static int spi_flash_bank(struct spi_flash *flash, u32 offset)
 115 {
 116         u8 bank_sel;
 117         int ret;
 118
 119         bank_sel = offset / SPI_FLASH_16MB_BOUN;
 120
 121         ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 122         if (ret) {
 123                 debug("SF: fail to set bank%d\n", bank_sel);
 124                 return ret;
 125         }
 126
 127         return 0;
 128 }
 129 #endif
 130
 131 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
 132 {
 133         struct spi_slave *spi = flash->spi;
 134         unsigned long timebase;
 135         int ret;
 136         u8 status;
 137         u8 check_status = 0x0;
 138         u8 poll_bit = STATUS_WIP;
 139         u8 cmd = flash->poll_cmd;
 140
 141         if (cmd == CMD_FLAG_STATUS) {
 142                 poll_bit = STATUS_PEC;
 143                 check_status = poll_bit;
 144         }
 145
 146         ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
 147         if (ret) {
 148                 debug("SF: fail to read %s status register\n",
 149                       cmd == CMD_READ_STATUS ? "read" : "flag");
 150                 return ret;
 151         }
 152
 153         timebase = get_timer(0);
 154         do {
 155                 WATCHDOG_RESET();
 156
 157                 ret = spi_xfer(spi, 8, NULL, &status, 0);
 158                 if (ret)
 159                         return -1;
 160
 161                 if ((status & poll_bit) == check_status)
 162                         break;
 163
 164         } while (get_timer(timebase) < timeout);
 165
 166         spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
 167
 168         if ((status & poll_bit) == check_status)
 169                 return 0;
 170
 171         /* Timed out */
 172         debug("SF: time out!\n");
 173         return -1;
 174 }
 175
 176 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 177                 size_t cmd_len, const void *buf, size_t buf_len)
 178 {
 179         struct spi_slave *spi = flash->spi;
 180         unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
 181         int ret;
 182
 183         if (buf == NULL)
 184                 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
 185
 186         ret = spi_claim_bus(flash->spi);
 187         if (ret) {
 188                 debug("SF: unable to claim SPI bus\n");
 189                 return ret;
 190         }
 191
 192         ret = spi_flash_cmd_write_enable(flash);
 193         if (ret < 0) {
 194                 debug("SF: enabling write failed\n");
 195                 return ret;
 196         }
 197
 198         ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
 199         if (ret < 0) {
 200                 debug("SF: write cmd failed\n");
 201                 return ret;
 202         }
 203
 204         ret = spi_flash_cmd_wait_ready(flash, timeout);
 205         if (ret < 0) {
 206                 debug("SF: write %s timed out\n",
 207                       timeout == SPI_FLASH_PROG_TIMEOUT ?
 208                         "program" : "page erase");
 209                 return ret;
 210         }
 211
 212         spi_release_bus(spi);
 213
 214         return ret;
 215 }
 216
 217 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 218 {
 219         u32 erase_size;
 220         u8 cmd[SPI_FLASH_CMD_LEN];
 221         int ret = -1;
 222
 223         erase_size = flash->erase_size;
 224         if (offset % erase_size || len % erase_size) {
 225                 debug("SF: Erase offset/length not multiple of erase size\n");
 226                 return -1;
 227         }
 228
 229         cmd[0] = flash->erase_cmd;
 230         while (len) {
 231 #ifdef CONFIG_SPI_FLASH_BAR
 232                 ret = spi_flash_bank(flash, offset);
 233                 if (ret < 0)
 234                         return ret;
 235 #endif
 236                 spi_flash_addr(offset, cmd);
 237
 238                 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
 239                       cmd[2], cmd[3], offset);
 240
 241                 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
 242                 if (ret < 0) {
 243                         debug("SF: erase failed\n");
 244                         break;
 245                 }
 246
 247                 offset += erase_size;
 248                 len -= erase_size;
 249         }
 250
 251         return ret;
 252 }
 253
 254 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 255                 size_t len, const void *buf)
 256 {
 257         unsigned long byte_addr, page_size;
 258         size_t chunk_len, actual;
 259         u8 cmd[SPI_FLASH_CMD_LEN];
 260         int ret = -1;
 261
 262         page_size = flash->page_size;
 263
 264         cmd[0] = flash->write_cmd;
 265         for (actual = 0; actual < len; actual += chunk_len) {
 266 #ifdef CONFIG_SPI_FLASH_BAR
 267                 ret = spi_flash_bank(flash, offset);
 268                 if (ret < 0)
 269                         return ret;
 270 #endif
 271                 byte_addr = offset % page_size;
 272                 chunk_len = min(len - actual, page_size - byte_addr);
 273
 274                 if (flash->spi->max_write_size)
 275                         chunk_len = min(chunk_len, flash->spi->max_write_size);
 276
 277                 spi_flash_addr(offset, cmd);
 278
 279                 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
 280                       buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 281
 282                 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
 283                                         buf + actual, chunk_len);
 284                 if (ret < 0) {
 285                         debug("SF: write failed\n");
 286                         break;
 287                 }
 288
 289                 offset += chunk_len;
 290         }
 291
 292         return ret;
 293 }
 294
 295 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 296                 size_t cmd_len, void *data, size_t data_len)
 297 {
 298         struct spi_slave *spi = flash->spi;
 299         int ret;
 300
 301         ret = spi_claim_bus(flash->spi);
 302         if (ret) {
 303                 debug("SF: unable to claim SPI bus\n");
 304                 return ret;
 305         }
 306
 307         ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
 308         if (ret < 0) {
 309                 debug("SF: read cmd failed\n");
 310                 return ret;
 311         }
 312
 313         spi_release_bus(spi);
 314
 315         return ret;
 316 }
 317
 318 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 319                 size_t len, void *data)
 320 {
 321         u8 *cmd, cmdsz, bank_sel = 0;
 322         u32 remain_len, read_len;
 323         int ret = -1;
 324
 325         /* Handle memory-mapped SPI */
 326         if (flash->memory_map) {
 327                 ret = spi_claim_bus(flash->spi);
 328                 if (ret) {
 329                         debug("SF: unable to claim SPI bus\n");
 330                         return ret;
 331                 }
 332                 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
 333                 memcpy(data, flash->memory_map + offset, len);
 334                 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
 335                 spi_release_bus(flash->spi);
 336                 return 0;
 337         }
 338
 339         cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
 340         cmd = malloc(cmdsz);
 341         memset(cmd, 0, cmdsz);
 342
 343         cmd[0] = flash->read_cmd;
 344         while (len) {
 345 #ifdef CONFIG_SPI_FLASH_BAR
 346                 bank_sel = offset / SPI_FLASH_16MB_BOUN;
 347
 348                 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 349                 if (ret) {
 350                         debug("SF: fail to set bank%d\n", bank_sel);
 351                         return ret;
 352                 }
 353 #endif
 354                 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
 355                 if (len < remain_len)
 356                         read_len = len;
 357                 else
 358                         read_len = remain_len;
 359
 360                 spi_flash_addr(offset, cmd);
 361
 362                 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
 363                 if (ret < 0) {
 364                         debug("SF: read failed\n");
 365                         break;
 366                 }
 367
 368                 offset += read_len;
 369                 len -= read_len;
 370                 data += read_len;
 371         }
 372
 373         return ret;
 374 }
 375
 376 #ifdef CONFIG_SPI_FLASH_SST
 377 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
 378 {
 379         int ret;
 380         u8 cmd[4] = {
 381                 CMD_SST_BP,
 382                 offset >> 16,
 383                 offset >> 8,
 384                 offset,
 385         };
 386
 387         debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
 388               spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
 389
 390         ret = spi_flash_cmd_write_enable(flash);
 391         if (ret)
 392                 return ret;
 393
 394         ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
 395         if (ret)
 396                 return ret;
 397
 398         return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 399 }
 400
 401 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
 402                 const void *buf)
 403 {
 404         size_t actual, cmd_len;
 405         int ret;
 406         u8 cmd[4];
 407
 408         ret = spi_claim_bus(flash->spi);
 409         if (ret) {
 410                 debug("SF: Unable to claim SPI bus\n");
 411                 return ret;
 412         }
 413
 414         /* If the data is not word aligned, write out leading single byte */
 415         actual = offset % 2;
 416         if (actual) {
 417                 ret = sst_byte_write(flash, offset, buf);
 418                 if (ret)
 419                         goto done;
 420         }
 421         offset += actual;
 422
 423         ret = spi_flash_cmd_write_enable(flash);
 424         if (ret)
 425                 goto done;
 426
 427         cmd_len = 4;
 428         cmd[0] = CMD_SST_AAI_WP;
 429         cmd[1] = offset >> 16;
 430         cmd[2] = offset >> 8;
 431         cmd[3] = offset;
 432
 433         for (; actual < len - 1; actual += 2) {
 434                 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
 435                       spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
 436                       cmd[0], offset);
 437
 438                 ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
 439                                         buf + actual, 2);
 440                 if (ret) {
 441                         debug("SF: sst word program failed\n");
 442                         break;
 443                 }
 444
 445                 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 446                 if (ret)
 447                         break;
 448
 449                 cmd_len = 1;
 450                 offset += 2;
 451         }
 452
 453         if (!ret)
 454                 ret = spi_flash_cmd_write_disable(flash);
 455
 456         /* If there is a single trailing byte, write it out */
 457         if (!ret && actual != len)
 458                 ret = sst_byte_write(flash, offset, buf + actual);
 459
 460  done:
 461         debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
 462               ret ? "failure" : "success", len, offset - actual);
 463
 464         spi_release_bus(flash->spi);
 465         return ret;
 466 }
 467 #endif