4 * Copyright (C) 2008 Atmel Corporation
5 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <spi_flash.h>
17 #include "sf_internal.h"
19 static void spi_flash_addr(u32 addr, u8 *cmd)
21 /* cmd[0] is actual command */
27 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
32 cmd = CMD_READ_STATUS;
33 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
35 debug("SF: fail to read status register\n");
42 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
47 cmd = CMD_WRITE_STATUS;
48 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
50 debug("SF: fail to write status register\n");
57 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
58 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
63 cmd = CMD_READ_CONFIG;
64 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
66 debug("SF: fail to read config register\n");
73 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
79 ret = spi_flash_cmd_read_status(flash, &data[0]);
83 cmd = CMD_WRITE_STATUS;
85 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
87 debug("SF: fail to write config register\n");
95 #ifdef CONFIG_SPI_FLASH_BAR
96 static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
101 if (flash->bank_curr == bank_sel) {
102 debug("SF: not require to enable bank%d\n", bank_sel);
106 cmd = flash->bank_write_cmd;
107 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
109 debug("SF: fail to write bank register\n");
112 flash->bank_curr = bank_sel;
117 static int spi_flash_bank(struct spi_flash *flash, u32 offset)
122 bank_sel = offset / SPI_FLASH_16MB_BOUN;
124 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
126 debug("SF: fail to set bank%d\n", bank_sel);
134 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
136 struct spi_slave *spi = flash->spi;
137 unsigned long timebase;
140 u8 check_status = 0x0;
141 u8 poll_bit = STATUS_WIP;
142 u8 cmd = flash->poll_cmd;
144 if (cmd == CMD_FLAG_STATUS) {
145 poll_bit = STATUS_PEC;
146 check_status = poll_bit;
149 ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
151 debug("SF: fail to read %s status register\n",
152 cmd == CMD_READ_STATUS ? "read" : "flag");
156 timebase = get_timer(0);
160 ret = spi_xfer(spi, 8, NULL, &status, 0);
164 if ((status & poll_bit) == check_status)
167 } while (get_timer(timebase) < timeout);
169 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
171 if ((status & poll_bit) == check_status)
175 debug("SF: time out!\n");
179 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
180 size_t cmd_len, const void *buf, size_t buf_len)
182 struct spi_slave *spi = flash->spi;
183 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
187 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
189 ret = spi_claim_bus(flash->spi);
191 debug("SF: unable to claim SPI bus\n");
195 ret = spi_flash_cmd_write_enable(flash);
197 debug("SF: enabling write failed\n");
201 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
203 debug("SF: write cmd failed\n");
207 ret = spi_flash_cmd_wait_ready(flash, timeout);
209 debug("SF: write %s timed out\n",
210 timeout == SPI_FLASH_PROG_TIMEOUT ?
211 "program" : "page erase");
215 spi_release_bus(spi);
220 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
223 u8 cmd[SPI_FLASH_CMD_LEN];
226 erase_size = flash->erase_size;
227 if (offset % erase_size || len % erase_size) {
228 debug("SF: Erase offset/length not multiple of erase size\n");
232 cmd[0] = flash->erase_cmd;
234 #ifdef CONFIG_SPI_FLASH_BAR
235 ret = spi_flash_bank(flash, offset);
239 spi_flash_addr(offset, cmd);
241 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
242 cmd[2], cmd[3], offset);
244 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
246 debug("SF: erase failed\n");
250 offset += erase_size;
257 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
258 size_t len, const void *buf)
260 unsigned long byte_addr, page_size;
261 size_t chunk_len, actual;
262 u8 cmd[SPI_FLASH_CMD_LEN];
265 page_size = flash->page_size;
267 cmd[0] = flash->write_cmd;
268 for (actual = 0; actual < len; actual += chunk_len) {
269 #ifdef CONFIG_SPI_FLASH_BAR
270 ret = spi_flash_bank(flash, offset);
274 byte_addr = offset % page_size;
275 chunk_len = min(len - actual, page_size - byte_addr);
277 if (flash->spi->max_write_size)
278 chunk_len = min(chunk_len, flash->spi->max_write_size);
280 spi_flash_addr(offset, cmd);
282 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
283 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
285 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
286 buf + actual, chunk_len);
288 debug("SF: write failed\n");
298 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
299 size_t cmd_len, void *data, size_t data_len)
301 struct spi_slave *spi = flash->spi;
304 ret = spi_claim_bus(flash->spi);
306 debug("SF: unable to claim SPI bus\n");
310 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
312 debug("SF: read cmd failed\n");
316 spi_release_bus(spi);
321 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
322 size_t len, void *data)
324 u8 *cmd, cmdsz, bank_sel = 0;
325 u32 remain_len, read_len;
328 /* Handle memory-mapped SPI */
329 if (flash->memory_map) {
330 ret = spi_claim_bus(flash->spi);
332 debug("SF: unable to claim SPI bus\n");
335 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
336 memcpy(data, flash->memory_map + offset, len);
337 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
338 spi_release_bus(flash->spi);
342 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
344 memset(cmd, 0, cmdsz);
346 cmd[0] = flash->read_cmd;
348 #ifdef CONFIG_SPI_FLASH_BAR
349 bank_sel = offset / SPI_FLASH_16MB_BOUN;
351 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
353 debug("SF: fail to set bank%d\n", bank_sel);
357 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
358 if (len < remain_len)
361 read_len = remain_len;
363 spi_flash_addr(offset, cmd);
365 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
367 debug("SF: read failed\n");
379 #ifdef CONFIG_SPI_FLASH_SST
380 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
390 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
391 spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
393 ret = spi_flash_cmd_write_enable(flash);
397 ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
401 return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
404 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
407 size_t actual, cmd_len;
411 ret = spi_claim_bus(flash->spi);
413 debug("SF: Unable to claim SPI bus\n");
417 /* If the data is not word aligned, write out leading single byte */
420 ret = sst_byte_write(flash, offset, buf);
426 ret = spi_flash_cmd_write_enable(flash);
431 cmd[0] = CMD_SST_AAI_WP;
432 cmd[1] = offset >> 16;
433 cmd[2] = offset >> 8;
436 for (; actual < len - 1; actual += 2) {
437 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
438 spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
441 ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
444 debug("SF: sst word program failed\n");
448 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
457 ret = spi_flash_cmd_write_disable(flash);
459 /* If there is a single trailing byte, write it out */
460 if (!ret && actual != len)
461 ret = sst_byte_write(flash, offset, buf + actual);
464 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
465 ret ? "failure" : "success", len, offset - actual);
467 spi_release_bus(flash->spi);