2 * Samsung S3C64XX/S5PC1XX OneNAND driver
4 * Copyright © 2008-2010 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 * Marek Szyprowski <m.szyprowski@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * S3C64XX and S5PC100: emulate the pseudo BufferRAM
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/onenand.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/dma-mapping.h>
26 #include <asm/mach/flash.h>
27 #include <plat/regs-onenand.h>
38 #define ONENAND_ERASE_STATUS 0x00
39 #define ONENAND_MULTI_ERASE_SET 0x01
40 #define ONENAND_ERASE_START 0x03
41 #define ONENAND_UNLOCK_START 0x08
42 #define ONENAND_UNLOCK_END 0x09
43 #define ONENAND_LOCK_START 0x0A
44 #define ONENAND_LOCK_END 0x0B
45 #define ONENAND_LOCK_TIGHT_START 0x0C
46 #define ONENAND_LOCK_TIGHT_END 0x0D
47 #define ONENAND_UNLOCK_ALL 0x0E
48 #define ONENAND_OTP_ACCESS 0x12
49 #define ONENAND_SPARE_ACCESS_ONLY 0x13
50 #define ONENAND_MAIN_ACCESS_ONLY 0x14
51 #define ONENAND_ERASE_VERIFY 0x15
52 #define ONENAND_MAIN_SPARE_ACCESS 0x16
53 #define ONENAND_PIPELINE_READ 0x4000
60 #define S3C64XX_CMD_MAP_SHIFT 24
61 #define S5PC1XX_CMD_MAP_SHIFT 26
63 #define S3C6400_FBA_SHIFT 10
64 #define S3C6400_FPA_SHIFT 4
65 #define S3C6400_FSA_SHIFT 2
67 #define S3C6410_FBA_SHIFT 12
68 #define S3C6410_FPA_SHIFT 6
69 #define S3C6410_FSA_SHIFT 4
71 #define S5PC100_FBA_SHIFT 13
72 #define S5PC100_FPA_SHIFT 7
73 #define S5PC100_FSA_SHIFT 5
75 /* S5PC110 specific definitions */
76 #define S5PC110_DMA_SRC_ADDR 0x400
77 #define S5PC110_DMA_SRC_CFG 0x404
78 #define S5PC110_DMA_DST_ADDR 0x408
79 #define S5PC110_DMA_DST_CFG 0x40C
80 #define S5PC110_DMA_TRANS_SIZE 0x414
81 #define S5PC110_DMA_TRANS_CMD 0x418
82 #define S5PC110_DMA_TRANS_STATUS 0x41C
83 #define S5PC110_DMA_TRANS_DIR 0x420
85 #define S5PC110_DMA_CFG_SINGLE (0x0 << 16)
86 #define S5PC110_DMA_CFG_4BURST (0x2 << 16)
87 #define S5PC110_DMA_CFG_8BURST (0x3 << 16)
88 #define S5PC110_DMA_CFG_16BURST (0x4 << 16)
90 #define S5PC110_DMA_CFG_INC (0x0 << 8)
91 #define S5PC110_DMA_CFG_CNT (0x1 << 8)
93 #define S5PC110_DMA_CFG_8BIT (0x0 << 0)
94 #define S5PC110_DMA_CFG_16BIT (0x1 << 0)
95 #define S5PC110_DMA_CFG_32BIT (0x2 << 0)
97 #define S5PC110_DMA_SRC_CFG_READ (S5PC110_DMA_CFG_16BURST | \
98 S5PC110_DMA_CFG_INC | \
99 S5PC110_DMA_CFG_16BIT)
100 #define S5PC110_DMA_DST_CFG_READ (S5PC110_DMA_CFG_16BURST | \
101 S5PC110_DMA_CFG_INC | \
102 S5PC110_DMA_CFG_32BIT)
103 #define S5PC110_DMA_SRC_CFG_WRITE (S5PC110_DMA_CFG_16BURST | \
104 S5PC110_DMA_CFG_INC | \
105 S5PC110_DMA_CFG_32BIT)
106 #define S5PC110_DMA_DST_CFG_WRITE (S5PC110_DMA_CFG_16BURST | \
107 S5PC110_DMA_CFG_INC | \
108 S5PC110_DMA_CFG_16BIT)
110 #define S5PC110_DMA_TRANS_CMD_TDC (0x1 << 18)
111 #define S5PC110_DMA_TRANS_CMD_TEC (0x1 << 16)
112 #define S5PC110_DMA_TRANS_CMD_TR (0x1 << 0)
114 #define S5PC110_DMA_TRANS_STATUS_TD (0x1 << 18)
115 #define S5PC110_DMA_TRANS_STATUS_TB (0x1 << 17)
116 #define S5PC110_DMA_TRANS_STATUS_TE (0x1 << 16)
118 #define S5PC110_DMA_DIR_READ 0x0
119 #define S5PC110_DMA_DIR_WRITE 0x1
122 struct mtd_info *mtd;
123 struct platform_device *pdev;
126 struct resource *base_res;
127 void __iomem *ahb_addr;
128 struct resource *ahb_res;
130 void __iomem *page_buf;
131 void __iomem *oob_buf;
132 unsigned int (*mem_addr)(int fba, int fpa, int fsa);
133 unsigned int (*cmd_map)(unsigned int type, unsigned int val);
134 void __iomem *dma_addr;
135 struct resource *dma_res;
136 unsigned long phys_base;
137 #ifdef CONFIG_MTD_PARTITIONS
138 struct mtd_partition *parts;
142 #define CMD_MAP_00(dev, addr) (dev->cmd_map(MAP_00, ((addr) << 1)))
143 #define CMD_MAP_01(dev, mem_addr) (dev->cmd_map(MAP_01, (mem_addr)))
144 #define CMD_MAP_10(dev, mem_addr) (dev->cmd_map(MAP_10, (mem_addr)))
145 #define CMD_MAP_11(dev, addr) (dev->cmd_map(MAP_11, ((addr) << 2)))
147 static struct s3c_onenand *onenand;
149 #ifdef CONFIG_MTD_PARTITIONS
150 static const char *part_probes[] = { "cmdlinepart", NULL, };
153 static inline int s3c_read_reg(int offset)
155 return readl(onenand->base + offset);
158 static inline void s3c_write_reg(int value, int offset)
160 writel(value, onenand->base + offset);
163 static inline int s3c_read_cmd(unsigned int cmd)
165 return readl(onenand->ahb_addr + cmd);
168 static inline void s3c_write_cmd(int value, unsigned int cmd)
170 writel(value, onenand->ahb_addr + cmd);
174 static void s3c_dump_reg(void)
178 for (i = 0; i < 0x400; i += 0x40) {
179 printk(KERN_INFO "0x%08X: 0x%08x 0x%08x 0x%08x 0x%08x\n",
180 (unsigned int) onenand->base + i,
181 s3c_read_reg(i), s3c_read_reg(i + 0x10),
182 s3c_read_reg(i + 0x20), s3c_read_reg(i + 0x30));
187 static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val)
189 return (type << S3C64XX_CMD_MAP_SHIFT) | val;
192 static unsigned int s5pc1xx_cmd_map(unsigned type, unsigned val)
194 return (type << S5PC1XX_CMD_MAP_SHIFT) | val;
197 static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa)
199 return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) |
200 (fsa << S3C6400_FSA_SHIFT);
203 static unsigned int s3c6410_mem_addr(int fba, int fpa, int fsa)
205 return (fba << S3C6410_FBA_SHIFT) | (fpa << S3C6410_FPA_SHIFT) |
206 (fsa << S3C6410_FSA_SHIFT);
209 static unsigned int s5pc100_mem_addr(int fba, int fpa, int fsa)
211 return (fba << S5PC100_FBA_SHIFT) | (fpa << S5PC100_FPA_SHIFT) |
212 (fsa << S5PC100_FSA_SHIFT);
215 static void s3c_onenand_reset(void)
217 unsigned long timeout = 0x10000;
220 s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
221 while (1 && timeout--) {
222 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
226 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
227 s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
229 /* Clear interrupt */
230 s3c_write_reg(0x0, INT_ERR_ACK_OFFSET);
231 /* Clear the ECC status */
232 s3c_write_reg(0x0, ECC_ERR_STAT_OFFSET);
235 static unsigned short s3c_onenand_readw(void __iomem *addr)
237 struct onenand_chip *this = onenand->mtd->priv;
238 struct device *dev = &onenand->pdev->dev;
239 int reg = addr - this->base;
240 int word_addr = reg >> 1;
243 /* It's used for probing time */
245 case ONENAND_REG_MANUFACTURER_ID:
246 return s3c_read_reg(MANUFACT_ID_OFFSET);
247 case ONENAND_REG_DEVICE_ID:
248 return s3c_read_reg(DEVICE_ID_OFFSET);
249 case ONENAND_REG_VERSION_ID:
250 return s3c_read_reg(FLASH_VER_ID_OFFSET);
251 case ONENAND_REG_DATA_BUFFER_SIZE:
252 return s3c_read_reg(DATA_BUF_SIZE_OFFSET);
253 case ONENAND_REG_TECHNOLOGY:
254 return s3c_read_reg(TECH_OFFSET);
255 case ONENAND_REG_SYS_CFG1:
256 return s3c_read_reg(MEM_CFG_OFFSET);
258 /* Used at unlock all status */
259 case ONENAND_REG_CTRL_STATUS:
262 case ONENAND_REG_WP_STATUS:
263 return ONENAND_WP_US;
269 /* BootRAM access control */
270 if ((unsigned int) addr < ONENAND_DATARAM && onenand->bootram_command) {
272 return s3c_read_reg(MANUFACT_ID_OFFSET);
274 return s3c_read_reg(DEVICE_ID_OFFSET);
276 return s3c_read_reg(FLASH_VER_ID_OFFSET);
279 value = s3c_read_cmd(CMD_MAP_11(onenand, word_addr)) & 0xffff;
280 dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__,
285 static void s3c_onenand_writew(unsigned short value, void __iomem *addr)
287 struct onenand_chip *this = onenand->mtd->priv;
288 struct device *dev = &onenand->pdev->dev;
289 unsigned int reg = addr - this->base;
290 unsigned int word_addr = reg >> 1;
292 /* It's used for probing time */
294 case ONENAND_REG_SYS_CFG1:
295 s3c_write_reg(value, MEM_CFG_OFFSET);
298 case ONENAND_REG_START_ADDRESS1:
299 case ONENAND_REG_START_ADDRESS2:
302 /* Lock/lock-tight/unlock/unlock_all */
303 case ONENAND_REG_START_BLOCK_ADDRESS:
310 /* BootRAM access control */
311 if ((unsigned int)addr < ONENAND_DATARAM) {
312 if (value == ONENAND_CMD_READID) {
313 onenand->bootram_command = 1;
316 if (value == ONENAND_CMD_RESET) {
317 s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
318 onenand->bootram_command = 0;
323 dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__,
326 s3c_write_cmd(value, CMD_MAP_11(onenand, word_addr));
329 static int s3c_onenand_wait(struct mtd_info *mtd, int state)
331 struct device *dev = &onenand->pdev->dev;
332 unsigned int flags = INT_ACT;
333 unsigned int stat, ecc;
334 unsigned long timeout;
338 flags |= BLK_RW_CMP | LOAD_CMP;
341 flags |= BLK_RW_CMP | PGM_CMP;
344 flags |= BLK_RW_CMP | ERS_CMP;
353 /* The 20 msec is enough */
354 timeout = jiffies + msecs_to_jiffies(20);
355 while (time_before(jiffies, timeout)) {
356 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
360 if (state != FL_READING)
363 /* To get correct interrupt status in timeout case */
364 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
365 s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
368 * In the Spec. it checks the controller status first
369 * However if you get the correct information in case of
370 * power off recovery (POR) test, it should read ECC status first
372 if (stat & LOAD_CMP) {
373 ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET);
374 if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
375 dev_info(dev, "%s: ECC error = 0x%04x\n", __func__,
377 mtd->ecc_stats.failed++;
382 if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) {
383 dev_info(dev, "%s: controller error = 0x%04x\n", __func__,
385 if (stat & LOCKED_BLK)
386 dev_info(dev, "%s: it's locked error = 0x%04x\n",
395 static int s3c_onenand_command(struct mtd_info *mtd, int cmd, loff_t addr,
398 struct onenand_chip *this = mtd->priv;
400 int fba, fpa, fsa = 0;
401 unsigned int mem_addr, cmd_map_01, cmd_map_10;
402 int i, mcount, scount;
405 fba = (int) (addr >> this->erase_shift);
406 fpa = (int) (addr >> this->page_shift);
407 fpa &= this->page_mask;
409 mem_addr = onenand->mem_addr(fba, fpa, fsa);
410 cmd_map_01 = CMD_MAP_01(onenand, mem_addr);
411 cmd_map_10 = CMD_MAP_10(onenand, mem_addr);
414 case ONENAND_CMD_READ:
415 case ONENAND_CMD_READOOB:
416 case ONENAND_CMD_BUFFERRAM:
417 ONENAND_SET_NEXT_BUFFERRAM(this);
422 index = ONENAND_CURRENT_BUFFERRAM(this);
425 * Emulate Two BufferRAMs and access with 4 bytes pointer
427 m = (unsigned int *) onenand->page_buf;
428 s = (unsigned int *) onenand->oob_buf;
431 m += (this->writesize >> 2);
432 s += (mtd->oobsize >> 2);
435 mcount = mtd->writesize >> 2;
436 scount = mtd->oobsize >> 2;
439 case ONENAND_CMD_READ:
441 for (i = 0; i < mcount; i++)
442 *m++ = s3c_read_cmd(cmd_map_01);
445 case ONENAND_CMD_READOOB:
446 s3c_write_reg(TSRF, TRANS_SPARE_OFFSET);
448 for (i = 0; i < mcount; i++)
449 *m++ = s3c_read_cmd(cmd_map_01);
452 for (i = 0; i < scount; i++)
453 *s++ = s3c_read_cmd(cmd_map_01);
455 s3c_write_reg(0, TRANS_SPARE_OFFSET);
458 case ONENAND_CMD_PROG:
460 for (i = 0; i < mcount; i++)
461 s3c_write_cmd(*m++, cmd_map_01);
464 case ONENAND_CMD_PROGOOB:
465 s3c_write_reg(TSRF, TRANS_SPARE_OFFSET);
467 /* Main - dummy write */
468 for (i = 0; i < mcount; i++)
469 s3c_write_cmd(0xffffffff, cmd_map_01);
472 for (i = 0; i < scount; i++)
473 s3c_write_cmd(*s++, cmd_map_01);
475 s3c_write_reg(0, TRANS_SPARE_OFFSET);
478 case ONENAND_CMD_UNLOCK_ALL:
479 s3c_write_cmd(ONENAND_UNLOCK_ALL, cmd_map_10);
482 case ONENAND_CMD_ERASE:
483 s3c_write_cmd(ONENAND_ERASE_START, cmd_map_10);
493 static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area)
495 struct onenand_chip *this = mtd->priv;
496 int index = ONENAND_CURRENT_BUFFERRAM(this);
499 if (area == ONENAND_DATARAM) {
500 p = (unsigned char *) onenand->page_buf;
502 p += this->writesize;
504 p = (unsigned char *) onenand->oob_buf;
512 static int onenand_read_bufferram(struct mtd_info *mtd, int area,
513 unsigned char *buffer, int offset,
518 p = s3c_get_bufferram(mtd, area);
519 memcpy(buffer, p + offset, count);
523 static int onenand_write_bufferram(struct mtd_info *mtd, int area,
524 const unsigned char *buffer, int offset,
529 p = s3c_get_bufferram(mtd, area);
530 memcpy(p + offset, buffer, count);
534 static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
536 void __iomem *base = onenand->dma_addr;
539 writel(src, base + S5PC110_DMA_SRC_ADDR);
540 writel(dst, base + S5PC110_DMA_DST_ADDR);
542 if (direction == S5PC110_DMA_DIR_READ) {
543 writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
544 writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
546 writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
547 writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
550 writel(count, base + S5PC110_DMA_TRANS_SIZE);
551 writel(direction, base + S5PC110_DMA_TRANS_DIR);
553 writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
556 status = readl(base + S5PC110_DMA_TRANS_STATUS);
557 } while (!(status & S5PC110_DMA_TRANS_STATUS_TD));
559 if (status & S5PC110_DMA_TRANS_STATUS_TE) {
560 writel(S5PC110_DMA_TRANS_CMD_TEC, base + S5PC110_DMA_TRANS_CMD);
561 writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
565 writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
570 static int s5pc110_read_bufferram(struct mtd_info *mtd, int area,
571 unsigned char *buffer, int offset, size_t count)
573 struct onenand_chip *this = mtd->priv;
575 void *buf = (void *) buffer;
576 dma_addr_t dma_src, dma_dst;
579 p = this->base + area;
580 if (ONENAND_CURRENT_BUFFERRAM(this)) {
581 if (area == ONENAND_DATARAM)
582 p += this->writesize;
587 if (offset & 3 || (size_t) buf & 3 ||
588 !onenand->dma_addr || count != mtd->writesize)
591 /* Handle vmalloc address */
592 if (buf >= high_memory) {
595 if (((size_t) buf & PAGE_MASK) !=
596 ((size_t) (buf + count - 1) & PAGE_MASK))
598 page = vmalloc_to_page(buf);
601 buf = page_address(page) + ((size_t) buf & ~PAGE_MASK);
605 dma_src = onenand->phys_base + (p - this->base);
606 dma_dst = dma_map_single(&onenand->pdev->dev,
607 buf, count, DMA_FROM_DEVICE);
608 if (dma_mapping_error(&onenand->pdev->dev, dma_dst)) {
609 dev_err(&onenand->pdev->dev,
610 "Couldn't map a %d byte buffer for DMA\n", count);
613 err = s5pc110_dma_ops((void *) dma_dst, (void *) dma_src,
614 count, S5PC110_DMA_DIR_READ);
615 dma_unmap_single(&onenand->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
621 if (count != mtd->writesize) {
622 /* Copy the bufferram to memory to prevent unaligned access */
623 memcpy(this->page_buf, p, mtd->writesize);
624 p = this->page_buf + offset;
627 memcpy(buffer, p, count);
632 static int s5pc110_chip_probe(struct mtd_info *mtd)
634 /* Now just return 0 */
638 static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state)
640 unsigned int flags = INT_ACT | LOAD_CMP;
642 unsigned long timeout;
644 /* The 20 msec is enough */
645 timeout = jiffies + msecs_to_jiffies(20);
646 while (time_before(jiffies, timeout)) {
647 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
651 /* To get correct interrupt status in timeout case */
652 stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
653 s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
655 if (stat & LD_FAIL_ECC_ERR) {
657 return ONENAND_BBT_READ_ERROR;
660 if (stat & LOAD_CMP) {
661 int ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET);
662 if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
664 return ONENAND_BBT_READ_ERROR;
671 static void s3c_onenand_check_lock_status(struct mtd_info *mtd)
673 struct onenand_chip *this = mtd->priv;
674 struct device *dev = &onenand->pdev->dev;
675 unsigned int block, end;
678 end = this->chipsize >> this->erase_shift;
680 for (block = 0; block < end; block++) {
681 unsigned int mem_addr = onenand->mem_addr(block, 0, 0);
682 tmp = s3c_read_cmd(CMD_MAP_01(onenand, mem_addr));
684 if (s3c_read_reg(INT_ERR_STAT_OFFSET) & LOCKED_BLK) {
685 dev_err(dev, "block %d is write-protected!\n", block);
686 s3c_write_reg(LOCKED_BLK, INT_ERR_ACK_OFFSET);
691 static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs,
694 struct onenand_chip *this = mtd->priv;
695 int start, end, start_mem_addr, end_mem_addr;
697 start = ofs >> this->erase_shift;
698 start_mem_addr = onenand->mem_addr(start, 0, 0);
699 end = start + (len >> this->erase_shift) - 1;
700 end_mem_addr = onenand->mem_addr(end, 0, 0);
702 if (cmd == ONENAND_CMD_LOCK) {
703 s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(onenand,
705 s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(onenand,
708 s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(onenand,
710 s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(onenand,
714 this->wait(mtd, FL_LOCKING);
717 static void s3c_unlock_all(struct mtd_info *mtd)
719 struct onenand_chip *this = mtd->priv;
721 size_t len = this->chipsize;
723 if (this->options & ONENAND_HAS_UNLOCK_ALL) {
724 /* Write unlock command */
725 this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
727 /* No need to check return value */
728 this->wait(mtd, FL_LOCKING);
730 /* Workaround for all block unlock in DDP */
731 if (!ONENAND_IS_DDP(this)) {
732 s3c_onenand_check_lock_status(mtd);
736 /* All blocks on another chip */
737 ofs = this->chipsize >> 1;
738 len = this->chipsize >> 1;
741 s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
743 s3c_onenand_check_lock_status(mtd);
746 static void s3c_onenand_setup(struct mtd_info *mtd)
748 struct onenand_chip *this = mtd->priv;
752 if (onenand->type == TYPE_S3C6400) {
753 onenand->mem_addr = s3c6400_mem_addr;
754 onenand->cmd_map = s3c64xx_cmd_map;
755 } else if (onenand->type == TYPE_S3C6410) {
756 onenand->mem_addr = s3c6410_mem_addr;
757 onenand->cmd_map = s3c64xx_cmd_map;
758 } else if (onenand->type == TYPE_S5PC100) {
759 onenand->mem_addr = s5pc100_mem_addr;
760 onenand->cmd_map = s5pc1xx_cmd_map;
761 } else if (onenand->type == TYPE_S5PC110) {
762 /* Use generic onenand functions */
763 onenand->cmd_map = s5pc1xx_cmd_map;
764 this->read_bufferram = s5pc110_read_bufferram;
765 this->chip_probe = s5pc110_chip_probe;
771 this->read_word = s3c_onenand_readw;
772 this->write_word = s3c_onenand_writew;
774 this->wait = s3c_onenand_wait;
775 this->bbt_wait = s3c_onenand_bbt_wait;
776 this->unlock_all = s3c_unlock_all;
777 this->command = s3c_onenand_command;
779 this->read_bufferram = onenand_read_bufferram;
780 this->write_bufferram = onenand_write_bufferram;
783 static int s3c_onenand_probe(struct platform_device *pdev)
785 struct onenand_platform_data *pdata;
786 struct onenand_chip *this;
787 struct mtd_info *mtd;
791 pdata = pdev->dev.platform_data;
792 /* No need to check pdata. the platform data is optional */
794 size = sizeof(struct mtd_info) + sizeof(struct onenand_chip);
795 mtd = kzalloc(size, GFP_KERNEL);
797 dev_err(&pdev->dev, "failed to allocate memory\n");
801 onenand = kzalloc(sizeof(struct s3c_onenand), GFP_KERNEL);
807 this = (struct onenand_chip *) &mtd[1];
809 mtd->dev.parent = &pdev->dev;
810 mtd->owner = THIS_MODULE;
811 onenand->pdev = pdev;
812 onenand->type = platform_get_device_id(pdev)->driver_data;
814 s3c_onenand_setup(mtd);
816 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 dev_err(&pdev->dev, "no memory resource defined\n");
820 goto ahb_resource_failed;
823 onenand->base_res = request_mem_region(r->start, resource_size(r),
825 if (!onenand->base_res) {
826 dev_err(&pdev->dev, "failed to request memory resource\n");
828 goto resource_failed;
831 onenand->base = ioremap(r->start, resource_size(r));
832 if (!onenand->base) {
833 dev_err(&pdev->dev, "failed to map memory resource\n");
837 /* Set onenand_chip also */
838 this->base = onenand->base;
840 /* Use runtime badblock check */
841 this->options |= ONENAND_SKIP_UNLOCK_CHECK;
843 if (onenand->type != TYPE_S5PC110) {
844 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
846 dev_err(&pdev->dev, "no buffer memory resource defined\n");
848 goto ahb_resource_failed;
851 onenand->ahb_res = request_mem_region(r->start, resource_size(r),
853 if (!onenand->ahb_res) {
854 dev_err(&pdev->dev, "failed to request buffer memory resource\n");
856 goto ahb_resource_failed;
859 onenand->ahb_addr = ioremap(r->start, resource_size(r));
860 if (!onenand->ahb_addr) {
861 dev_err(&pdev->dev, "failed to map buffer memory resource\n");
863 goto ahb_ioremap_failed;
866 /* Allocate 4KiB BufferRAM */
867 onenand->page_buf = kzalloc(SZ_4K, GFP_KERNEL);
868 if (!onenand->page_buf) {
873 /* Allocate 128 SpareRAM */
874 onenand->oob_buf = kzalloc(128, GFP_KERNEL);
875 if (!onenand->oob_buf) {
880 /* S3C doesn't handle subpage write */
881 mtd->subpage_sft = 0;
882 this->subpagesize = mtd->writesize;
884 } else { /* S5PC110 */
885 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
887 dev_err(&pdev->dev, "no dma memory resource defined\n");
889 goto dma_resource_failed;
892 onenand->dma_res = request_mem_region(r->start, resource_size(r),
894 if (!onenand->dma_res) {
895 dev_err(&pdev->dev, "failed to request dma memory resource\n");
897 goto dma_resource_failed;
900 onenand->dma_addr = ioremap(r->start, resource_size(r));
901 if (!onenand->dma_addr) {
902 dev_err(&pdev->dev, "failed to map dma memory resource\n");
904 goto dma_ioremap_failed;
907 onenand->phys_base = onenand->base_res->start;
910 if (onenand_scan(mtd, 1)) {
915 if (onenand->type != TYPE_S5PC110) {
916 /* S3C doesn't handle subpage write */
917 mtd->subpage_sft = 0;
918 this->subpagesize = mtd->writesize;
921 if (s3c_read_reg(MEM_CFG_OFFSET) & ONENAND_SYS_CFG1_SYNC_READ)
922 dev_info(&onenand->pdev->dev, "OneNAND Sync. Burst Read enabled\n");
924 #ifdef CONFIG_MTD_PARTITIONS
925 err = parse_mtd_partitions(mtd, part_probes, &onenand->parts, 0);
927 add_mtd_partitions(mtd, onenand->parts, err);
928 else if (err <= 0 && pdata && pdata->parts)
929 add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
932 err = add_mtd_device(mtd);
934 platform_set_drvdata(pdev, mtd);
939 if (onenand->dma_addr)
940 iounmap(onenand->dma_addr);
942 if (onenand->dma_res)
943 release_mem_region(onenand->dma_res->start,
944 resource_size(onenand->dma_res));
945 kfree(onenand->oob_buf);
947 kfree(onenand->page_buf);
949 if (onenand->ahb_addr)
950 iounmap(onenand->ahb_addr);
952 if (onenand->ahb_res)
953 release_mem_region(onenand->ahb_res->start,
954 resource_size(onenand->ahb_res));
957 iounmap(onenand->base);
959 if (onenand->base_res)
960 release_mem_region(onenand->base_res->start,
961 resource_size(onenand->base_res));
969 static int __devexit s3c_onenand_remove(struct platform_device *pdev)
971 struct mtd_info *mtd = platform_get_drvdata(pdev);
973 onenand_release(mtd);
974 if (onenand->ahb_addr)
975 iounmap(onenand->ahb_addr);
976 if (onenand->ahb_res)
977 release_mem_region(onenand->ahb_res->start,
978 resource_size(onenand->ahb_res));
979 if (onenand->dma_addr)
980 iounmap(onenand->dma_addr);
981 if (onenand->dma_res)
982 release_mem_region(onenand->dma_res->start,
983 resource_size(onenand->dma_res));
985 iounmap(onenand->base);
986 release_mem_region(onenand->base_res->start,
987 resource_size(onenand->base_res));
989 platform_set_drvdata(pdev, NULL);
990 kfree(onenand->oob_buf);
991 kfree(onenand->page_buf);
997 static int s3c_pm_ops_suspend(struct device *dev)
999 struct platform_device *pdev = to_platform_device(dev);
1000 struct mtd_info *mtd = platform_get_drvdata(pdev);
1001 struct onenand_chip *this = mtd->priv;
1003 this->wait(mtd, FL_PM_SUSPENDED);
1004 return mtd->suspend(mtd);
1007 static int s3c_pm_ops_resume(struct device *dev)
1009 struct platform_device *pdev = to_platform_device(dev);
1010 struct mtd_info *mtd = platform_get_drvdata(pdev);
1011 struct onenand_chip *this = mtd->priv;
1014 this->unlock_all(mtd);
1018 static const struct dev_pm_ops s3c_pm_ops = {
1019 .suspend = s3c_pm_ops_suspend,
1020 .resume = s3c_pm_ops_resume,
1023 static struct platform_device_id s3c_onenand_driver_ids[] = {
1025 .name = "s3c6400-onenand",
1026 .driver_data = TYPE_S3C6400,
1028 .name = "s3c6410-onenand",
1029 .driver_data = TYPE_S3C6410,
1031 .name = "s5pc100-onenand",
1032 .driver_data = TYPE_S5PC100,
1034 .name = "s5pc110-onenand",
1035 .driver_data = TYPE_S5PC110,
1038 MODULE_DEVICE_TABLE(platform, s3c_onenand_driver_ids);
1040 static struct platform_driver s3c_onenand_driver = {
1042 .name = "samsung-onenand",
1045 .id_table = s3c_onenand_driver_ids,
1046 .probe = s3c_onenand_probe,
1047 .remove = __devexit_p(s3c_onenand_remove),
1050 static int __init s3c_onenand_init(void)
1052 return platform_driver_register(&s3c_onenand_driver);
1055 static void __exit s3c_onenand_exit(void)
1057 platform_driver_unregister(&s3c_onenand_driver);
1060 module_init(s3c_onenand_init);
1061 module_exit(s3c_onenand_exit);
1063 MODULE_LICENSE("GPL");
1064 MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
1065 MODULE_DESCRIPTION("Samsung OneNAND controller support");