drivers/mtd/nand/tegra_nand.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
   4  * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
   5  * (C) Copyright 2006 DENX Software Engineering
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <nand.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/funcmux.h>
  15 #include <asm/arch-tegra/clk_rst.h>
  16 #include <asm/errno.h>
  17 #include <asm/gpio.h>
  18 #include <fdtdec.h>
  19 #include "tegra_nand.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define NAND_CMD_TIMEOUT_MS             10
  24
  25 #define SKIPPED_SPARE_BYTES             4
  26
  27 /* ECC bytes to be generated for tag data */
  28 #define TAG_ECC_BYTES                   4
  29
  30 /* 64 byte oob block info for large page (== 2KB) device
  31  *
  32  * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
  33  *      Skipped bytes(4)
  34  *      Main area Ecc(36)
  35  *      Tag data(20)
  36  *      Tag data Ecc(4)
  37  *
  38  * Yaffs2 will use 16 tag bytes.
  39  */
  40 static struct nand_ecclayout eccoob = {
  41         .eccbytes = 36,
  42         .eccpos = {
  43                 4,  5,  6,  7,  8,  9,  10, 11, 12,
  44                 13, 14, 15, 16, 17, 18, 19, 20, 21,
  45                 22, 23, 24, 25, 26, 27, 28, 29, 30,
  46                 31, 32, 33, 34, 35, 36, 37, 38, 39,
  47         },
  48         .oobavail = 20,
  49         .oobfree = {
  50                         {
  51                         .offset = 40,
  52                         .length = 20,
  53                         },
  54         }
  55 };
  56
  57 enum {
  58         ECC_OK,
  59         ECC_TAG_ERROR = 1 << 0,
  60         ECC_DATA_ERROR = 1 << 1
  61 };
  62
  63 /* Timing parameters */
  64 enum {
  65         FDT_NAND_MAX_TRP_TREA,
  66         FDT_NAND_TWB,
  67         FDT_NAND_MAX_TCR_TAR_TRR,
  68         FDT_NAND_TWHR,
  69         FDT_NAND_MAX_TCS_TCH_TALS_TALH,
  70         FDT_NAND_TWH,
  71         FDT_NAND_TWP,
  72         FDT_NAND_TRH,
  73         FDT_NAND_TADL,
  74
  75         FDT_NAND_TIMING_COUNT
  76 };
  77
  78 /* Information about an attached NAND chip */
  79 struct fdt_nand {
  80         struct nand_ctlr *reg;
  81         int enabled;            /* 1 to enable, 0 to disable */
  82         struct gpio_desc wp_gpio;       /* write-protect GPIO */
  83         s32 width;              /* bit width, normally 8 */
  84         u32 timing[FDT_NAND_TIMING_COUNT];
  85 };
  86
  87 struct nand_drv {
  88         struct nand_ctlr *reg;
  89         struct fdt_nand config;
  90 };
  91
  92 static struct nand_drv nand_ctrl;
  93 static struct mtd_info *our_mtd;
  94 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  95
  96 #ifdef CONFIG_SYS_DCACHE_OFF
  97 static inline void dma_prepare(void *start, unsigned long length,
  98                                int is_writing)
  99 {
 100 }
 101 #else
 102 /**
 103  * Prepare for a DMA transaction
 104  *
 105  * For a write we flush out our data. For a read we invalidate, since we
 106  * need to do this before we read from the buffer after the DMA has
 107  * completed, so may as well do it now.
 108  *
 109  * @param start         Start address for DMA buffer (should be cache-aligned)
 110  * @param length        Length of DMA buffer in bytes
 111  * @param is_writing    0 if reading, non-zero if writing
 112  */
 113 static void dma_prepare(void *start, unsigned long length, int is_writing)
 114 {
 115         unsigned long addr = (unsigned long)start;
 116
 117         length = ALIGN(length, ARCH_DMA_MINALIGN);
 118         if (is_writing)
 119                 flush_dcache_range(addr, addr + length);
 120         else
 121                 invalidate_dcache_range(addr, addr + length);
 122 }
 123 #endif
 124
 125 /**
 126  * Wait for command completion
 127  *
 128  * @param reg   nand_ctlr structure
 129  * @return
 130  *      1 - Command completed
 131  *      0 - Timeout
 132  */
 133 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
 134 {
 135         u32 reg_val;
 136         int running;
 137         int i;
 138
 139         for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
 140                 if ((readl(&reg->command) & CMD_GO) ||
 141                                 !(readl(&reg->status) & STATUS_RBSY0) ||
 142                                 !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
 143                         udelay(1);
 144                         continue;
 145                 }
 146                 reg_val = readl(&reg->dma_mst_ctrl);
 147                 /*
 148                  * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
 149                  * is set, that means DMA engine is running.
 150                  *
 151                  * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
 152                  * is cleared, indicating DMA transfer completion.
 153                  */
 154                 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
 155                                 DMA_MST_CTRL_EN_B_ENABLE);
 156                 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
 157                         return 1;
 158                 udelay(1);
 159         }
 160         return 0;
 161 }
 162
 163 /**
 164  * Read one byte from the chip
 165  *
 166  * @param mtd   MTD device structure
 167  * @return      data byte
 168  *
 169  * Read function for 8bit bus-width
 170  */
 171 static uint8_t read_byte(struct mtd_info *mtd)
 172 {
 173         struct nand_chip *chip = mtd->priv;
 174         struct nand_drv *info;
 175
 176         info = (struct nand_drv *)chip->priv;
 177
 178         writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
 179                &info->reg->command);
 180         if (!nand_waitfor_cmd_completion(info->reg))
 181                 printf("Command timeout\n");
 182
 183         return (uint8_t)readl(&info->reg->resp);
 184 }
 185
 186 /**
 187  * Read len bytes from the chip into a buffer
 188  *
 189  * @param mtd   MTD device structure
 190  * @param buf   buffer to store data to
 191  * @param len   number of bytes to read
 192  *
 193  * Read function for 8bit bus-width
 194  */
 195 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 196 {
 197         int i, s;
 198         unsigned int reg;
 199         struct nand_chip *chip = mtd->priv;
 200         struct nand_drv *info = (struct nand_drv *)chip->priv;
 201
 202         for (i = 0; i < len; i += 4) {
 203                 s = (len - i) > 4 ? 4 : len - i;
 204                 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
 205                         ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
 206                         &info->reg->command);
 207                 if (!nand_waitfor_cmd_completion(info->reg))
 208                         puts("Command timeout during read_buf\n");
 209                 reg = readl(&info->reg->resp);
 210                 memcpy(buf + i, &reg, s);
 211         }
 212 }
 213
 214 /**
 215  * Check NAND status to see if it is ready or not
 216  *
 217  * @param mtd   MTD device structure
 218  * @return
 219  *      1 - ready
 220  *      0 - not ready
 221  */
 222 static int nand_dev_ready(struct mtd_info *mtd)
 223 {
 224         struct nand_chip *chip = mtd->priv;
 225         int reg_val;
 226         struct nand_drv *info;
 227
 228         info = (struct nand_drv *)chip->priv;
 229
 230         reg_val = readl(&info->reg->status);
 231         if (reg_val & STATUS_RBSY0)
 232                 return 1;
 233         else
 234                 return 0;
 235 }
 236
 237 /* Dummy implementation: we don't support multiple chips */
 238 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 239 {
 240         switch (chipnr) {
 241         case -1:
 242         case 0:
 243                 break;
 244
 245         default:
 246                 BUG();
 247         }
 248 }
 249
 250 /**
 251  * Clear all interrupt status bits
 252  *
 253  * @param reg   nand_ctlr structure
 254  */
 255 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
 256 {
 257         u32 reg_val;
 258
 259         /* Clear interrupt status */
 260         reg_val = readl(&reg->isr);
 261         writel(reg_val, &reg->isr);
 262 }
 263
 264 /**
 265  * Send command to NAND device
 266  *
 267  * @param mtd           MTD device structure
 268  * @param command       the command to be sent
 269  * @param column        the column address for this command, -1 if none
 270  * @param page_addr     the page address for this command, -1 if none
 271  */
 272 static void nand_command(struct mtd_info *mtd, unsigned int command,
 273         int column, int page_addr)
 274 {
 275         struct nand_chip *chip = mtd->priv;
 276         struct nand_drv *info;
 277
 278         info = (struct nand_drv *)chip->priv;
 279
 280         /*
 281          * Write out the command to the device.
 282          *
 283          * Only command NAND_CMD_RESET or NAND_CMD_READID will come
 284          * here before mtd->writesize is initialized.
 285          */
 286
 287         /* Emulate NAND_CMD_READOOB */
 288         if (command == NAND_CMD_READOOB) {
 289                 assert(mtd->writesize != 0);
 290                 column += mtd->writesize;
 291                 command = NAND_CMD_READ0;
 292         }
 293
 294         /* Adjust columns for 16 bit bus-width */
 295         if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
 296                 column >>= 1;
 297
 298         nand_clear_interrupt_status(info->reg);
 299
 300         /* Stop DMA engine, clear DMA completion status */
 301         writel(DMA_MST_CTRL_EN_A_DISABLE
 302                 | DMA_MST_CTRL_EN_B_DISABLE
 303                 | DMA_MST_CTRL_IS_DMA_DONE,
 304                 &info->reg->dma_mst_ctrl);
 305
 306         /*
 307          * Program and erase have their own busy handlers
 308          * status and sequential in needs no delay
 309          */
 310         switch (command) {
 311         case NAND_CMD_READID:
 312                 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
 313                 writel(column & 0xFF, &info->reg->addr_reg1);
 314                 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
 315                        &info->reg->command);
 316                 break;
 317         case NAND_CMD_PARAM:
 318                 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
 319                 writel(column & 0xFF, &info->reg->addr_reg1);
 320                 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
 321                         &info->reg->command);
 322                 break;
 323         case NAND_CMD_READ0:
 324                 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
 325                 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
 326                 writel((page_addr << 16) | (column & 0xFFFF),
 327                         &info->reg->addr_reg1);
 328                 writel(page_addr >> 16, &info->reg->addr_reg2);
 329                 return;
 330         case NAND_CMD_SEQIN:
 331                 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
 332                 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
 333                 writel((page_addr << 16) | (column & 0xFFFF),
 334                         &info->reg->addr_reg1);
 335                 writel(page_addr >> 16,
 336                         &info->reg->addr_reg2);
 337                 return;
 338         case NAND_CMD_PAGEPROG:
 339                 return;
 340         case NAND_CMD_ERASE1:
 341                 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
 342                 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
 343                 writel(page_addr, &info->reg->addr_reg1);
 344                 writel(CMD_GO | CMD_CLE | CMD_ALE |
 345                         CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
 346                         &info->reg->command);
 347                 break;
 348         case NAND_CMD_ERASE2:
 349                 return;
 350         case NAND_CMD_STATUS:
 351                 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
 352                 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
 353                         | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
 354                         | CMD_CE0,
 355                         &info->reg->command);
 356                 break;
 357         case NAND_CMD_RESET:
 358                 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
 359                 writel(CMD_GO | CMD_CLE | CMD_CE0,
 360                         &info->reg->command);
 361                 break;
 362         case NAND_CMD_RNDOUT:
 363         default:
 364                 printf("%s: Unsupported command %d\n", __func__, command);
 365                 return;
 366         }
 367         if (!nand_waitfor_cmd_completion(info->reg))
 368                 printf("Command 0x%02X timeout\n", command);
 369 }
 370
 371 /**
 372  * Check whether the pointed buffer are all 0xff (blank).
 373  *
 374  * @param buf   data buffer for blank check
 375  * @param len   length of the buffer in byte
 376  * @return
 377  *      1 - blank
 378  *      0 - non-blank
 379  */
 380 static int blank_check(u8 *buf, int len)
 381 {
 382         int i;
 383
 384         for (i = 0; i < len; i++)
 385                 if (buf[i] != 0xFF)
 386                         return 0;
 387         return 1;
 388 }
 389
 390 /**
 391  * After a DMA transfer for read, we call this function to see whether there
 392  * is any uncorrectable error on the pointed data buffer or oob buffer.
 393  *
 394  * @param reg           nand_ctlr structure
 395  * @param databuf       data buffer
 396  * @param a_len         data buffer length
 397  * @param oobbuf        oob buffer
 398  * @param b_len         oob buffer length
 399  * @return
 400  *      ECC_OK - no ECC error or correctable ECC error
 401  *      ECC_TAG_ERROR - uncorrectable tag ECC error
 402  *      ECC_DATA_ERROR - uncorrectable data ECC error
 403  *      ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
 404  */
 405 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
 406         int a_len, u8 *oobbuf, int b_len)
 407 {
 408         int return_val = ECC_OK;
 409         u32 reg_val;
 410
 411         if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
 412                 return ECC_OK;
 413
 414         /*
 415          * Area A is used for the data block (databuf). Area B is used for
 416          * the spare block (oobbuf)
 417          */
 418         reg_val = readl(&reg->dec_status);
 419         if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
 420                 reg_val = readl(&reg->bch_dec_status_buf);
 421                 /*
 422                  * If uncorrectable error occurs on data area, then see whether
 423                  * they are all FF. If all are FF, it's a blank page.
 424                  * Not error.
 425                  */
 426                 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
 427                                 !blank_check(databuf, a_len))
 428                         return_val |= ECC_DATA_ERROR;
 429         }
 430
 431         if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
 432                 reg_val = readl(&reg->bch_dec_status_buf);
 433                 /*
 434                  * If uncorrectable error occurs on tag area, then see whether
 435                  * they are all FF. If all are FF, it's a blank page.
 436                  * Not error.
 437                  */
 438                 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
 439                                 !blank_check(oobbuf, b_len))
 440                         return_val |= ECC_TAG_ERROR;
 441         }
 442
 443         return return_val;
 444 }
 445
 446 /**
 447  * Set GO bit to send command to device
 448  *
 449  * @param reg   nand_ctlr structure
 450  */
 451 static void start_command(struct nand_ctlr *reg)
 452 {
 453         u32 reg_val;
 454
 455         reg_val = readl(&reg->command);
 456         reg_val |= CMD_GO;
 457         writel(reg_val, &reg->command);
 458 }
 459
 460 /**
 461  * Clear command GO bit, DMA GO bit, and DMA completion status
 462  *
 463  * @param reg   nand_ctlr structure
 464  */
 465 static void stop_command(struct nand_ctlr *reg)
 466 {
 467         /* Stop command */
 468         writel(0, &reg->command);
 469
 470         /* Stop DMA engine and clear DMA completion status */
 471         writel(DMA_MST_CTRL_GO_DISABLE
 472                 | DMA_MST_CTRL_IS_DMA_DONE,
 473                 &reg->dma_mst_ctrl);
 474 }
 475
 476 /**
 477  * Set up NAND bus width and page size
 478  *
 479  * @param info          nand_info structure
 480  * @param *reg_val      address of reg_val
 481  * @return 0 if ok, -1 on error
 482  */
 483 static int set_bus_width_page_size(struct fdt_nand *config,
 484         u32 *reg_val)
 485 {
 486         if (config->width == 8)
 487                 *reg_val = CFG_BUS_WIDTH_8BIT;
 488         else if (config->width == 16)
 489                 *reg_val = CFG_BUS_WIDTH_16BIT;
 490         else {
 491                 debug("%s: Unsupported bus width %d\n", __func__,
 492                       config->width);
 493                 return -1;
 494         }
 495
 496         if (our_mtd->writesize == 512)
 497                 *reg_val |= CFG_PAGE_SIZE_512;
 498         else if (our_mtd->writesize == 2048)
 499                 *reg_val |= CFG_PAGE_SIZE_2048;
 500         else if (our_mtd->writesize == 4096)
 501                 *reg_val |= CFG_PAGE_SIZE_4096;
 502         else {
 503                 debug("%s: Unsupported page size %d\n", __func__,
 504                       our_mtd->writesize);
 505                 return -1;
 506         }
 507
 508         return 0;
 509 }
 510
 511 /**
 512  * Page read/write function
 513  *
 514  * @param mtd           mtd info structure
 515  * @param chip          nand chip info structure
 516  * @param buf           data buffer
 517  * @param page          page number
 518  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 519  * @param is_writing    0 for read, 1 for write
 520  * @return      0 when successfully completed
 521  *              -EIO when command timeout
 522  */
 523 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 524         uint8_t *buf, int page, int with_ecc, int is_writing)
 525 {
 526         u32 reg_val;
 527         int tag_size;
 528         struct nand_oobfree *free = chip->ecc.layout->oobfree;
 529         /* 4*128=512 (byte) is the value that our HW can support. */
 530         ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
 531         char *tag_ptr;
 532         struct nand_drv *info;
 533         struct fdt_nand *config;
 534
 535         if ((uintptr_t)buf & 0x03) {
 536                 printf("buf %p has to be 4-byte aligned\n", buf);
 537                 return -EINVAL;
 538         }
 539
 540         info = (struct nand_drv *)chip->priv;
 541         config = &info->config;
 542         if (set_bus_width_page_size(config, &reg_val))
 543                 return -EINVAL;
 544
 545         /* Need to be 4-byte aligned */
 546         tag_ptr = (char *)tag_buf;
 547
 548         stop_command(info->reg);
 549
 550         writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
 551         writel(virt_to_phys(buf), &info->reg->data_block_ptr);
 552
 553         if (with_ecc) {
 554                 writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
 555                 if (is_writing)
 556                         memcpy(tag_ptr, chip->oob_poi + free->offset,
 557                                 chip->ecc.layout->oobavail +
 558                                 TAG_ECC_BYTES);
 559         } else {
 560                 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
 561         }
 562
 563         /* Set ECC selection, configure ECC settings */
 564         if (with_ecc) {
 565                 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
 566                 reg_val |= (CFG_SKIP_SPARE_SEL_4
 567                         | CFG_SKIP_SPARE_ENABLE
 568                         | CFG_HW_ECC_CORRECTION_ENABLE
 569                         | CFG_ECC_EN_TAG_DISABLE
 570                         | CFG_HW_ECC_SEL_RS
 571                         | CFG_HW_ECC_ENABLE
 572                         | CFG_TVAL4
 573                         | (tag_size - 1));
 574
 575                 if (!is_writing)
 576                         tag_size += SKIPPED_SPARE_BYTES;
 577                 dma_prepare(tag_ptr, tag_size, is_writing);
 578         } else {
 579                 tag_size = mtd->oobsize;
 580                 reg_val |= (CFG_SKIP_SPARE_DISABLE
 581                         | CFG_HW_ECC_CORRECTION_DISABLE
 582                         | CFG_ECC_EN_TAG_DISABLE
 583                         | CFG_HW_ECC_DISABLE
 584                         | (tag_size - 1));
 585                 dma_prepare(chip->oob_poi, tag_size, is_writing);
 586         }
 587         writel(reg_val, &info->reg->config);
 588
 589         dma_prepare(buf, 1 << chip->page_shift, is_writing);
 590
 591         writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
 592
 593         writel(tag_size - 1, &info->reg->dma_cfg_b);
 594
 595         nand_clear_interrupt_status(info->reg);
 596
 597         reg_val = CMD_CLE | CMD_ALE
 598                 | CMD_SEC_CMD
 599                 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
 600                 | CMD_A_VALID
 601                 | CMD_B_VALID
 602                 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
 603                 | CMD_CE0;
 604         if (!is_writing)
 605                 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
 606         else
 607                 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
 608         writel(reg_val, &info->reg->command);
 609
 610         /* Setup DMA engine */
 611         reg_val = DMA_MST_CTRL_GO_ENABLE
 612                 | DMA_MST_CTRL_BURST_8WORDS
 613                 | DMA_MST_CTRL_EN_A_ENABLE
 614                 | DMA_MST_CTRL_EN_B_ENABLE;
 615
 616         if (!is_writing)
 617                 reg_val |= DMA_MST_CTRL_DIR_READ;
 618         else
 619                 reg_val |= DMA_MST_CTRL_DIR_WRITE;
 620
 621         writel(reg_val, &info->reg->dma_mst_ctrl);
 622
 623         start_command(info->reg);
 624
 625         if (!nand_waitfor_cmd_completion(info->reg)) {
 626                 if (!is_writing)
 627                         printf("Read Page 0x%X timeout ", page);
 628                 else
 629                         printf("Write Page 0x%X timeout ", page);
 630                 if (with_ecc)
 631                         printf("with ECC");
 632                 else
 633                         printf("without ECC");
 634                 printf("\n");
 635                 return -EIO;
 636         }
 637
 638         if (with_ecc && !is_writing) {
 639                 memcpy(chip->oob_poi, tag_ptr,
 640                         SKIPPED_SPARE_BYTES);
 641                 memcpy(chip->oob_poi + free->offset,
 642                         tag_ptr + SKIPPED_SPARE_BYTES,
 643                         chip->ecc.layout->oobavail);
 644                 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
 645                         1 << chip->page_shift,
 646                         (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
 647                         chip->ecc.layout->oobavail);
 648                 if (reg_val & ECC_TAG_ERROR)
 649                         printf("Read Page 0x%X tag ECC error\n", page);
 650                 if (reg_val & ECC_DATA_ERROR)
 651                         printf("Read Page 0x%X data ECC error\n",
 652                                 page);
 653                 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
 654                         return -EIO;
 655         }
 656         return 0;
 657 }
 658
 659 /**
 660  * Hardware ecc based page read function
 661  *
 662  * @param mtd   mtd info structure
 663  * @param chip  nand chip info structure
 664  * @param buf   buffer to store read data
 665  * @param page  page number to read
 666  * @return      0 when successfully completed
 667  *              -EIO when command timeout
 668  */
 669 static int nand_read_page_hwecc(struct mtd_info *mtd,
 670         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 671 {
 672         return nand_rw_page(mtd, chip, buf, page, 1, 0);
 673 }
 674
 675 /**
 676  * Hardware ecc based page write function
 677  *
 678  * @param mtd   mtd info structure
 679  * @param chip  nand chip info structure
 680  * @param buf   data buffer
 681  */
 682 static int nand_write_page_hwecc(struct mtd_info *mtd,
 683         struct nand_chip *chip, const uint8_t *buf, int oob_required)
 684 {
 685         int page;
 686         struct nand_drv *info;
 687
 688         info = (struct nand_drv *)chip->priv;
 689
 690         page = (readl(&info->reg->addr_reg1) >> 16) |
 691                 (readl(&info->reg->addr_reg2) << 16);
 692
 693         nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
 694         return 0;
 695 }
 696
 697
 698 /**
 699  * Read raw page data without ecc
 700  *
 701  * @param mtd   mtd info structure
 702  * @param chip  nand chip info structure
 703  * @param buf   buffer to store read data
 704  * @param page  page number to read
 705  * @return      0 when successfully completed
 706  *              -EINVAL when chip->oob_poi is not double-word aligned
 707  *              -EIO when command timeout
 708  */
 709 static int nand_read_page_raw(struct mtd_info *mtd,
 710         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 711 {
 712         return nand_rw_page(mtd, chip, buf, page, 0, 0);
 713 }
 714
 715 /**
 716  * Raw page write function
 717  *
 718  * @param mtd   mtd info structure
 719  * @param chip  nand chip info structure
 720  * @param buf   data buffer
 721  */
 722 static int nand_write_page_raw(struct mtd_info *mtd,
 723                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 724 {
 725         int page;
 726         struct nand_drv *info;
 727
 728         info = (struct nand_drv *)chip->priv;
 729         page = (readl(&info->reg->addr_reg1) >> 16) |
 730                 (readl(&info->reg->addr_reg2) << 16);
 731
 732         nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
 733         return 0;
 734 }
 735
 736 /**
 737  * OOB data read/write function
 738  *
 739  * @param mtd           mtd info structure
 740  * @param chip          nand chip info structure
 741  * @param page          page number to read
 742  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 743  * @param is_writing    0 for read, 1 for write
 744  * @return      0 when successfully completed
 745  *              -EINVAL when chip->oob_poi is not double-word aligned
 746  *              -EIO when command timeout
 747  */
 748 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 749         int page, int with_ecc, int is_writing)
 750 {
 751         u32 reg_val;
 752         int tag_size;
 753         struct nand_oobfree *free = chip->ecc.layout->oobfree;
 754         struct nand_drv *info;
 755
 756         if (((int)chip->oob_poi) & 0x03)
 757                 return -EINVAL;
 758         info = (struct nand_drv *)chip->priv;
 759         if (set_bus_width_page_size(&info->config, &reg_val))
 760                 return -EINVAL;
 761
 762         stop_command(info->reg);
 763
 764         writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
 765
 766         /* Set ECC selection */
 767         tag_size = mtd->oobsize;
 768         if (with_ecc)
 769                 reg_val |= CFG_ECC_EN_TAG_ENABLE;
 770         else
 771                 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
 772
 773         reg_val |= ((tag_size - 1) |
 774                 CFG_SKIP_SPARE_DISABLE |
 775                 CFG_HW_ECC_CORRECTION_DISABLE |
 776                 CFG_HW_ECC_DISABLE);
 777         writel(reg_val, &info->reg->config);
 778
 779         dma_prepare(chip->oob_poi, tag_size, is_writing);
 780
 781         writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
 782
 783         if (is_writing && with_ecc)
 784                 tag_size -= TAG_ECC_BYTES;
 785
 786         writel(tag_size - 1, &info->reg->dma_cfg_b);
 787
 788         nand_clear_interrupt_status(info->reg);
 789
 790         reg_val = CMD_CLE | CMD_ALE
 791                 | CMD_SEC_CMD
 792                 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
 793                 | CMD_B_VALID
 794                 | CMD_CE0;
 795         if (!is_writing)
 796                 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
 797         else
 798                 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
 799         writel(reg_val, &info->reg->command);
 800
 801         /* Setup DMA engine */
 802         reg_val = DMA_MST_CTRL_GO_ENABLE
 803                 | DMA_MST_CTRL_BURST_8WORDS
 804                 | DMA_MST_CTRL_EN_B_ENABLE;
 805         if (!is_writing)
 806                 reg_val |= DMA_MST_CTRL_DIR_READ;
 807         else
 808                 reg_val |= DMA_MST_CTRL_DIR_WRITE;
 809
 810         writel(reg_val, &info->reg->dma_mst_ctrl);
 811
 812         start_command(info->reg);
 813
 814         if (!nand_waitfor_cmd_completion(info->reg)) {
 815                 if (!is_writing)
 816                         printf("Read OOB of Page 0x%X timeout\n", page);
 817                 else
 818                         printf("Write OOB of Page 0x%X timeout\n", page);
 819                 return -EIO;
 820         }
 821
 822         if (with_ecc && !is_writing) {
 823                 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
 824                         (u8 *)(chip->oob_poi + free->offset),
 825                         chip->ecc.layout->oobavail);
 826                 if (reg_val & ECC_TAG_ERROR)
 827                         printf("Read OOB of Page 0x%X tag ECC error\n", page);
 828         }
 829         return 0;
 830 }
 831
 832 /**
 833  * OOB data read function
 834  *
 835  * @param mtd           mtd info structure
 836  * @param chip          nand chip info structure
 837  * @param page          page number to read
 838  */
 839 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 840         int page)
 841 {
 842         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 843         nand_rw_oob(mtd, chip, page, 0, 0);
 844         return 0;
 845 }
 846
 847 /**
 848  * OOB data write function
 849  *
 850  * @param mtd   mtd info structure
 851  * @param chip  nand chip info structure
 852  * @param page  page number to write
 853  * @return      0 when successfully completed
 854  *              -EINVAL when chip->oob_poi is not double-word aligned
 855  *              -EIO when command timeout
 856  */
 857 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 858         int page)
 859 {
 860         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 861
 862         return nand_rw_oob(mtd, chip, page, 0, 1);
 863 }
 864
 865 /**
 866  * Set up NAND memory timings according to the provided parameters
 867  *
 868  * @param timing        Timing parameters
 869  * @param reg           NAND controller register address
 870  */
 871 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
 872                          struct nand_ctlr *reg)
 873 {
 874         u32 reg_val, clk_rate, clk_period, time_val;
 875
 876         clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
 877                 CLOCK_ID_PERIPH) / 1000000;
 878         clk_period = 1000 / clk_rate;
 879         reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
 880                 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
 881         reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
 882                 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
 883         time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
 884         if (time_val > 2)
 885                 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
 886                         TIMING_TCR_TAR_TRR_CNT_MASK;
 887         reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
 888                 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
 889         time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
 890         if (time_val > 1)
 891                 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
 892                         TIMING_TCS_CNT_MASK;
 893         reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
 894                 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
 895         reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
 896                 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
 897         reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
 898                 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
 899         reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
 900                 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
 901         writel(reg_val, &reg->timing);
 902
 903         reg_val = 0;
 904         time_val = timing[FDT_NAND_TADL] / clk_period;
 905         if (time_val > 2)
 906                 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
 907         writel(reg_val, &reg->timing2);
 908 }
 909
 910 /**
 911  * Decode NAND parameters from the device tree
 912  *
 913  * @param blob  Device tree blob
 914  * @param node  Node containing "nand-flash" compatble node
 915  * @return 0 if ok, -ve on error (FDT_ERR_...)
 916  */
 917 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
 918 {
 919         int err;
 920
 921         config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
 922         config->enabled = fdtdec_get_is_enabled(blob, node);
 923         config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
 924         err = gpio_request_by_name_nodev(blob, node, "nvidia,wp-gpios", 0,
 925                                  &config->wp_gpio, GPIOD_IS_OUT);
 926         if (err)
 927                 return err;
 928         err = fdtdec_get_int_array(blob, node, "nvidia,timing",
 929                         config->timing, FDT_NAND_TIMING_COUNT);
 930         if (err < 0)
 931                 return err;
 932
 933         /* Now look up the controller and decode that */
 934         node = fdt_next_node(blob, node, NULL);
 935         if (node < 0)
 936                 return node;
 937
 938         return 0;
 939 }
 940
 941 /**
 942  * Board-specific NAND initialization
 943  *
 944  * @param nand  nand chip info structure
 945  * @return 0, after initialized, -1 on error
 946  */
 947 int tegra_nand_init(struct nand_chip *nand, int devnum)
 948 {
 949         struct nand_drv *info = &nand_ctrl;
 950         struct fdt_nand *config = &info->config;
 951         int node, ret;
 952
 953         node = fdtdec_next_compatible(gd->fdt_blob, 0,
 954                                       COMPAT_NVIDIA_TEGRA20_NAND);
 955         if (node < 0)
 956                 return -1;
 957         if (fdt_decode_nand(gd->fdt_blob, node, config)) {
 958                 printf("Could not decode nand-flash in device tree\n");
 959                 return -1;
 960         }
 961         if (!config->enabled)
 962                 return -1;
 963         info->reg = config->reg;
 964         nand->ecc.mode = NAND_ECC_HW;
 965         nand->ecc.layout = &eccoob;
 966
 967         nand->options = LP_OPTIONS;
 968         nand->cmdfunc = nand_command;
 969         nand->read_byte = read_byte;
 970         nand->read_buf = read_buf;
 971         nand->ecc.read_page = nand_read_page_hwecc;
 972         nand->ecc.write_page = nand_write_page_hwecc;
 973         nand->ecc.read_page_raw = nand_read_page_raw;
 974         nand->ecc.write_page_raw = nand_write_page_raw;
 975         nand->ecc.read_oob = nand_read_oob;
 976         nand->ecc.write_oob = nand_write_oob;
 977         nand->ecc.strength = 1;
 978         nand->select_chip = nand_select_chip;
 979         nand->dev_ready  = nand_dev_ready;
 980         nand->priv = &nand_ctrl;
 981
 982         /* Adjust controller clock rate */
 983         clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
 984
 985         /* Adjust timing for NAND device */
 986         setup_timing(config->timing, info->reg);
 987
 988         dm_gpio_set_value(&config->wp_gpio, 1);
 989
 990         our_mtd = &nand_info[devnum];
 991         our_mtd->priv = nand;
 992         ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
 993         if (ret)
 994                 return ret;
 995
 996         nand->ecc.size = our_mtd->writesize;
 997         nand->ecc.bytes = our_mtd->oobsize;
 998
 999         ret = nand_scan_tail(our_mtd);
1000         if (ret)
1001                 return ret;
1002
1003         ret = nand_register(devnum);
1004         if (ret)
1005                 return ret;
1006
1007         return 0;
1008 }
1009
1010 void board_nand_init(void)
1011 {
1012         struct nand_chip *nand = &nand_chip[0];
1013
1014         if (tegra_nand_init(nand, 0))
1015                 puts("Tegra NAND init failed\n");
1016 }