1 // SPDX-License-Identifier: GPL-2.0
4 * Chuanhong Guo <gch981213@gmail.com>
7 #include <linux/device.h>
8 #include <linux/kernel.h>
9 #include <linux/mtd/spinand.h>
11 #define SPINAND_MFR_GIGADEVICE 0xC8
12 #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
13 #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
15 #define GD5FXGQ4UEXXG_REG_STATUS2 0xf0
17 static SPINAND_OP_VARIANTS(read_cache_variants,
18 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
19 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
20 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
21 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
22 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
23 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
25 static SPINAND_OP_VARIANTS(write_cache_variants,
26 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
27 SPINAND_PROG_LOAD(true, 0, NULL, 0));
29 static SPINAND_OP_VARIANTS(update_cache_variants,
30 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
31 SPINAND_PROG_LOAD(false, 0, NULL, 0));
33 static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
34 struct mtd_oob_region *region)
39 region->offset = (16 * section) + 8;
45 static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
46 struct mtd_oob_region *region)
52 region->offset = 16 * section;
55 /* section 0 has one byte reserved for bad block mark */
62 static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
65 switch (status & STATUS_ECC_MASK) {
66 case STATUS_ECC_NO_BITFLIPS:
69 case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
70 /* 1-7 bits are flipped. return the maximum. */
73 case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
76 case STATUS_ECC_UNCOR_ERROR:
86 static int gd5fxgq4uexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
87 struct mtd_oob_region *region)
98 static int gd5fxgq4uexxg_ooblayout_free(struct mtd_info *mtd, int section,
99 struct mtd_oob_region *region)
104 /* Reserve 1 bytes for the BBM. */
111 static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
115 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
119 switch (status & STATUS_ECC_MASK) {
120 case STATUS_ECC_NO_BITFLIPS:
123 case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
125 * Read status2 register to determine a more fine grained
128 ret = spi_mem_exec_op(spinand->spimem, &op);
133 * 4 ... 7 bits are flipped (1..4 can't be detected, so
134 * report the maximum of 4 in this case
136 /* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
137 return ((status & STATUS_ECC_MASK) >> 2) |
138 ((status2 & STATUS_ECC_MASK) >> 4);
140 case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
143 case STATUS_ECC_UNCOR_ERROR:
153 static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
154 .ecc = gd5fxgq4xa_ooblayout_ecc,
155 .free = gd5fxgq4xa_ooblayout_free,
158 static const struct mtd_ooblayout_ops gd5fxgq4uexxg_ooblayout = {
159 .ecc = gd5fxgq4uexxg_ooblayout_ecc,
160 .free = gd5fxgq4uexxg_ooblayout_free,
163 static const struct spinand_info gigadevice_spinand_table[] = {
164 SPINAND_INFO("GD5F1GQ4xA", 0xF1,
165 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
167 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
168 &write_cache_variants,
169 &update_cache_variants),
171 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
172 gd5fxgq4xa_ecc_get_status)),
173 SPINAND_INFO("GD5F2GQ4xA", 0xF2,
174 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
176 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
177 &write_cache_variants,
178 &update_cache_variants),
180 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
181 gd5fxgq4xa_ecc_get_status)),
182 SPINAND_INFO("GD5F4GQ4xA", 0xF4,
183 NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
185 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
186 &write_cache_variants,
187 &update_cache_variants),
189 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
190 gd5fxgq4xa_ecc_get_status)),
191 SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
192 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
194 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
195 &write_cache_variants,
196 &update_cache_variants),
198 SPINAND_ECCINFO(&gd5fxgq4uexxg_ooblayout,
199 gd5fxgq4uexxg_ecc_get_status)),
202 static int gigadevice_spinand_detect(struct spinand_device *spinand)
204 u8 *id = spinand->id.data;
208 * For GD NANDs, There is an address byte needed to shift in before IDs
209 * are read out, so the first byte in raw_id is dummy.
211 if (id[1] != SPINAND_MFR_GIGADEVICE)
214 ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
215 ARRAY_SIZE(gigadevice_spinand_table),
223 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
224 .detect = gigadevice_spinand_detect,
227 const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
228 .id = SPINAND_MFR_GIGADEVICE,
229 .name = "GigaDevice",
230 .ops = &gigadevice_spinand_manuf_ops,