1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Micron Technology, Inc.
6 * Peter Pan <peterpandong@micron.com>
7 * Boris Brezillon <boris.brezillon@bootlin.com>
10 #define pr_fmt(fmt) "spi-nand: " fmt
13 #include <linux/device.h>
14 #include <linux/jiffies.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/mtd/spinand.h>
19 #include <linux/slab.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi-mem.h>
27 #include <dm/device_compat.h>
28 #include <dm/devres.h>
29 #include <linux/bitops.h>
30 #include <linux/bug.h>
31 #include <linux/mtd/spinand.h>
34 /* SPI NAND index visible in MTD names */
35 static int spi_nand_idx;
37 static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
38 const struct nand_page_io_req *req,
41 struct nand_device *nand = spinand_to_nand(spinand);
44 if (nand->memorg.planes_per_lun < 2)
47 /* The plane number is passed in MSB just above the column address */
48 shift = fls(nand->memorg.pagesize);
49 *column |= req->pos.plane << shift;
52 static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
54 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
58 ret = spi_mem_exec_op(spinand->slave, &op);
62 *val = *spinand->scratchbuf;
66 static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
68 struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
71 *spinand->scratchbuf = val;
72 return spi_mem_exec_op(spinand->slave, &op);
75 static int spinand_read_status(struct spinand_device *spinand, u8 *status)
77 return spinand_read_reg_op(spinand, REG_STATUS, status);
80 static int spinand_get_cfg(struct spinand_device *spinand, u8 *cfg)
82 struct nand_device *nand = spinand_to_nand(spinand);
84 if (WARN_ON(spinand->cur_target < 0 ||
85 spinand->cur_target >= nand->memorg.ntargets))
88 *cfg = spinand->cfg_cache[spinand->cur_target];
92 static int spinand_set_cfg(struct spinand_device *spinand, u8 cfg)
94 struct nand_device *nand = spinand_to_nand(spinand);
97 if (WARN_ON(spinand->cur_target < 0 ||
98 spinand->cur_target >= nand->memorg.ntargets))
101 if (spinand->cfg_cache[spinand->cur_target] == cfg)
104 ret = spinand_write_reg_op(spinand, REG_CFG, cfg);
108 spinand->cfg_cache[spinand->cur_target] = cfg;
113 * spinand_upd_cfg() - Update the configuration register
114 * @spinand: the spinand device
115 * @mask: the mask encoding the bits to update in the config reg
116 * @val: the new value to apply
118 * Update the configuration register.
120 * Return: 0 on success, a negative error code otherwise.
122 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val)
127 ret = spinand_get_cfg(spinand, &cfg);
134 return spinand_set_cfg(spinand, cfg);
138 * spinand_select_target() - Select a specific NAND target/die
139 * @spinand: the spinand device
140 * @target: the target/die to select
142 * Select a new target/die. If chip only has one die, this function is a NOOP.
144 * Return: 0 on success, a negative error code otherwise.
146 int spinand_select_target(struct spinand_device *spinand, unsigned int target)
148 struct nand_device *nand = spinand_to_nand(spinand);
151 if (WARN_ON(target >= nand->memorg.ntargets))
154 if (spinand->cur_target == target)
157 if (nand->memorg.ntargets == 1) {
158 spinand->cur_target = target;
162 ret = spinand->select_target(spinand, target);
166 spinand->cur_target = target;
170 static int spinand_init_cfg_cache(struct spinand_device *spinand)
172 struct nand_device *nand = spinand_to_nand(spinand);
173 struct udevice *dev = spinand->slave->dev;
177 spinand->cfg_cache = devm_kzalloc(dev,
178 sizeof(*spinand->cfg_cache) *
179 nand->memorg.ntargets,
181 if (!spinand->cfg_cache)
184 for (target = 0; target < nand->memorg.ntargets; target++) {
185 ret = spinand_select_target(spinand, target);
190 * We use spinand_read_reg_op() instead of spinand_get_cfg()
191 * here to bypass the config cache.
193 ret = spinand_read_reg_op(spinand, REG_CFG,
194 &spinand->cfg_cache[target]);
202 static int spinand_init_quad_enable(struct spinand_device *spinand)
206 if (!(spinand->flags & SPINAND_HAS_QE_BIT))
209 if (spinand->op_templates.read_cache->data.buswidth == 4 ||
210 spinand->op_templates.write_cache->data.buswidth == 4 ||
211 spinand->op_templates.update_cache->data.buswidth == 4)
214 return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
215 enable ? CFG_QUAD_ENABLE : 0);
218 static int spinand_ecc_enable(struct spinand_device *spinand,
221 return spinand_upd_cfg(spinand, CFG_ECC_ENABLE,
222 enable ? CFG_ECC_ENABLE : 0);
225 static int spinand_write_enable_op(struct spinand_device *spinand)
227 struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true);
229 return spi_mem_exec_op(spinand->slave, &op);
232 static int spinand_load_page_op(struct spinand_device *spinand,
233 const struct nand_page_io_req *req)
235 struct nand_device *nand = spinand_to_nand(spinand);
236 unsigned int row = nanddev_pos_to_row(nand, &req->pos);
237 struct spi_mem_op op = SPINAND_PAGE_READ_OP(row);
239 return spi_mem_exec_op(spinand->slave, &op);
242 static int spinand_read_from_cache_op(struct spinand_device *spinand,
243 const struct nand_page_io_req *req)
245 struct spi_mem_op op = *spinand->op_templates.read_cache;
246 struct nand_device *nand = spinand_to_nand(spinand);
247 struct mtd_info *mtd = nanddev_to_mtd(nand);
248 struct nand_page_io_req adjreq = *req;
249 unsigned int nbytes = 0;
255 adjreq.datalen = nanddev_page_size(nand);
257 adjreq.databuf.in = spinand->databuf;
258 buf = spinand->databuf;
259 nbytes = adjreq.datalen;
263 adjreq.ooblen = nanddev_per_page_oobsize(nand);
265 adjreq.oobbuf.in = spinand->oobbuf;
266 nbytes += nanddev_per_page_oobsize(nand);
268 buf = spinand->oobbuf;
269 column = nanddev_page_size(nand);
273 spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
274 op.addr.val = column;
277 * Some controllers are limited in term of max RX data size. In this
278 * case, just repeat the READ_CACHE operation after updating the
282 op.data.buf.in = buf;
283 op.data.nbytes = nbytes;
284 ret = spi_mem_adjust_op_size(spinand->slave, &op);
288 ret = spi_mem_exec_op(spinand->slave, &op);
292 buf += op.data.nbytes;
293 nbytes -= op.data.nbytes;
294 op.addr.val += op.data.nbytes;
298 memcpy(req->databuf.in, spinand->databuf + req->dataoffs,
302 if (req->mode == MTD_OPS_AUTO_OOB)
303 mtd_ooblayout_get_databytes(mtd, req->oobbuf.in,
308 memcpy(req->oobbuf.in, spinand->oobbuf + req->ooboffs,
315 static int spinand_write_to_cache_op(struct spinand_device *spinand,
316 const struct nand_page_io_req *req)
318 struct spi_mem_op op = *spinand->op_templates.write_cache;
319 struct nand_device *nand = spinand_to_nand(spinand);
320 struct mtd_info *mtd = nanddev_to_mtd(nand);
321 struct nand_page_io_req adjreq = *req;
322 unsigned int nbytes = 0;
327 memset(spinand->databuf, 0xff,
328 nanddev_page_size(nand) +
329 nanddev_per_page_oobsize(nand));
332 memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
335 adjreq.datalen = nanddev_page_size(nand);
336 adjreq.databuf.out = spinand->databuf;
337 nbytes = adjreq.datalen;
338 buf = spinand->databuf;
342 if (req->mode == MTD_OPS_AUTO_OOB)
343 mtd_ooblayout_set_databytes(mtd, req->oobbuf.out,
348 memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
351 adjreq.ooblen = nanddev_per_page_oobsize(nand);
353 nbytes += nanddev_per_page_oobsize(nand);
355 buf = spinand->oobbuf;
356 column = nanddev_page_size(nand);
360 spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
362 op = *spinand->op_templates.write_cache;
363 op.addr.val = column;
366 * Some controllers are limited in term of max TX data size. In this
367 * case, split the operation into one LOAD CACHE and one or more
371 op.data.buf.out = buf;
372 op.data.nbytes = nbytes;
374 ret = spi_mem_adjust_op_size(spinand->slave, &op);
378 ret = spi_mem_exec_op(spinand->slave, &op);
382 buf += op.data.nbytes;
383 nbytes -= op.data.nbytes;
384 op.addr.val += op.data.nbytes;
387 * We need to use the RANDOM LOAD CACHE operation if there's
388 * more than one iteration, because the LOAD operation resets
392 column = op.addr.val;
393 op = *spinand->op_templates.update_cache;
394 op.addr.val = column;
401 static int spinand_program_op(struct spinand_device *spinand,
402 const struct nand_page_io_req *req)
404 struct nand_device *nand = spinand_to_nand(spinand);
405 unsigned int row = nanddev_pos_to_row(nand, &req->pos);
406 struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row);
408 return spi_mem_exec_op(spinand->slave, &op);
411 static int spinand_erase_op(struct spinand_device *spinand,
412 const struct nand_pos *pos)
414 struct nand_device *nand = &spinand->base;
415 unsigned int row = nanddev_pos_to_row(nand, pos);
416 struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row);
418 return spi_mem_exec_op(spinand->slave, &op);
421 static int spinand_wait(struct spinand_device *spinand, u8 *s)
423 unsigned long start, stop;
427 start = get_timer(0);
430 ret = spinand_read_status(spinand, &status);
434 if (!(status & STATUS_BUSY))
436 } while (get_timer(start) < stop);
439 * Extra read, just in case the STATUS_READY bit has changed
440 * since our last check
442 ret = spinand_read_status(spinand, &status);
450 return status & STATUS_BUSY ? -ETIMEDOUT : 0;
453 static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
455 struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
459 ret = spi_mem_exec_op(spinand->slave, &op);
461 memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
466 static int spinand_reset_op(struct spinand_device *spinand)
468 struct spi_mem_op op = SPINAND_RESET_OP;
471 ret = spi_mem_exec_op(spinand->slave, &op);
475 return spinand_wait(spinand, NULL);
478 static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
480 return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
483 static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status)
485 struct nand_device *nand = spinand_to_nand(spinand);
487 if (spinand->eccinfo.get_status)
488 return spinand->eccinfo.get_status(spinand, status);
490 switch (status & STATUS_ECC_MASK) {
491 case STATUS_ECC_NO_BITFLIPS:
494 case STATUS_ECC_HAS_BITFLIPS:
496 * We have no way to know exactly how many bitflips have been
497 * fixed, so let's return the maximum possible value so that
498 * wear-leveling layers move the data immediately.
500 return nand->eccreq.strength;
502 case STATUS_ECC_UNCOR_ERROR:
512 static int spinand_read_page(struct spinand_device *spinand,
513 const struct nand_page_io_req *req,
519 ret = spinand_load_page_op(spinand, req);
523 ret = spinand_wait(spinand, &status);
527 ret = spinand_read_from_cache_op(spinand, req);
534 return spinand_check_ecc_status(spinand, status);
537 static int spinand_write_page(struct spinand_device *spinand,
538 const struct nand_page_io_req *req)
543 ret = spinand_write_enable_op(spinand);
547 ret = spinand_write_to_cache_op(spinand, req);
551 ret = spinand_program_op(spinand, req);
555 ret = spinand_wait(spinand, &status);
556 if (!ret && (status & STATUS_PROG_FAILED))
562 static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
563 struct mtd_oob_ops *ops)
565 struct spinand_device *spinand = mtd_to_spinand(mtd);
566 struct nand_device *nand = mtd_to_nanddev(mtd);
567 unsigned int max_bitflips = 0;
568 struct nand_io_iter iter;
569 bool enable_ecc = false;
570 bool ecc_failed = false;
573 if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
577 mutex_lock(&spinand->lock);
580 nanddev_io_for_each_page(nand, from, ops, &iter) {
581 ret = spinand_select_target(spinand, iter.req.pos.target);
585 ret = spinand_ecc_enable(spinand, enable_ecc);
589 ret = spinand_read_page(spinand, &iter.req, enable_ecc);
590 if (ret < 0 && ret != -EBADMSG)
593 if (ret == -EBADMSG) {
595 mtd->ecc_stats.failed++;
598 mtd->ecc_stats.corrected += ret;
599 max_bitflips = max_t(unsigned int, max_bitflips, ret);
602 ops->retlen += iter.req.datalen;
603 ops->oobretlen += iter.req.ooblen;
607 mutex_unlock(&spinand->lock);
609 if (ecc_failed && !ret)
612 return ret ? ret : max_bitflips;
615 static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
616 struct mtd_oob_ops *ops)
618 struct spinand_device *spinand = mtd_to_spinand(mtd);
619 struct nand_device *nand = mtd_to_nanddev(mtd);
620 struct nand_io_iter iter;
621 bool enable_ecc = false;
624 if (ops->mode != MTD_OPS_RAW && mtd->ooblayout)
628 mutex_lock(&spinand->lock);
631 nanddev_io_for_each_page(nand, to, ops, &iter) {
632 ret = spinand_select_target(spinand, iter.req.pos.target);
636 ret = spinand_ecc_enable(spinand, enable_ecc);
640 ret = spinand_write_page(spinand, &iter.req);
644 ops->retlen += iter.req.datalen;
645 ops->oobretlen += iter.req.ooblen;
649 mutex_unlock(&spinand->lock);
655 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
657 struct spinand_device *spinand = nand_to_spinand(nand);
659 struct nand_page_io_req req = {
661 .ooblen = sizeof(marker),
668 ret = spinand_select_target(spinand, pos->target);
672 ret = spinand_read_page(spinand, &req, false);
676 if (marker[0] != 0xff || marker[1] != 0xff)
682 static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
684 struct nand_device *nand = mtd_to_nanddev(mtd);
686 struct spinand_device *spinand = nand_to_spinand(nand);
691 nanddev_offs_to_pos(nand, offs, &pos);
693 mutex_lock(&spinand->lock);
695 ret = nanddev_isbad(nand, &pos);
697 mutex_unlock(&spinand->lock);
702 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
704 struct spinand_device *spinand = nand_to_spinand(nand);
706 struct nand_page_io_req req = {
709 .ooblen = sizeof(marker),
710 .oobbuf.out = marker,
715 ret = spinand_select_target(spinand, pos->target);
719 return spinand_write_page(spinand, &req);
722 static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
724 struct nand_device *nand = mtd_to_nanddev(mtd);
726 struct spinand_device *spinand = nand_to_spinand(nand);
731 nanddev_offs_to_pos(nand, offs, &pos);
733 mutex_lock(&spinand->lock);
735 ret = nanddev_markbad(nand, &pos);
737 mutex_unlock(&spinand->lock);
742 static int spinand_erase(struct nand_device *nand, const struct nand_pos *pos)
744 struct spinand_device *spinand = nand_to_spinand(nand);
748 ret = spinand_select_target(spinand, pos->target);
752 ret = spinand_write_enable_op(spinand);
756 ret = spinand_erase_op(spinand, pos);
760 ret = spinand_wait(spinand, &status);
761 if (!ret && (status & STATUS_ERASE_FAILED))
767 static int spinand_mtd_erase(struct mtd_info *mtd,
768 struct erase_info *einfo)
771 struct spinand_device *spinand = mtd_to_spinand(mtd);
776 mutex_lock(&spinand->lock);
778 ret = nanddev_mtd_erase(mtd, einfo);
780 mutex_unlock(&spinand->lock);
786 static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs)
789 struct spinand_device *spinand = mtd_to_spinand(mtd);
791 struct nand_device *nand = mtd_to_nanddev(mtd);
795 nanddev_offs_to_pos(nand, offs, &pos);
797 mutex_lock(&spinand->lock);
799 ret = nanddev_isreserved(nand, &pos);
801 mutex_unlock(&spinand->lock);
807 const struct spi_mem_op *
808 spinand_find_supported_op(struct spinand_device *spinand,
809 const struct spi_mem_op *ops,
814 for (i = 0; i < nops; i++) {
815 if (spi_mem_supports_op(spinand->slave, &ops[i]))
822 static const struct nand_ops spinand_ops = {
823 .erase = spinand_erase,
824 .markbad = spinand_markbad,
825 .isbad = spinand_isbad,
828 static const struct spinand_manufacturer *spinand_manufacturers[] = {
829 &gigadevice_spinand_manufacturer,
830 ¯onix_spinand_manufacturer,
831 µn_spinand_manufacturer,
832 &toshiba_spinand_manufacturer,
833 &winbond_spinand_manufacturer,
836 static int spinand_manufacturer_detect(struct spinand_device *spinand)
841 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
842 ret = spinand_manufacturers[i]->ops->detect(spinand);
844 spinand->manufacturer = spinand_manufacturers[i];
846 } else if (ret < 0) {
854 static int spinand_manufacturer_init(struct spinand_device *spinand)
856 if (spinand->manufacturer->ops->init)
857 return spinand->manufacturer->ops->init(spinand);
862 static void spinand_manufacturer_cleanup(struct spinand_device *spinand)
864 /* Release manufacturer private data */
865 if (spinand->manufacturer->ops->cleanup)
866 return spinand->manufacturer->ops->cleanup(spinand);
869 static const struct spi_mem_op *
870 spinand_select_op_variant(struct spinand_device *spinand,
871 const struct spinand_op_variants *variants)
873 struct nand_device *nand = spinand_to_nand(spinand);
876 for (i = 0; i < variants->nops; i++) {
877 struct spi_mem_op op = variants->ops[i];
881 nbytes = nanddev_per_page_oobsize(nand) +
882 nanddev_page_size(nand);
885 op.data.nbytes = nbytes;
886 ret = spi_mem_adjust_op_size(spinand->slave, &op);
890 if (!spi_mem_supports_op(spinand->slave, &op))
893 nbytes -= op.data.nbytes;
897 return &variants->ops[i];
904 * spinand_match_and_init() - Try to find a match between a device ID and an
905 * entry in a spinand_info table
906 * @spinand: SPI NAND object
907 * @table: SPI NAND device description table
908 * @table_size: size of the device description table
910 * Should be used by SPI NAND manufacturer drivers when they want to find a
911 * match between a device ID retrieved through the READ_ID command and an
912 * entry in the SPI NAND description table. If a match is found, the spinand
913 * object will be initialized with information provided by the matching
914 * spinand_info entry.
916 * Return: 0 on success, a negative error code otherwise.
918 int spinand_match_and_init(struct spinand_device *spinand,
919 const struct spinand_info *table,
920 unsigned int table_size, u8 devid)
922 struct nand_device *nand = spinand_to_nand(spinand);
925 for (i = 0; i < table_size; i++) {
926 const struct spinand_info *info = &table[i];
927 const struct spi_mem_op *op;
929 if (devid != info->devid)
932 nand->memorg = table[i].memorg;
933 nand->eccreq = table[i].eccreq;
934 spinand->eccinfo = table[i].eccinfo;
935 spinand->flags = table[i].flags;
936 spinand->select_target = table[i].select_target;
938 op = spinand_select_op_variant(spinand,
939 info->op_variants.read_cache);
943 spinand->op_templates.read_cache = op;
945 op = spinand_select_op_variant(spinand,
946 info->op_variants.write_cache);
950 spinand->op_templates.write_cache = op;
952 op = spinand_select_op_variant(spinand,
953 info->op_variants.update_cache);
954 spinand->op_templates.update_cache = op;
962 static int spinand_detect(struct spinand_device *spinand)
964 struct nand_device *nand = spinand_to_nand(spinand);
967 ret = spinand_reset_op(spinand);
971 ret = spinand_read_id_op(spinand, spinand->id.data);
975 spinand->id.len = SPINAND_MAX_ID_LEN;
977 ret = spinand_manufacturer_detect(spinand);
979 dev_err(spinand->slave->dev, "unknown raw ID %*phN\n",
980 SPINAND_MAX_ID_LEN, spinand->id.data);
984 if (nand->memorg.ntargets > 1 && !spinand->select_target) {
985 dev_err(spinand->slave->dev,
986 "SPI NANDs with more than one die must implement ->select_target()\n");
990 dev_info(spinand->slave->dev,
991 "%s SPI NAND was found.\n", spinand->manufacturer->name);
992 dev_info(spinand->slave->dev,
993 "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n",
994 nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10,
995 nanddev_page_size(nand), nanddev_per_page_oobsize(nand));
1000 static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section,
1001 struct mtd_oob_region *region)
1006 static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section,
1007 struct mtd_oob_region *region)
1012 /* Reserve 2 bytes for the BBM. */
1014 region->length = 62;
1019 static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = {
1020 .ecc = spinand_noecc_ooblayout_ecc,
1021 .rfree = spinand_noecc_ooblayout_free,
1024 static int spinand_init(struct spinand_device *spinand)
1026 struct mtd_info *mtd = spinand_to_mtd(spinand);
1027 struct nand_device *nand = mtd_to_nanddev(mtd);
1031 * We need a scratch buffer because the spi_mem interface requires that
1032 * buf passed in spi_mem_op->data.buf be DMA-able.
1034 spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
1035 if (!spinand->scratchbuf)
1038 ret = spinand_detect(spinand);
1043 * Use kzalloc() instead of devm_kzalloc() here, because some drivers
1044 * may use this buffer for DMA access.
1045 * Memory allocated by devm_ does not guarantee DMA-safe alignment.
1047 spinand->databuf = kzalloc(nanddev_page_size(nand) +
1048 nanddev_per_page_oobsize(nand),
1050 if (!spinand->databuf) {
1055 spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
1057 ret = spinand_init_cfg_cache(spinand);
1061 ret = spinand_init_quad_enable(spinand);
1065 ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0);
1069 ret = spinand_manufacturer_init(spinand);
1071 dev_err(spinand->slave->dev,
1072 "Failed to initialize the SPI NAND chip (err = %d)\n",
1077 /* After power up, all blocks are locked, so unlock them here. */
1078 for (i = 0; i < nand->memorg.ntargets; i++) {
1079 ret = spinand_select_target(spinand, i);
1083 ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED);
1088 ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
1090 goto err_manuf_cleanup;
1093 * Right now, we don't support ECC, so let the whole oob
1094 * area is available for user.
1096 mtd->_read_oob = spinand_mtd_read;
1097 mtd->_write_oob = spinand_mtd_write;
1098 mtd->_block_isbad = spinand_mtd_block_isbad;
1099 mtd->_block_markbad = spinand_mtd_block_markbad;
1100 mtd->_block_isreserved = spinand_mtd_block_isreserved;
1101 mtd->_erase = spinand_mtd_erase;
1103 if (spinand->eccinfo.ooblayout)
1104 mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout);
1106 mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout);
1108 ret = mtd_ooblayout_count_freebytes(mtd);
1110 goto err_cleanup_nanddev;
1112 mtd->oobavail = ret;
1116 err_cleanup_nanddev:
1117 nanddev_cleanup(nand);
1120 spinand_manufacturer_cleanup(spinand);
1123 kfree(spinand->databuf);
1124 kfree(spinand->scratchbuf);
1128 static void spinand_cleanup(struct spinand_device *spinand)
1130 struct nand_device *nand = spinand_to_nand(spinand);
1132 nanddev_cleanup(nand);
1133 spinand_manufacturer_cleanup(spinand);
1134 kfree(spinand->databuf);
1135 kfree(spinand->scratchbuf);
1138 static int spinand_probe(struct udevice *dev)
1140 struct spinand_device *spinand = dev_get_priv(dev);
1141 struct spi_slave *slave = dev_get_parent_priv(dev);
1142 struct mtd_info *mtd = dev_get_uclass_priv(dev);
1143 struct nand_device *nand = spinand_to_nand(spinand);
1147 spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand),
1152 spinand->spimem = mem;
1153 spi_mem_set_drvdata(mem, spinand);
1154 spinand_set_of_node(spinand, mem->spi->dev.of_node);
1155 mutex_init(&spinand->lock);
1157 mtd = spinand_to_mtd(spinand);
1158 mtd->dev.parent = &mem->spi->dev;
1163 mtd->name = malloc(20);
1166 sprintf(mtd->name, "spi-nand%d", spi_nand_idx++);
1167 spinand->slave = slave;
1168 spinand_set_of_node(spinand, dev->node.np);
1171 ret = spinand_init(spinand);
1176 ret = mtd_device_register(mtd, NULL, 0);
1178 ret = add_mtd_device(mtd);
1181 goto err_spinand_cleanup;
1185 err_spinand_cleanup:
1186 spinand_cleanup(spinand);
1192 static int spinand_remove(struct udevice *slave)
1194 struct spinand_device *spinand;
1195 struct mtd_info *mtd;
1198 spinand = spi_mem_get_drvdata(slave);
1199 mtd = spinand_to_mtd(spinand);
1202 ret = mtd_device_unregister(mtd);
1206 spinand_cleanup(spinand);
1211 static const struct spi_device_id spinand_ids[] = {
1212 { .name = "spi-nand" },
1217 static const struct of_device_id spinand_of_ids[] = {
1218 { .compatible = "spi-nand" },
1223 static struct spi_mem_driver spinand_drv = {
1225 .id_table = spinand_ids,
1228 .of_match_table = of_match_ptr(spinand_of_ids),
1231 .probe = spinand_probe,
1232 .remove = spinand_remove,
1234 module_spi_mem_driver(spinand_drv);
1236 MODULE_DESCRIPTION("SPI NAND framework");
1237 MODULE_AUTHOR("Peter Pan<peterpandong@micron.com>");
1238 MODULE_LICENSE("GPL v2");
1239 #endif /* __UBOOT__ */
1241 static const struct udevice_id spinand_ids[] = {
1242 { .compatible = "spi-nand" },
1246 U_BOOT_DRIVER(spinand) = {
1249 .of_match = spinand_ids,
1250 .priv_auto = sizeof(struct spinand_device),
1251 .probe = spinand_probe,