drivers/mtd/nand/s3c2410.c

   1 /* linux/drivers/mtd/nand/s3c2410.c
   2  *
   3  * Copyright © 2004-2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Samsung S3C2410/S3C2440/S3C2412 NAND driver
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24 #define pr_fmt(fmt) "nand-s3c2410: " fmt
  25
  26 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  27 #define DEBUG
  28 #endif
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/kernel.h>
  34 #include <linux/string.h>
  35 #include <linux/io.h>
  36 #include <linux/ioport.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/delay.h>
  39 #include <linux/err.h>
  40 #include <linux/slab.h>
  41 #include <linux/clk.h>
  42 #include <linux/cpufreq.h>
  43
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/nand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/partitions.h>
  48
  49 #include <linux/platform_data/mtd-nand-s3c2410.h>
  50
  51 #define S3C2410_NFREG(x) (x)
  52
  53 #define S3C2410_NFCONF          S3C2410_NFREG(0x00)
  54 #define S3C2410_NFCMD           S3C2410_NFREG(0x04)
  55 #define S3C2410_NFADDR          S3C2410_NFREG(0x08)
  56 #define S3C2410_NFDATA          S3C2410_NFREG(0x0C)
  57 #define S3C2410_NFSTAT          S3C2410_NFREG(0x10)
  58 #define S3C2410_NFECC           S3C2410_NFREG(0x14)
  59 #define S3C2440_NFCONT          S3C2410_NFREG(0x04)
  60 #define S3C2440_NFCMD           S3C2410_NFREG(0x08)
  61 #define S3C2440_NFADDR          S3C2410_NFREG(0x0C)
  62 #define S3C2440_NFDATA          S3C2410_NFREG(0x10)
  63 #define S3C2440_NFSTAT          S3C2410_NFREG(0x20)
  64 #define S3C2440_NFMECC0         S3C2410_NFREG(0x2C)
  65 #define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
  66 #define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
  67 #define S3C2410_NFCONF_EN               (1<<15)
  68 #define S3C2410_NFCONF_INITECC          (1<<12)
  69 #define S3C2410_NFCONF_nFCE             (1<<11)
  70 #define S3C2410_NFCONF_TACLS(x)         ((x)<<8)
  71 #define S3C2410_NFCONF_TWRPH0(x)        ((x)<<4)
  72 #define S3C2410_NFCONF_TWRPH1(x)        ((x)<<0)
  73 #define S3C2410_NFSTAT_BUSY             (1<<0)
  74 #define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
  75 #define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
  76 #define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
  77 #define S3C2440_NFCONT_INITECC          (1<<4)
  78 #define S3C2440_NFCONT_nFCE             (1<<1)
  79 #define S3C2440_NFCONT_ENABLE           (1<<0)
  80 #define S3C2440_NFSTAT_READY            (1<<0)
  81 #define S3C2412_NFCONF_NANDBOOT         (1<<31)
  82 #define S3C2412_NFCONT_INIT_MAIN_ECC    (1<<5)
  83 #define S3C2412_NFCONT_nFCE0            (1<<1)
  84 #define S3C2412_NFSTAT_READY            (1<<0)
  85
  86 /* new oob placement block for use with hardware ecc generation
  87  */
  88
  89 static struct nand_ecclayout nand_hw_eccoob = {
  90         .eccbytes = 3,
  91         .eccpos = {0, 1, 2},
  92         .oobfree = {{8, 8}}
  93 };
  94
  95 /* controller and mtd information */
  96
  97 struct s3c2410_nand_info;
  98
  99 /**
 100  * struct s3c2410_nand_mtd - driver MTD structure
 101  * @mtd: The MTD instance to pass to the MTD layer.
 102  * @chip: The NAND chip information.
 103  * @set: The platform information supplied for this set of NAND chips.
 104  * @info: Link back to the hardware information.
 105  * @scan_res: The result from calling nand_scan_ident().
 106 */
 107 struct s3c2410_nand_mtd {
 108         struct mtd_info                 mtd;
 109         struct nand_chip                chip;
 110         struct s3c2410_nand_set         *set;
 111         struct s3c2410_nand_info        *info;
 112         int                             scan_res;
 113 };
 114
 115 enum s3c_cpu_type {
 116         TYPE_S3C2410,
 117         TYPE_S3C2412,
 118         TYPE_S3C2440,
 119 };
 120
 121 enum s3c_nand_clk_state {
 122         CLOCK_DISABLE   = 0,
 123         CLOCK_ENABLE,
 124         CLOCK_SUSPEND,
 125 };
 126
 127 /* overview of the s3c2410 nand state */
 128
 129 /**
 130  * struct s3c2410_nand_info - NAND controller state.
 131  * @mtds: An array of MTD instances on this controoler.
 132  * @platform: The platform data for this board.
 133  * @device: The platform device we bound to.
 134  * @clk: The clock resource for this controller.
 135  * @regs: The area mapped for the hardware registers.
 136  * @sel_reg: Pointer to the register controlling the NAND selection.
 137  * @sel_bit: The bit in @sel_reg to select the NAND chip.
 138  * @mtd_count: The number of MTDs created from this controller.
 139  * @save_sel: The contents of @sel_reg to be saved over suspend.
 140  * @clk_rate: The clock rate from @clk.
 141  * @clk_state: The current clock state.
 142  * @cpu_type: The exact type of this controller.
 143  */
 144 struct s3c2410_nand_info {
 145         /* mtd info */
 146         struct nand_hw_control          controller;
 147         struct s3c2410_nand_mtd         *mtds;
 148         struct s3c2410_platform_nand    *platform;
 149
 150         /* device info */
 151         struct device                   *device;
 152         struct clk                      *clk;
 153         void __iomem                    *regs;
 154         void __iomem                    *sel_reg;
 155         int                             sel_bit;
 156         int                             mtd_count;
 157         unsigned long                   save_sel;
 158         unsigned long                   clk_rate;
 159         enum s3c_nand_clk_state         clk_state;
 160
 161         enum s3c_cpu_type               cpu_type;
 162
 163 #ifdef CONFIG_CPU_FREQ
 164         struct notifier_block   freq_transition;
 165 #endif
 166 };
 167
 168 /* conversion functions */
 169
 170 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 171 {
 172         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
 173 }
 174
 175 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 176 {
 177         return s3c2410_nand_mtd_toours(mtd)->info;
 178 }
 179
 180 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 181 {
 182         return platform_get_drvdata(dev);
 183 }
 184
 185 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 186 {
 187         return dev_get_platdata(&dev->dev);
 188 }
 189
 190 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
 191 {
 192 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
 193         return 1;
 194 #else
 195         return 0;
 196 #endif
 197 }
 198
 199 /**
 200  * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
 201  * @info: The controller instance.
 202  * @new_state: State to which clock should be set.
 203  */
 204 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
 205                 enum s3c_nand_clk_state new_state)
 206 {
 207         if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
 208                 return;
 209
 210         if (info->clk_state == CLOCK_ENABLE) {
 211                 if (new_state != CLOCK_ENABLE)
 212                         clk_disable(info->clk);
 213         } else {
 214                 if (new_state == CLOCK_ENABLE)
 215                         clk_enable(info->clk);
 216         }
 217
 218         info->clk_state = new_state;
 219 }
 220
 221 /* timing calculations */
 222
 223 #define NS_IN_KHZ 1000000
 224
 225 /**
 226  * s3c_nand_calc_rate - calculate timing data.
 227  * @wanted: The cycle time in nanoseconds.
 228  * @clk: The clock rate in kHz.
 229  * @max: The maximum divider value.
 230  *
 231  * Calculate the timing value from the given parameters.
 232  */
 233 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
 234 {
 235         int result;
 236
 237         result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
 238
 239         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 240
 241         if (result > max) {
 242                 pr_err("%d ns is too big for current clock rate %ld\n",
 243                         wanted, clk);
 244                 return -1;
 245         }
 246
 247         if (result < 1)
 248                 result = 1;
 249
 250         return result;
 251 }
 252
 253 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 254
 255 /* controller setup */
 256
 257 /**
 258  * s3c2410_nand_setrate - setup controller timing information.
 259  * @info: The controller instance.
 260  *
 261  * Given the information supplied by the platform, calculate and set
 262  * the necessary timing registers in the hardware to generate the
 263  * necessary timing cycles to the hardware.
 264  */
 265 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
 266 {
 267         struct s3c2410_platform_nand *plat = info->platform;
 268         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
 269         int tacls, twrph0, twrph1;
 270         unsigned long clkrate = clk_get_rate(info->clk);
 271         unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
 272         unsigned long flags;
 273
 274         /* calculate the timing information for the controller */
 275
 276         info->clk_rate = clkrate;
 277         clkrate /= 1000;        /* turn clock into kHz for ease of use */
 278
 279         if (plat != NULL) {
 280                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
 281                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
 282                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
 283         } else {
 284                 /* default timings */
 285                 tacls = tacls_max;
 286                 twrph0 = 8;
 287                 twrph1 = 8;
 288         }
 289
 290         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 291                 dev_err(info->device, "cannot get suitable timings\n");
 292                 return -EINVAL;
 293         }
 294
 295         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 296                 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
 297                                                 twrph1, to_ns(twrph1, clkrate));
 298
 299         switch (info->cpu_type) {
 300         case TYPE_S3C2410:
 301                 mask = (S3C2410_NFCONF_TACLS(3) |
 302                         S3C2410_NFCONF_TWRPH0(7) |
 303                         S3C2410_NFCONF_TWRPH1(7));
 304                 set = S3C2410_NFCONF_EN;
 305                 set |= S3C2410_NFCONF_TACLS(tacls - 1);
 306                 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 307                 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 308                 break;
 309
 310         case TYPE_S3C2440:
 311         case TYPE_S3C2412:
 312                 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
 313                         S3C2440_NFCONF_TWRPH0(7) |
 314                         S3C2440_NFCONF_TWRPH1(7));
 315
 316                 set = S3C2440_NFCONF_TACLS(tacls - 1);
 317                 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 318                 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
 319                 break;
 320
 321         default:
 322                 BUG();
 323         }
 324
 325         local_irq_save(flags);
 326
 327         cfg = readl(info->regs + S3C2410_NFCONF);
 328         cfg &= ~mask;
 329         cfg |= set;
 330         writel(cfg, info->regs + S3C2410_NFCONF);
 331
 332         local_irq_restore(flags);
 333
 334         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
 335
 336         return 0;
 337 }
 338
 339 /**
 340  * s3c2410_nand_inithw - basic hardware initialisation
 341  * @info: The hardware state.
 342  *
 343  * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
 344  * to setup the hardware access speeds and set the controller to be enabled.
 345 */
 346 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
 347 {
 348         int ret;
 349
 350         ret = s3c2410_nand_setrate(info);
 351         if (ret < 0)
 352                 return ret;
 353
 354         switch (info->cpu_type) {
 355         case TYPE_S3C2410:
 356         default:
 357                 break;
 358
 359         case TYPE_S3C2440:
 360         case TYPE_S3C2412:
 361                 /* enable the controller and de-assert nFCE */
 362
 363                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
 364         }
 365
 366         return 0;
 367 }
 368
 369 /**
 370  * s3c2410_nand_select_chip - select the given nand chip
 371  * @mtd: The MTD instance for this chip.
 372  * @chip: The chip number.
 373  *
 374  * This is called by the MTD layer to either select a given chip for the
 375  * @mtd instance, or to indicate that the access has finished and the
 376  * chip can be de-selected.
 377  *
 378  * The routine ensures that the nFCE line is correctly setup, and any
 379  * platform specific selection code is called to route nFCE to the specific
 380  * chip.
 381  */
 382 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
 383 {
 384         struct s3c2410_nand_info *info;
 385         struct s3c2410_nand_mtd *nmtd;
 386         struct nand_chip *this = mtd->priv;
 387         unsigned long cur;
 388
 389         nmtd = this->priv;
 390         info = nmtd->info;
 391
 392         if (chip != -1)
 393                 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
 394
 395         cur = readl(info->sel_reg);
 396
 397         if (chip == -1) {
 398                 cur |= info->sel_bit;
 399         } else {
 400                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 401                         dev_err(info->device, "invalid chip %d\n", chip);
 402                         return;
 403                 }
 404
 405                 if (info->platform != NULL) {
 406                         if (info->platform->select_chip != NULL)
 407                                 (info->platform->select_chip) (nmtd->set, chip);
 408                 }
 409
 410                 cur &= ~info->sel_bit;
 411         }
 412
 413         writel(cur, info->sel_reg);
 414
 415         if (chip == -1)
 416                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
 417 }
 418
 419 /* s3c2410_nand_hwcontrol
 420  *
 421  * Issue command and address cycles to the chip
 422 */
 423
 424 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 425                                    unsigned int ctrl)
 426 {
 427         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 428
 429         if (cmd == NAND_CMD_NONE)
 430                 return;
 431
 432         if (ctrl & NAND_CLE)
 433                 writeb(cmd, info->regs + S3C2410_NFCMD);
 434         else
 435                 writeb(cmd, info->regs + S3C2410_NFADDR);
 436 }
 437
 438 /* command and control functions */
 439
 440 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 441                                    unsigned int ctrl)
 442 {
 443         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 444
 445         if (cmd == NAND_CMD_NONE)
 446                 return;
 447
 448         if (ctrl & NAND_CLE)
 449                 writeb(cmd, info->regs + S3C2440_NFCMD);
 450         else
 451                 writeb(cmd, info->regs + S3C2440_NFADDR);
 452 }
 453
 454 /* s3c2410_nand_devready()
 455  *
 456  * returns 0 if the nand is busy, 1 if it is ready
 457 */
 458
 459 static int s3c2410_nand_devready(struct mtd_info *mtd)
 460 {
 461         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 462         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 463 }
 464
 465 static int s3c2440_nand_devready(struct mtd_info *mtd)
 466 {
 467         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 468         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 469 }
 470
 471 static int s3c2412_nand_devready(struct mtd_info *mtd)
 472 {
 473         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 474         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
 475 }
 476
 477 /* ECC handling functions */
 478
 479 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
 480 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 481                                      u_char *read_ecc, u_char *calc_ecc)
 482 {
 483         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 484         unsigned int diff0, diff1, diff2;
 485         unsigned int bit, byte;
 486
 487         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
 488
 489         diff0 = read_ecc[0] ^ calc_ecc[0];
 490         diff1 = read_ecc[1] ^ calc_ecc[1];
 491         diff2 = read_ecc[2] ^ calc_ecc[2];
 492
 493         pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
 494                  __func__, 3, read_ecc, 3, calc_ecc,
 495                  diff0, diff1, diff2);
 496
 497         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
 498                 return 0;               /* ECC is ok */
 499
 500         /* sometimes people do not think about using the ECC, so check
 501          * to see if we have an 0xff,0xff,0xff read ECC and then ignore
 502          * the error, on the assumption that this is an un-eccd page.
 503          */
 504         if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
 505             && info->platform->ignore_unset_ecc)
 506                 return 0;
 507
 508         /* Can we correct this ECC (ie, one row and column change).
 509          * Note, this is similar to the 256 error code on smartmedia */
 510
 511         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
 512             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
 513             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
 514                 /* calculate the bit position of the error */
 515
 516                 bit  = ((diff2 >> 3) & 1) |
 517                        ((diff2 >> 4) & 2) |
 518                        ((diff2 >> 5) & 4);
 519
 520                 /* calculate the byte position of the error */
 521
 522                 byte = ((diff2 << 7) & 0x100) |
 523                        ((diff1 << 0) & 0x80)  |
 524                        ((diff1 << 1) & 0x40)  |
 525                        ((diff1 << 2) & 0x20)  |
 526                        ((diff1 << 3) & 0x10)  |
 527                        ((diff0 >> 4) & 0x08)  |
 528                        ((diff0 >> 3) & 0x04)  |
 529                        ((diff0 >> 2) & 0x02)  |
 530                        ((diff0 >> 1) & 0x01);
 531
 532                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
 533                         bit, byte);
 534
 535                 dat[byte] ^= (1 << bit);
 536                 return 1;
 537         }
 538
 539         /* if there is only one bit difference in the ECC, then
 540          * one of only a row or column parity has changed, which
 541          * means the error is most probably in the ECC itself */
 542
 543         diff0 |= (diff1 << 8);
 544         diff0 |= (diff2 << 16);
 545
 546         if ((diff0 & ~(1<<fls(diff0))) == 0)
 547                 return 1;
 548
 549         return -1;
 550 }
 551
 552 /* ECC functions
 553  *
 554  * These allow the s3c2410 and s3c2440 to use the controller's ECC
 555  * generator block to ECC the data as it passes through]
 556 */
 557
 558 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 559 {
 560         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 561         unsigned long ctrl;
 562
 563         ctrl = readl(info->regs + S3C2410_NFCONF);
 564         ctrl |= S3C2410_NFCONF_INITECC;
 565         writel(ctrl, info->regs + S3C2410_NFCONF);
 566 }
 567
 568 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 569 {
 570         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 571         unsigned long ctrl;
 572
 573         ctrl = readl(info->regs + S3C2440_NFCONT);
 574         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
 575                info->regs + S3C2440_NFCONT);
 576 }
 577
 578 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 579 {
 580         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 581         unsigned long ctrl;
 582
 583         ctrl = readl(info->regs + S3C2440_NFCONT);
 584         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 585 }
 586
 587 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 588                                       u_char *ecc_code)
 589 {
 590         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 591
 592         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 593         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 594         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 595
 596         pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
 597
 598         return 0;
 599 }
 600
 601 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 602                                       u_char *ecc_code)
 603 {
 604         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 605         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
 606
 607         ecc_code[0] = ecc;
 608         ecc_code[1] = ecc >> 8;
 609         ecc_code[2] = ecc >> 16;
 610
 611         pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
 612
 613         return 0;
 614 }
 615
 616 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 617                                       u_char *ecc_code)
 618 {
 619         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 620         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 621
 622         ecc_code[0] = ecc;
 623         ecc_code[1] = ecc >> 8;
 624         ecc_code[2] = ecc >> 16;
 625
 626         pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
 627
 628         return 0;
 629 }
 630 #endif
 631
 632 /* over-ride the standard functions for a little more speed. We can
 633  * use read/write block to move the data buffers to/from the controller
 634 */
 635
 636 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 637 {
 638         struct nand_chip *this = mtd->priv;
 639         readsb(this->IO_ADDR_R, buf, len);
 640 }
 641
 642 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 643 {
 644         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 645
 646         readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 647
 648         /* cleanup if we've got less than a word to do */
 649         if (len & 3) {
 650                 buf += len & ~3;
 651
 652                 for (; len & 3; len--)
 653                         *buf++ = readb(info->regs + S3C2440_NFDATA);
 654         }
 655 }
 656
 657 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
 658                                    int len)
 659 {
 660         struct nand_chip *this = mtd->priv;
 661         writesb(this->IO_ADDR_W, buf, len);
 662 }
 663
 664 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
 665                                    int len)
 666 {
 667         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 668
 669         writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 670
 671         /* cleanup any fractional write */
 672         if (len & 3) {
 673                 buf += len & ~3;
 674
 675                 for (; len & 3; len--, buf++)
 676                         writeb(*buf, info->regs + S3C2440_NFDATA);
 677         }
 678 }
 679
 680 /* cpufreq driver support */
 681
 682 #ifdef CONFIG_CPU_FREQ
 683
 684 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
 685                                           unsigned long val, void *data)
 686 {
 687         struct s3c2410_nand_info *info;
 688         unsigned long newclk;
 689
 690         info = container_of(nb, struct s3c2410_nand_info, freq_transition);
 691         newclk = clk_get_rate(info->clk);
 692
 693         if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
 694             (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
 695                 s3c2410_nand_setrate(info);
 696         }
 697
 698         return 0;
 699 }
 700
 701 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 702 {
 703         info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
 704
 705         return cpufreq_register_notifier(&info->freq_transition,
 706                                          CPUFREQ_TRANSITION_NOTIFIER);
 707 }
 708
 709 static inline void
 710 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 711 {
 712         cpufreq_unregister_notifier(&info->freq_transition,
 713                                     CPUFREQ_TRANSITION_NOTIFIER);
 714 }
 715
 716 #else
 717 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 718 {
 719         return 0;
 720 }
 721
 722 static inline void
 723 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 724 {
 725 }
 726 #endif
 727
 728 /* device management functions */
 729
 730 static int s3c24xx_nand_remove(struct platform_device *pdev)
 731 {
 732         struct s3c2410_nand_info *info = to_nand_info(pdev);
 733
 734         if (info == NULL)
 735                 return 0;
 736
 737         s3c2410_nand_cpufreq_deregister(info);
 738
 739         /* Release all our mtds  and their partitions, then go through
 740          * freeing the resources used
 741          */
 742
 743         if (info->mtds != NULL) {
 744                 struct s3c2410_nand_mtd *ptr = info->mtds;
 745                 int mtdno;
 746
 747                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 748                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 749                         nand_release(&ptr->mtd);
 750                 }
 751         }
 752
 753         /* free the common resources */
 754
 755         if (!IS_ERR(info->clk))
 756                 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
 757
 758         return 0;
 759 }
 760
 761 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 762                                       struct s3c2410_nand_mtd *mtd,
 763                                       struct s3c2410_nand_set *set)
 764 {
 765         if (set) {
 766                 mtd->mtd.name = set->name;
 767
 768                 return mtd_device_parse_register(&mtd->mtd, NULL, NULL,
 769                                          set->partitions, set->nr_partitions);
 770         }
 771
 772         return -ENODEV;
 773 }
 774
 775 /**
 776  * s3c2410_nand_init_chip - initialise a single instance of an chip
 777  * @info: The base NAND controller the chip is on.
 778  * @nmtd: The new controller MTD instance to fill in.
 779  * @set: The information passed from the board specific platform data.
 780  *
 781  * Initialise the given @nmtd from the information in @info and @set. This
 782  * readies the structure for use with the MTD layer functions by ensuring
 783  * all pointers are setup and the necessary control routines selected.
 784  */
 785 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 786                                    struct s3c2410_nand_mtd *nmtd,
 787                                    struct s3c2410_nand_set *set)
 788 {
 789         struct nand_chip *chip = &nmtd->chip;
 790         void __iomem *regs = info->regs;
 791
 792         chip->write_buf    = s3c2410_nand_write_buf;
 793         chip->read_buf     = s3c2410_nand_read_buf;
 794         chip->select_chip  = s3c2410_nand_select_chip;
 795         chip->chip_delay   = 50;
 796         chip->priv         = nmtd;
 797         chip->options      = set->options;
 798         chip->controller   = &info->controller;
 799
 800         switch (info->cpu_type) {
 801         case TYPE_S3C2410:
 802                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
 803                 info->sel_reg   = regs + S3C2410_NFCONF;
 804                 info->sel_bit   = S3C2410_NFCONF_nFCE;
 805                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
 806                 chip->dev_ready = s3c2410_nand_devready;
 807                 break;
 808
 809         case TYPE_S3C2440:
 810                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 811                 info->sel_reg   = regs + S3C2440_NFCONT;
 812                 info->sel_bit   = S3C2440_NFCONT_nFCE;
 813                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 814                 chip->dev_ready = s3c2440_nand_devready;
 815                 chip->read_buf  = s3c2440_nand_read_buf;
 816                 chip->write_buf = s3c2440_nand_write_buf;
 817                 break;
 818
 819         case TYPE_S3C2412:
 820                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 821                 info->sel_reg   = regs + S3C2440_NFCONT;
 822                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
 823                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 824                 chip->dev_ready = s3c2412_nand_devready;
 825
 826                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
 827                         dev_info(info->device, "System booted from NAND\n");
 828
 829                 break;
 830         }
 831
 832         chip->IO_ADDR_R = chip->IO_ADDR_W;
 833
 834         nmtd->info         = info;
 835         nmtd->mtd.priv     = chip;
 836         nmtd->mtd.owner    = THIS_MODULE;
 837         nmtd->set          = set;
 838
 839 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
 840         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 841         chip->ecc.correct   = s3c2410_nand_correct_data;
 842         chip->ecc.mode      = NAND_ECC_HW;
 843         chip->ecc.strength  = 1;
 844
 845         switch (info->cpu_type) {
 846         case TYPE_S3C2410:
 847                 chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
 848                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 849                 break;
 850
 851         case TYPE_S3C2412:
 852                 chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
 853                 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
 854                 break;
 855
 856         case TYPE_S3C2440:
 857                 chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
 858                 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
 859                 break;
 860         }
 861 #else
 862         chip->ecc.mode      = NAND_ECC_SOFT;
 863 #endif
 864
 865         if (set->ecc_layout != NULL)
 866                 chip->ecc.layout = set->ecc_layout;
 867
 868         if (set->disable_ecc)
 869                 chip->ecc.mode  = NAND_ECC_NONE;
 870
 871         switch (chip->ecc.mode) {
 872         case NAND_ECC_NONE:
 873                 dev_info(info->device, "NAND ECC disabled\n");
 874                 break;
 875         case NAND_ECC_SOFT:
 876                 dev_info(info->device, "NAND soft ECC\n");
 877                 break;
 878         case NAND_ECC_HW:
 879                 dev_info(info->device, "NAND hardware ECC\n");
 880                 break;
 881         default:
 882                 dev_info(info->device, "NAND ECC UNKNOWN\n");
 883                 break;
 884         }
 885
 886         /* If you use u-boot BBT creation code, specifying this flag will
 887          * let the kernel fish out the BBT from the NAND, and also skip the
 888          * full NAND scan that can take 1/2s or so. Little things... */
 889         if (set->flash_bbt) {
 890                 chip->bbt_options |= NAND_BBT_USE_FLASH;
 891                 chip->options |= NAND_SKIP_BBTSCAN;
 892         }
 893 }
 894
 895 /**
 896  * s3c2410_nand_update_chip - post probe update
 897  * @info: The controller instance.
 898  * @nmtd: The driver version of the MTD instance.
 899  *
 900  * This routine is called after the chip probe has successfully completed
 901  * and the relevant per-chip information updated. This call ensure that
 902  * we update the internal state accordingly.
 903  *
 904  * The internal state is currently limited to the ECC state information.
 905 */
 906 static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
 907                                      struct s3c2410_nand_mtd *nmtd)
 908 {
 909         struct nand_chip *chip = &nmtd->chip;
 910
 911         dev_dbg(info->device, "chip %p => page shift %d\n",
 912                 chip, chip->page_shift);
 913
 914         if (chip->ecc.mode != NAND_ECC_HW)
 915                 return;
 916
 917                 /* change the behaviour depending on whether we are using
 918                  * the large or small page nand device */
 919
 920         if (chip->page_shift > 10) {
 921                 chip->ecc.size      = 256;
 922                 chip->ecc.bytes     = 3;
 923         } else {
 924                 chip->ecc.size      = 512;
 925                 chip->ecc.bytes     = 3;
 926                 chip->ecc.layout    = &nand_hw_eccoob;
 927         }
 928 }
 929
 930 /* s3c24xx_nand_probe
 931  *
 932  * called by device layer when it finds a device matching
 933  * one our driver can handled. This code checks to see if
 934  * it can allocate all necessary resources then calls the
 935  * nand layer to look for devices
 936 */
 937 static int s3c24xx_nand_probe(struct platform_device *pdev)
 938 {
 939         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 940         enum s3c_cpu_type cpu_type;
 941         struct s3c2410_nand_info *info;
 942         struct s3c2410_nand_mtd *nmtd;
 943         struct s3c2410_nand_set *sets;
 944         struct resource *res;
 945         int err = 0;
 946         int size;
 947         int nr_sets;
 948         int setno;
 949
 950         cpu_type = platform_get_device_id(pdev)->driver_data;
 951
 952         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
 953
 954         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
 955         if (info == NULL) {
 956                 err = -ENOMEM;
 957                 goto exit_error;
 958         }
 959
 960         platform_set_drvdata(pdev, info);
 961
 962         spin_lock_init(&info->controller.lock);
 963         init_waitqueue_head(&info->controller.wq);
 964
 965         /* get the clock source and enable it */
 966
 967         info->clk = devm_clk_get(&pdev->dev, "nand");
 968         if (IS_ERR(info->clk)) {
 969                 dev_err(&pdev->dev, "failed to get clock\n");
 970                 err = -ENOENT;
 971                 goto exit_error;
 972         }
 973
 974         s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
 975
 976         /* allocate and map the resource */
 977
 978         /* currently we assume we have the one resource */
 979         res = pdev->resource;
 980         size = resource_size(res);
 981
 982         info->device    = &pdev->dev;
 983         info->platform  = plat;
 984         info->cpu_type  = cpu_type;
 985
 986         info->regs = devm_ioremap_resource(&pdev->dev, res);
 987         if (IS_ERR(info->regs)) {
 988                 err = PTR_ERR(info->regs);
 989                 goto exit_error;
 990         }
 991
 992         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
 993
 994         /* initialise the hardware */
 995
 996         err = s3c2410_nand_inithw(info);
 997         if (err != 0)
 998                 goto exit_error;
 999
1000         sets = (plat != NULL) ? plat->sets : NULL;
1001         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
1002
1003         info->mtd_count = nr_sets;
1004
1005         /* allocate our information */
1006
1007         size = nr_sets * sizeof(*info->mtds);
1008         info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1009         if (info->mtds == NULL) {
1010                 err = -ENOMEM;
1011                 goto exit_error;
1012         }
1013
1014         /* initialise all possible chips */
1015
1016         nmtd = info->mtds;
1017
1018         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
1019                 pr_debug("initialising set %d (%p, info %p)\n",
1020                          setno, nmtd, info);
1021
1022                 s3c2410_nand_init_chip(info, nmtd, sets);
1023
1024                 nmtd->scan_res = nand_scan_ident(&nmtd->mtd,
1025                                                  (sets) ? sets->nr_chips : 1,
1026                                                  NULL);
1027
1028                 if (nmtd->scan_res == 0) {
1029                         s3c2410_nand_update_chip(info, nmtd);
1030                         nand_scan_tail(&nmtd->mtd);
1031                         s3c2410_nand_add_partition(info, nmtd, sets);
1032                 }
1033
1034                 if (sets != NULL)
1035                         sets++;
1036         }
1037
1038         err = s3c2410_nand_cpufreq_register(info);
1039         if (err < 0) {
1040                 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1041                 goto exit_error;
1042         }
1043
1044         if (allow_clk_suspend(info)) {
1045                 dev_info(&pdev->dev, "clock idle support enabled\n");
1046                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1047         }
1048
1049         pr_debug("initialised ok\n");
1050         return 0;
1051
1052  exit_error:
1053         s3c24xx_nand_remove(pdev);
1054
1055         if (err == 0)
1056                 err = -EINVAL;
1057         return err;
1058 }
1059
1060 /* PM Support */
1061 #ifdef CONFIG_PM
1062
1063 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1064 {
1065         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1066
1067         if (info) {
1068                 info->save_sel = readl(info->sel_reg);
1069
1070                 /* For the moment, we must ensure nFCE is high during
1071                  * the time we are suspended. This really should be
1072                  * handled by suspending the MTDs we are using, but
1073                  * that is currently not the case. */
1074
1075                 writel(info->save_sel | info->sel_bit, info->sel_reg);
1076
1077                 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1078         }
1079
1080         return 0;
1081 }
1082
1083 static int s3c24xx_nand_resume(struct platform_device *dev)
1084 {
1085         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1086         unsigned long sel;
1087
1088         if (info) {
1089                 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1090                 s3c2410_nand_inithw(info);
1091
1092                 /* Restore the state of the nFCE line. */
1093
1094                 sel = readl(info->sel_reg);
1095                 sel &= ~info->sel_bit;
1096                 sel |= info->save_sel & info->sel_bit;
1097                 writel(sel, info->sel_reg);
1098
1099                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1100         }
1101
1102         return 0;
1103 }
1104
1105 #else
1106 #define s3c24xx_nand_suspend NULL
1107 #define s3c24xx_nand_resume NULL
1108 #endif
1109
1110 /* driver device registration */
1111
1112 static struct platform_device_id s3c24xx_driver_ids[] = {
1113         {
1114                 .name           = "s3c2410-nand",
1115                 .driver_data    = TYPE_S3C2410,
1116         }, {
1117                 .name           = "s3c2440-nand",
1118                 .driver_data    = TYPE_S3C2440,
1119         }, {
1120                 .name           = "s3c2412-nand",
1121                 .driver_data    = TYPE_S3C2412,
1122         }, {
1123                 .name           = "s3c6400-nand",
1124                 .driver_data    = TYPE_S3C2412, /* compatible with 2412 */
1125         },
1126         { }
1127 };
1128
1129 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1130
1131 static struct platform_driver s3c24xx_nand_driver = {
1132         .probe          = s3c24xx_nand_probe,
1133         .remove         = s3c24xx_nand_remove,
1134         .suspend        = s3c24xx_nand_suspend,
1135         .resume         = s3c24xx_nand_resume,
1136         .id_table       = s3c24xx_driver_ids,
1137         .driver         = {
1138                 .name   = "s3c24xx-nand",
1139                 .owner  = THIS_MODULE,
1140         },
1141 };
1142
1143 module_platform_driver(s3c24xx_nand_driver);
1144
1145 MODULE_LICENSE("GPL");
1146 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1147 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");