drivers/mtd/nand/s3c2410.c

   1 /* linux/drivers/mtd/nand/s3c2410.c
   2  *
   3  * Copyright © 2004-2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Samsung S3C2410/S3C2440/S3C2412 NAND driver
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  25 #define DEBUG
  26 #endif
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/string.h>
  33 #include <linux/ioport.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/delay.h>
  36 #include <linux/err.h>
  37 #include <linux/slab.h>
  38 #include <linux/clk.h>
  39 #include <linux/cpufreq.h>
  40
  41 #include <linux/mtd/mtd.h>
  42 #include <linux/mtd/nand.h>
  43 #include <linux/mtd/nand_ecc.h>
  44 #include <linux/mtd/partitions.h>
  45
  46 #include <asm/io.h>
  47
  48 #include <plat/regs-nand.h>
  49 #include <plat/nand.h>
  50
  51 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
  52 static int hardware_ecc = 1;
  53 #else
  54 static int hardware_ecc = 0;
  55 #endif
  56
  57 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
  58 static int clock_stop = 1;
  59 #else
  60 static const int clock_stop = 0;
  61 #endif
  62
  63
  64 /* new oob placement block for use with hardware ecc generation
  65  */
  66
  67 static struct nand_ecclayout nand_hw_eccoob = {
  68         .eccbytes = 3,
  69         .eccpos = {0, 1, 2},
  70         .oobfree = {{8, 8}}
  71 };
  72
  73 /* controller and mtd information */
  74
  75 struct s3c2410_nand_info;
  76
  77 /**
  78  * struct s3c2410_nand_mtd - driver MTD structure
  79  * @mtd: The MTD instance to pass to the MTD layer.
  80  * @chip: The NAND chip information.
  81  * @set: The platform information supplied for this set of NAND chips.
  82  * @info: Link back to the hardware information.
  83  * @scan_res: The result from calling nand_scan_ident().
  84 */
  85 struct s3c2410_nand_mtd {
  86         struct mtd_info                 mtd;
  87         struct nand_chip                chip;
  88         struct s3c2410_nand_set         *set;
  89         struct s3c2410_nand_info        *info;
  90         int                             scan_res;
  91 };
  92
  93 enum s3c_cpu_type {
  94         TYPE_S3C2410,
  95         TYPE_S3C2412,
  96         TYPE_S3C2440,
  97 };
  98
  99 /* overview of the s3c2410 nand state */
 100
 101 /**
 102  * struct s3c2410_nand_info - NAND controller state.
 103  * @mtds: An array of MTD instances on this controoler.
 104  * @platform: The platform data for this board.
 105  * @device: The platform device we bound to.
 106  * @area: The IO area resource that came from request_mem_region().
 107  * @clk: The clock resource for this controller.
 108  * @regs: The area mapped for the hardware registers described by @area.
 109  * @sel_reg: Pointer to the register controlling the NAND selection.
 110  * @sel_bit: The bit in @sel_reg to select the NAND chip.
 111  * @mtd_count: The number of MTDs created from this controller.
 112  * @save_sel: The contents of @sel_reg to be saved over suspend.
 113  * @clk_rate: The clock rate from @clk.
 114  * @cpu_type: The exact type of this controller.
 115  */
 116 struct s3c2410_nand_info {
 117         /* mtd info */
 118         struct nand_hw_control          controller;
 119         struct s3c2410_nand_mtd         *mtds;
 120         struct s3c2410_platform_nand    *platform;
 121
 122         /* device info */
 123         struct device                   *device;
 124         struct resource                 *area;
 125         struct clk                      *clk;
 126         void __iomem                    *regs;
 127         void __iomem                    *sel_reg;
 128         int                             sel_bit;
 129         int                             mtd_count;
 130         unsigned long                   save_sel;
 131         unsigned long                   clk_rate;
 132
 133         enum s3c_cpu_type               cpu_type;
 134
 135 #ifdef CONFIG_CPU_FREQ
 136         struct notifier_block   freq_transition;
 137 #endif
 138 };
 139
 140 /* conversion functions */
 141
 142 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 143 {
 144         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
 145 }
 146
 147 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 148 {
 149         return s3c2410_nand_mtd_toours(mtd)->info;
 150 }
 151
 152 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 153 {
 154         return platform_get_drvdata(dev);
 155 }
 156
 157 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 158 {
 159         return dev->dev.platform_data;
 160 }
 161
 162 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
 163 {
 164         return clock_stop;
 165 }
 166
 167 /* timing calculations */
 168
 169 #define NS_IN_KHZ 1000000
 170
 171 /**
 172  * s3c_nand_calc_rate - calculate timing data.
 173  * @wanted: The cycle time in nanoseconds.
 174  * @clk: The clock rate in kHz.
 175  * @max: The maximum divider value.
 176  *
 177  * Calculate the timing value from the given parameters.
 178  */
 179 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
 180 {
 181         int result;
 182
 183         result = (wanted * clk) / NS_IN_KHZ;
 184         result++;
 185
 186         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 187
 188         if (result > max) {
 189                 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
 190                 return -1;
 191         }
 192
 193         if (result < 1)
 194                 result = 1;
 195
 196         return result;
 197 }
 198
 199 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 200
 201 /* controller setup */
 202
 203 /**
 204  * s3c2410_nand_setrate - setup controller timing information.
 205  * @info: The controller instance.
 206  *
 207  * Given the information supplied by the platform, calculate and set
 208  * the necessary timing registers in the hardware to generate the
 209  * necessary timing cycles to the hardware.
 210  */
 211 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
 212 {
 213         struct s3c2410_platform_nand *plat = info->platform;
 214         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
 215         int tacls, twrph0, twrph1;
 216         unsigned long clkrate = clk_get_rate(info->clk);
 217         unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
 218         unsigned long flags;
 219
 220         /* calculate the timing information for the controller */
 221
 222         info->clk_rate = clkrate;
 223         clkrate /= 1000;        /* turn clock into kHz for ease of use */
 224
 225         if (plat != NULL) {
 226                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
 227                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
 228                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
 229         } else {
 230                 /* default timings */
 231                 tacls = tacls_max;
 232                 twrph0 = 8;
 233                 twrph1 = 8;
 234         }
 235
 236         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 237                 dev_err(info->device, "cannot get suitable timings\n");
 238                 return -EINVAL;
 239         }
 240
 241         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 242                tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
 243
 244         switch (info->cpu_type) {
 245         case TYPE_S3C2410:
 246                 mask = (S3C2410_NFCONF_TACLS(3) |
 247                         S3C2410_NFCONF_TWRPH0(7) |
 248                         S3C2410_NFCONF_TWRPH1(7));
 249                 set = S3C2410_NFCONF_EN;
 250                 set |= S3C2410_NFCONF_TACLS(tacls - 1);
 251                 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 252                 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 253                 break;
 254
 255         case TYPE_S3C2440:
 256         case TYPE_S3C2412:
 257                 mask = (S3C2410_NFCONF_TACLS(tacls_max - 1) |
 258                         S3C2410_NFCONF_TWRPH0(7) |
 259                         S3C2410_NFCONF_TWRPH1(7));
 260
 261                 set = S3C2440_NFCONF_TACLS(tacls - 1);
 262                 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 263                 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
 264                 break;
 265
 266         default:
 267                 BUG();
 268         }
 269
 270         local_irq_save(flags);
 271
 272         cfg = readl(info->regs + S3C2410_NFCONF);
 273         cfg &= ~mask;
 274         cfg |= set;
 275         writel(cfg, info->regs + S3C2410_NFCONF);
 276
 277         local_irq_restore(flags);
 278
 279         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
 280
 281         return 0;
 282 }
 283
 284 /**
 285  * s3c2410_nand_inithw - basic hardware initialisation
 286  * @info: The hardware state.
 287  *
 288  * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
 289  * to setup the hardware access speeds and set the controller to be enabled.
 290 */
 291 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
 292 {
 293         int ret;
 294
 295         ret = s3c2410_nand_setrate(info);
 296         if (ret < 0)
 297                 return ret;
 298
 299         switch (info->cpu_type) {
 300         case TYPE_S3C2410:
 301         default:
 302                 break;
 303
 304         case TYPE_S3C2440:
 305         case TYPE_S3C2412:
 306                 /* enable the controller and de-assert nFCE */
 307
 308                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
 309         }
 310
 311         return 0;
 312 }
 313
 314 /**
 315  * s3c2410_nand_select_chip - select the given nand chip
 316  * @mtd: The MTD instance for this chip.
 317  * @chip: The chip number.
 318  *
 319  * This is called by the MTD layer to either select a given chip for the
 320  * @mtd instance, or to indicate that the access has finished and the
 321  * chip can be de-selected.
 322  *
 323  * The routine ensures that the nFCE line is correctly setup, and any
 324  * platform specific selection code is called to route nFCE to the specific
 325  * chip.
 326  */
 327 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
 328 {
 329         struct s3c2410_nand_info *info;
 330         struct s3c2410_nand_mtd *nmtd;
 331         struct nand_chip *this = mtd->priv;
 332         unsigned long cur;
 333
 334         nmtd = this->priv;
 335         info = nmtd->info;
 336
 337         if (chip != -1 && allow_clk_stop(info))
 338                 clk_enable(info->clk);
 339
 340         cur = readl(info->sel_reg);
 341
 342         if (chip == -1) {
 343                 cur |= info->sel_bit;
 344         } else {
 345                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 346                         dev_err(info->device, "invalid chip %d\n", chip);
 347                         return;
 348                 }
 349
 350                 if (info->platform != NULL) {
 351                         if (info->platform->select_chip != NULL)
 352                                 (info->platform->select_chip) (nmtd->set, chip);
 353                 }
 354
 355                 cur &= ~info->sel_bit;
 356         }
 357
 358         writel(cur, info->sel_reg);
 359
 360         if (chip == -1 && allow_clk_stop(info))
 361                 clk_disable(info->clk);
 362 }
 363
 364 /* s3c2410_nand_hwcontrol
 365  *
 366  * Issue command and address cycles to the chip
 367 */
 368
 369 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 370                                    unsigned int ctrl)
 371 {
 372         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 373
 374         if (cmd == NAND_CMD_NONE)
 375                 return;
 376
 377         if (ctrl & NAND_CLE)
 378                 writeb(cmd, info->regs + S3C2410_NFCMD);
 379         else
 380                 writeb(cmd, info->regs + S3C2410_NFADDR);
 381 }
 382
 383 /* command and control functions */
 384
 385 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 386                                    unsigned int ctrl)
 387 {
 388         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 389
 390         if (cmd == NAND_CMD_NONE)
 391                 return;
 392
 393         if (ctrl & NAND_CLE)
 394                 writeb(cmd, info->regs + S3C2440_NFCMD);
 395         else
 396                 writeb(cmd, info->regs + S3C2440_NFADDR);
 397 }
 398
 399 /* s3c2410_nand_devready()
 400  *
 401  * returns 0 if the nand is busy, 1 if it is ready
 402 */
 403
 404 static int s3c2410_nand_devready(struct mtd_info *mtd)
 405 {
 406         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 407         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 408 }
 409
 410 static int s3c2440_nand_devready(struct mtd_info *mtd)
 411 {
 412         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 413         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 414 }
 415
 416 static int s3c2412_nand_devready(struct mtd_info *mtd)
 417 {
 418         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 419         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
 420 }
 421
 422 /* ECC handling functions */
 423
 424 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 425                                      u_char *read_ecc, u_char *calc_ecc)
 426 {
 427         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 428         unsigned int diff0, diff1, diff2;
 429         unsigned int bit, byte;
 430
 431         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
 432
 433         diff0 = read_ecc[0] ^ calc_ecc[0];
 434         diff1 = read_ecc[1] ^ calc_ecc[1];
 435         diff2 = read_ecc[2] ^ calc_ecc[2];
 436
 437         pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
 438                  __func__,
 439                  read_ecc[0], read_ecc[1], read_ecc[2],
 440                  calc_ecc[0], calc_ecc[1], calc_ecc[2],
 441                  diff0, diff1, diff2);
 442
 443         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
 444                 return 0;               /* ECC is ok */
 445
 446         /* sometimes people do not think about using the ECC, so check
 447          * to see if we have an 0xff,0xff,0xff read ECC and then ignore
 448          * the error, on the assumption that this is an un-eccd page.
 449          */
 450         if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
 451             && info->platform->ignore_unset_ecc)
 452                 return 0;
 453
 454         /* Can we correct this ECC (ie, one row and column change).
 455          * Note, this is similar to the 256 error code on smartmedia */
 456
 457         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
 458             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
 459             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
 460                 /* calculate the bit position of the error */
 461
 462                 bit  = ((diff2 >> 3) & 1) |
 463                        ((diff2 >> 4) & 2) |
 464                        ((diff2 >> 5) & 4);
 465
 466                 /* calculate the byte position of the error */
 467
 468                 byte = ((diff2 << 7) & 0x100) |
 469                        ((diff1 << 0) & 0x80)  |
 470                        ((diff1 << 1) & 0x40)  |
 471                        ((diff1 << 2) & 0x20)  |
 472                        ((diff1 << 3) & 0x10)  |
 473                        ((diff0 >> 4) & 0x08)  |
 474                        ((diff0 >> 3) & 0x04)  |
 475                        ((diff0 >> 2) & 0x02)  |
 476                        ((diff0 >> 1) & 0x01);
 477
 478                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
 479                         bit, byte);
 480
 481                 dat[byte] ^= (1 << bit);
 482                 return 1;
 483         }
 484
 485         /* if there is only one bit difference in the ECC, then
 486          * one of only a row or column parity has changed, which
 487          * means the error is most probably in the ECC itself */
 488
 489         diff0 |= (diff1 << 8);
 490         diff0 |= (diff2 << 16);
 491
 492         if ((diff0 & ~(1<<fls(diff0))) == 0)
 493                 return 1;
 494
 495         return -1;
 496 }
 497
 498 /* ECC functions
 499  *
 500  * These allow the s3c2410 and s3c2440 to use the controller's ECC
 501  * generator block to ECC the data as it passes through]
 502 */
 503
 504 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 505 {
 506         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 507         unsigned long ctrl;
 508
 509         ctrl = readl(info->regs + S3C2410_NFCONF);
 510         ctrl |= S3C2410_NFCONF_INITECC;
 511         writel(ctrl, info->regs + S3C2410_NFCONF);
 512 }
 513
 514 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 515 {
 516         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 517         unsigned long ctrl;
 518
 519         ctrl = readl(info->regs + S3C2440_NFCONT);
 520         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
 521 }
 522
 523 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 524 {
 525         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 526         unsigned long ctrl;
 527
 528         ctrl = readl(info->regs + S3C2440_NFCONT);
 529         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 530 }
 531
 532 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 533 {
 534         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 535
 536         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 537         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 538         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 539
 540         pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
 541                  ecc_code[0], ecc_code[1], ecc_code[2]);
 542
 543         return 0;
 544 }
 545
 546 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 547 {
 548         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 549         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
 550
 551         ecc_code[0] = ecc;
 552         ecc_code[1] = ecc >> 8;
 553         ecc_code[2] = ecc >> 16;
 554
 555         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
 556
 557         return 0;
 558 }
 559
 560 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 561 {
 562         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 563         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 564
 565         ecc_code[0] = ecc;
 566         ecc_code[1] = ecc >> 8;
 567         ecc_code[2] = ecc >> 16;
 568
 569         pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
 570
 571         return 0;
 572 }
 573
 574 /* over-ride the standard functions for a little more speed. We can
 575  * use read/write block to move the data buffers to/from the controller
 576 */
 577
 578 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 579 {
 580         struct nand_chip *this = mtd->priv;
 581         readsb(this->IO_ADDR_R, buf, len);
 582 }
 583
 584 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 585 {
 586         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 587
 588         readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 589
 590         /* cleanup if we've got less than a word to do */
 591         if (len & 3) {
 592                 buf += len & ~3;
 593
 594                 for (; len & 3; len--)
 595                         *buf++ = readb(info->regs + S3C2440_NFDATA);
 596         }
 597 }
 598
 599 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 600 {
 601         struct nand_chip *this = mtd->priv;
 602         writesb(this->IO_ADDR_W, buf, len);
 603 }
 604
 605 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 606 {
 607         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 608
 609         writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 610
 611         /* cleanup any fractional write */
 612         if (len & 3) {
 613                 buf += len & ~3;
 614
 615                 for (; len & 3; len--, buf++)
 616                         writeb(*buf, info->regs + S3C2440_NFDATA);
 617         }
 618 }
 619
 620 /* cpufreq driver support */
 621
 622 #ifdef CONFIG_CPU_FREQ
 623
 624 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
 625                                           unsigned long val, void *data)
 626 {
 627         struct s3c2410_nand_info *info;
 628         unsigned long newclk;
 629
 630         info = container_of(nb, struct s3c2410_nand_info, freq_transition);
 631         newclk = clk_get_rate(info->clk);
 632
 633         if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
 634             (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
 635                 s3c2410_nand_setrate(info);
 636         }
 637
 638         return 0;
 639 }
 640
 641 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 642 {
 643         info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
 644
 645         return cpufreq_register_notifier(&info->freq_transition,
 646                                          CPUFREQ_TRANSITION_NOTIFIER);
 647 }
 648
 649 static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 650 {
 651         cpufreq_unregister_notifier(&info->freq_transition,
 652                                     CPUFREQ_TRANSITION_NOTIFIER);
 653 }
 654
 655 #else
 656 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 657 {
 658         return 0;
 659 }
 660
 661 static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 662 {
 663 }
 664 #endif
 665
 666 /* device management functions */
 667
 668 static int s3c24xx_nand_remove(struct platform_device *pdev)
 669 {
 670         struct s3c2410_nand_info *info = to_nand_info(pdev);
 671
 672         platform_set_drvdata(pdev, NULL);
 673
 674         if (info == NULL)
 675                 return 0;
 676
 677         s3c2410_nand_cpufreq_deregister(info);
 678
 679         /* Release all our mtds  and their partitions, then go through
 680          * freeing the resources used
 681          */
 682
 683         if (info->mtds != NULL) {
 684                 struct s3c2410_nand_mtd *ptr = info->mtds;
 685                 int mtdno;
 686
 687                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 688                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 689                         nand_release(&ptr->mtd);
 690                 }
 691
 692                 kfree(info->mtds);
 693         }
 694
 695         /* free the common resources */
 696
 697         if (info->clk != NULL && !IS_ERR(info->clk)) {
 698                 if (!allow_clk_stop(info))
 699                         clk_disable(info->clk);
 700                 clk_put(info->clk);
 701         }
 702
 703         if (info->regs != NULL) {
 704                 iounmap(info->regs);
 705                 info->regs = NULL;
 706         }
 707
 708         if (info->area != NULL) {
 709                 release_resource(info->area);
 710                 kfree(info->area);
 711                 info->area = NULL;
 712         }
 713
 714         kfree(info);
 715
 716         return 0;
 717 }
 718
 719 #ifdef CONFIG_MTD_PARTITIONS
 720 const char *part_probes[] = { "cmdlinepart", NULL };
 721 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 722                                       struct s3c2410_nand_mtd *mtd,
 723                                       struct s3c2410_nand_set *set)
 724 {
 725         struct mtd_partition *part_info;
 726         int nr_part = 0;
 727
 728         if (set == NULL)
 729                 return add_mtd_device(&mtd->mtd);
 730
 731         if (set->nr_partitions == 0) {
 732                 mtd->mtd.name = set->name;
 733                 nr_part = parse_mtd_partitions(&mtd->mtd, part_probes,
 734                                                 &part_info, 0);
 735         } else {
 736                 if (set->nr_partitions > 0 && set->partitions != NULL) {
 737                         nr_part = set->nr_partitions;
 738                         part_info = set->partitions;
 739                 }
 740         }
 741
 742         if (nr_part > 0 && part_info)
 743                 return add_mtd_partitions(&mtd->mtd, part_info, nr_part);
 744
 745         return add_mtd_device(&mtd->mtd);
 746 }
 747 #else
 748 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 749                                       struct s3c2410_nand_mtd *mtd,
 750                                       struct s3c2410_nand_set *set)
 751 {
 752         return add_mtd_device(&mtd->mtd);
 753 }
 754 #endif
 755
 756 /**
 757  * s3c2410_nand_init_chip - initialise a single instance of an chip
 758  * @info: The base NAND controller the chip is on.
 759  * @nmtd: The new controller MTD instance to fill in.
 760  * @set: The information passed from the board specific platform data.
 761  *
 762  * Initialise the given @nmtd from the information in @info and @set. This
 763  * readies the structure for use with the MTD layer functions by ensuring
 764  * all pointers are setup and the necessary control routines selected.
 765  */
 766 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 767                                    struct s3c2410_nand_mtd *nmtd,
 768                                    struct s3c2410_nand_set *set)
 769 {
 770         struct nand_chip *chip = &nmtd->chip;
 771         void __iomem *regs = info->regs;
 772
 773         chip->write_buf    = s3c2410_nand_write_buf;
 774         chip->read_buf     = s3c2410_nand_read_buf;
 775         chip->select_chip  = s3c2410_nand_select_chip;
 776         chip->chip_delay   = 50;
 777         chip->priv         = nmtd;
 778         chip->options      = 0;
 779         chip->controller   = &info->controller;
 780
 781         switch (info->cpu_type) {
 782         case TYPE_S3C2410:
 783                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
 784                 info->sel_reg   = regs + S3C2410_NFCONF;
 785                 info->sel_bit   = S3C2410_NFCONF_nFCE;
 786                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
 787                 chip->dev_ready = s3c2410_nand_devready;
 788                 break;
 789
 790         case TYPE_S3C2440:
 791                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 792                 info->sel_reg   = regs + S3C2440_NFCONT;
 793                 info->sel_bit   = S3C2440_NFCONT_nFCE;
 794                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 795                 chip->dev_ready = s3c2440_nand_devready;
 796                 chip->read_buf  = s3c2440_nand_read_buf;
 797                 chip->write_buf = s3c2440_nand_write_buf;
 798                 break;
 799
 800         case TYPE_S3C2412:
 801                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 802                 info->sel_reg   = regs + S3C2440_NFCONT;
 803                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
 804                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 805                 chip->dev_ready = s3c2412_nand_devready;
 806
 807                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
 808                         dev_info(info->device, "System booted from NAND\n");
 809
 810                 break;
 811         }
 812
 813         chip->IO_ADDR_R = chip->IO_ADDR_W;
 814
 815         nmtd->info         = info;
 816         nmtd->mtd.priv     = chip;
 817         nmtd->mtd.owner    = THIS_MODULE;
 818         nmtd->set          = set;
 819
 820         if (hardware_ecc) {
 821                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 822                 chip->ecc.correct   = s3c2410_nand_correct_data;
 823                 chip->ecc.mode      = NAND_ECC_HW;
 824
 825                 switch (info->cpu_type) {
 826                 case TYPE_S3C2410:
 827                         chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
 828                         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 829                         break;
 830
 831                 case TYPE_S3C2412:
 832                         chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
 833                         chip->ecc.calculate = s3c2412_nand_calculate_ecc;
 834                         break;
 835
 836                 case TYPE_S3C2440:
 837                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
 838                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
 839                         break;
 840
 841                 }
 842         } else {
 843                 chip->ecc.mode      = NAND_ECC_SOFT;
 844         }
 845
 846         if (set->ecc_layout != NULL)
 847                 chip->ecc.layout = set->ecc_layout;
 848
 849         if (set->disable_ecc)
 850                 chip->ecc.mode  = NAND_ECC_NONE;
 851
 852         switch (chip->ecc.mode) {
 853         case NAND_ECC_NONE:
 854                 dev_info(info->device, "NAND ECC disabled\n");
 855                 break;
 856         case NAND_ECC_SOFT:
 857                 dev_info(info->device, "NAND soft ECC\n");
 858                 break;
 859         case NAND_ECC_HW:
 860                 dev_info(info->device, "NAND hardware ECC\n");
 861                 break;
 862         default:
 863                 dev_info(info->device, "NAND ECC UNKNOWN\n");
 864                 break;
 865         }
 866
 867         /* If you use u-boot BBT creation code, specifying this flag will
 868          * let the kernel fish out the BBT from the NAND, and also skip the
 869          * full NAND scan that can take 1/2s or so. Little things... */
 870         if (set->flash_bbt)
 871                 chip->options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
 872 }
 873
 874 /**
 875  * s3c2410_nand_update_chip - post probe update
 876  * @info: The controller instance.
 877  * @nmtd: The driver version of the MTD instance.
 878  *
 879  * This routine is called after the chip probe has succesfully completed
 880  * and the relevant per-chip information updated. This call ensure that
 881  * we update the internal state accordingly.
 882  *
 883  * The internal state is currently limited to the ECC state information.
 884 */
 885 static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
 886                                      struct s3c2410_nand_mtd *nmtd)
 887 {
 888         struct nand_chip *chip = &nmtd->chip;
 889
 890         dev_dbg(info->device, "chip %p => page shift %d\n",
 891                 chip, chip->page_shift);
 892
 893         if (chip->ecc.mode != NAND_ECC_HW)
 894                 return;
 895
 896                 /* change the behaviour depending on wether we are using
 897                  * the large or small page nand device */
 898
 899         if (chip->page_shift > 10) {
 900                 chip->ecc.size      = 256;
 901                 chip->ecc.bytes     = 3;
 902         } else {
 903                 chip->ecc.size      = 512;
 904                 chip->ecc.bytes     = 3;
 905                 chip->ecc.layout    = &nand_hw_eccoob;
 906         }
 907 }
 908
 909 /* s3c24xx_nand_probe
 910  *
 911  * called by device layer when it finds a device matching
 912  * one our driver can handled. This code checks to see if
 913  * it can allocate all necessary resources then calls the
 914  * nand layer to look for devices
 915 */
 916 static int s3c24xx_nand_probe(struct platform_device *pdev)
 917 {
 918         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 919         enum s3c_cpu_type cpu_type;
 920         struct s3c2410_nand_info *info;
 921         struct s3c2410_nand_mtd *nmtd;
 922         struct s3c2410_nand_set *sets;
 923         struct resource *res;
 924         int err = 0;
 925         int size;
 926         int nr_sets;
 927         int setno;
 928
 929         cpu_type = platform_get_device_id(pdev)->driver_data;
 930
 931         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
 932
 933         info = kmalloc(sizeof(*info), GFP_KERNEL);
 934         if (info == NULL) {
 935                 dev_err(&pdev->dev, "no memory for flash info\n");
 936                 err = -ENOMEM;
 937                 goto exit_error;
 938         }
 939
 940         memset(info, 0, sizeof(*info));
 941         platform_set_drvdata(pdev, info);
 942
 943         spin_lock_init(&info->controller.lock);
 944         init_waitqueue_head(&info->controller.wq);
 945
 946         /* get the clock source and enable it */
 947
 948         info->clk = clk_get(&pdev->dev, "nand");
 949         if (IS_ERR(info->clk)) {
 950                 dev_err(&pdev->dev, "failed to get clock\n");
 951                 err = -ENOENT;
 952                 goto exit_error;
 953         }
 954
 955         clk_enable(info->clk);
 956
 957         /* allocate and map the resource */
 958
 959         /* currently we assume we have the one resource */
 960         res  = pdev->resource;
 961         size = res->end - res->start + 1;
 962
 963         info->area = request_mem_region(res->start, size, pdev->name);
 964
 965         if (info->area == NULL) {
 966                 dev_err(&pdev->dev, "cannot reserve register region\n");
 967                 err = -ENOENT;
 968                 goto exit_error;
 969         }
 970
 971         info->device     = &pdev->dev;
 972         info->platform   = plat;
 973         info->regs       = ioremap(res->start, size);
 974         info->cpu_type   = cpu_type;
 975
 976         if (info->regs == NULL) {
 977                 dev_err(&pdev->dev, "cannot reserve register region\n");
 978                 err = -EIO;
 979                 goto exit_error;
 980         }
 981
 982         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
 983
 984         /* initialise the hardware */
 985
 986         err = s3c2410_nand_inithw(info);
 987         if (err != 0)
 988                 goto exit_error;
 989
 990         sets = (plat != NULL) ? plat->sets : NULL;
 991         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
 992
 993         info->mtd_count = nr_sets;
 994
 995         /* allocate our information */
 996
 997         size = nr_sets * sizeof(*info->mtds);
 998         info->mtds = kmalloc(size, GFP_KERNEL);
 999         if (info->mtds == NULL) {
1000                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
1001                 err = -ENOMEM;
1002                 goto exit_error;
1003         }
1004
1005         memset(info->mtds, 0, size);
1006
1007         /* initialise all possible chips */
1008
1009         nmtd = info->mtds;
1010
1011         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
1012                 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
1013
1014                 s3c2410_nand_init_chip(info, nmtd, sets);
1015
1016                 nmtd->scan_res = nand_scan_ident(&nmtd->mtd,
1017                                                  (sets) ? sets->nr_chips : 1);
1018
1019                 if (nmtd->scan_res == 0) {
1020                         s3c2410_nand_update_chip(info, nmtd);
1021                         nand_scan_tail(&nmtd->mtd);
1022                         s3c2410_nand_add_partition(info, nmtd, sets);
1023                 }
1024
1025                 if (sets != NULL)
1026                         sets++;
1027         }
1028
1029         err = s3c2410_nand_cpufreq_register(info);
1030         if (err < 0) {
1031                 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1032                 goto exit_error;
1033         }
1034
1035         if (allow_clk_stop(info)) {
1036                 dev_info(&pdev->dev, "clock idle support enabled\n");
1037                 clk_disable(info->clk);
1038         }
1039
1040         pr_debug("initialised ok\n");
1041         return 0;
1042
1043  exit_error:
1044         s3c24xx_nand_remove(pdev);
1045
1046         if (err == 0)
1047                 err = -EINVAL;
1048         return err;
1049 }
1050
1051 /* PM Support */
1052 #ifdef CONFIG_PM
1053
1054 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1055 {
1056         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1057
1058         if (info) {
1059                 info->save_sel = readl(info->sel_reg);
1060
1061                 /* For the moment, we must ensure nFCE is high during
1062                  * the time we are suspended. This really should be
1063                  * handled by suspending the MTDs we are using, but
1064                  * that is currently not the case. */
1065
1066                 writel(info->save_sel | info->sel_bit, info->sel_reg);
1067
1068                 if (!allow_clk_stop(info))
1069                         clk_disable(info->clk);
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int s3c24xx_nand_resume(struct platform_device *dev)
1076 {
1077         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1078         unsigned long sel;
1079
1080         if (info) {
1081                 clk_enable(info->clk);
1082                 s3c2410_nand_inithw(info);
1083
1084                 /* Restore the state of the nFCE line. */
1085
1086                 sel = readl(info->sel_reg);
1087                 sel &= ~info->sel_bit;
1088                 sel |= info->save_sel & info->sel_bit;
1089                 writel(sel, info->sel_reg);
1090
1091                 if (allow_clk_stop(info))
1092                         clk_disable(info->clk);
1093         }
1094
1095         return 0;
1096 }
1097
1098 #else
1099 #define s3c24xx_nand_suspend NULL
1100 #define s3c24xx_nand_resume NULL
1101 #endif
1102
1103 /* driver device registration */
1104
1105 static struct platform_device_id s3c24xx_driver_ids[] = {
1106         {
1107                 .name           = "s3c2410-nand",
1108                 .driver_data    = TYPE_S3C2410,
1109         }, {
1110                 .name           = "s3c2440-nand",
1111                 .driver_data    = TYPE_S3C2440,
1112         }, {
1113                 .name           = "s3c2412-nand",
1114                 .driver_data    = TYPE_S3C2412,
1115         },
1116         { }
1117 };
1118
1119 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1120
1121 static struct platform_driver s3c24xx_nand_driver = {
1122         .probe          = s3c24xx_nand_probe,
1123         .remove         = s3c24xx_nand_remove,
1124         .suspend        = s3c24xx_nand_suspend,
1125         .resume         = s3c24xx_nand_resume,
1126         .id_table       = s3c24xx_driver_ids,
1127         .driver         = {
1128                 .name   = "s3c24xx-nand",
1129                 .owner  = THIS_MODULE,
1130         },
1131 };
1132
1133 static int __init s3c2410_nand_init(void)
1134 {
1135         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
1136
1137         return platform_driver_register(&s3c24xx_nand_driver);
1138 }
1139
1140 static void __exit s3c2410_nand_exit(void)
1141 {
1142         platform_driver_unregister(&s3c24xx_nand_driver);
1143 }
1144
1145 module_init(s3c2410_nand_init);
1146 module_exit(s3c2410_nand_exit);
1147
1148 MODULE_LICENSE("GPL");
1149 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1150 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");