drivers/mtd/nand/raw/zynq_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq NAND Flash Controller Driver
   6  * This driver is based on plat_nand.c and mxc_nand.c drivers
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <asm/io.h>
  12 #include <linux/errno.h>
  13 #include <nand.h>
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/rawnand.h>
  16 #include <linux/mtd/partitions.h>
  17 #include <linux/mtd/nand_ecc.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <dm.h>
  21
  22 /* The NAND flash driver defines */
  23 #define ZYNQ_NAND_CMD_PHASE             1
  24 #define ZYNQ_NAND_DATA_PHASE            2
  25 #define ZYNQ_NAND_ECC_SIZE              512
  26 #define ZYNQ_NAND_SET_OPMODE_8BIT       (0 << 0)
  27 #define ZYNQ_NAND_SET_OPMODE_16BIT      (1 << 0)
  28 #define ZYNQ_NAND_ECC_STATUS            (1 << 6)
  29 #define ZYNQ_MEMC_CLRCR_INT_CLR1        (1 << 4)
  30 #define ZYNQ_MEMC_SR_RAW_INT_ST1        (1 << 6)
  31 #define ZYNQ_MEMC_SR_INT_ST1            (1 << 4)
  32 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK    0xC
  33
  34 /* Flash memory controller operating parameters */
  35 #define ZYNQ_NAND_CLR_CONFIG    ((0x1 << 1)  |  /* Disable interrupt */ \
  36                                 (0x1 << 4)   |  /* Clear interrupt */ \
  37                                 (0x1 << 6))     /* Disable ECC interrupt */
  38
  39 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  40
  41 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  42 #define ZYNQ_NAND_SET_CYCLES    ((0x2 << 20) |  /* t_rr from nand_cycles */ \
  43                                 (0x2 << 17)  |  /* t_ar from nand_cycles */ \
  44                                 (0x1 << 14)  |  /* t_clr from nand_cycles */ \
  45                                 (0x3 << 11)  |  /* t_wp from nand_cycles */ \
  46                                 (0x2 << 8)   |  /* t_rea from nand_cycles */ \
  47                                 (0x5 << 4)   |  /* t_wc from nand_cycles */ \
  48                                 (0x5 << 0))     /* t_rc from nand_cycles */
  49 #endif
  50
  51
  52 #define ZYNQ_NAND_DIRECT_CMD    ((0x4 << 23) |  /* Chip 0 from interface 1 */ \
  53                                 (0x2 << 21))    /* UpdateRegs operation */
  54
  55 #define ZYNQ_NAND_ECC_CONFIG    ((0x1 << 2)  |  /* ECC available on APB */ \
  56                                 (0x1 << 4)   |  /* ECC read at end of page */ \
  57                                 (0x0 << 5))     /* No Jumping */
  58
  59 #define ZYNQ_NAND_ECC_CMD1      ((0x80)      |  /* Write command */ \
  60                                 (0x00 << 8)  |  /* Read command */ \
  61                                 (0x30 << 16) |  /* Read End command */ \
  62                                 (0x1 << 24))    /* Read End command calid */
  63
  64 #define ZYNQ_NAND_ECC_CMD2      ((0x85)      |  /* Write col change cmd */ \
  65                                 (0x05 << 8)  |  /* Read col change cmd */ \
  66                                 (0xE0 << 16) |  /* Read col change end cmd */ \
  67                                 (0x1 << 24))    /* Read col change
  68                                                         end cmd valid */
  69 /* AXI Address definitions */
  70 #define START_CMD_SHIFT                 3
  71 #define END_CMD_SHIFT                   11
  72 #define END_CMD_VALID_SHIFT             20
  73 #define ADDR_CYCLES_SHIFT               21
  74 #define CLEAR_CS_SHIFT                  21
  75 #define ECC_LAST_SHIFT                  10
  76 #define COMMAND_PHASE                   (0 << 19)
  77 #define DATA_PHASE                      (1 << 19)
  78 #define ONDIE_ECC_FEATURE_ADDR          0x90
  79 #define ONDIE_ECC_FEATURE_ENABLE        0x08
  80
  81 #define ZYNQ_NAND_ECC_LAST      (1 << ECC_LAST_SHIFT)   /* Set ECC_Last */
  82 #define ZYNQ_NAND_CLEAR_CS      (1 << CLEAR_CS_SHIFT)   /* Clear chip select */
  83
  84 /* ECC block registers bit position and bit mask */
  85 #define ZYNQ_NAND_ECC_BUSY      (1 << 6)        /* ECC block is busy */
  86 #define ZYNQ_NAND_ECC_MASK      0x00FFFFFF      /* ECC value mask */
  87
  88 #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK    0x0F
  89 #define ZYNQ_NAND_COL_ADDR_CYCL_MASK    0xF0
  90
  91 #define ZYNQ_NAND_MIO_NUM_NAND_8BIT     13
  92 #define ZYNQ_NAND_MIO_NUM_NAND_16BIT    8
  93
  94 enum zynq_nand_bus_width {
  95         NAND_BW_UNKNOWN = -1,
  96         NAND_BW_8BIT,
  97         NAND_BW_16BIT,
  98 };
  99
 100 #ifndef NAND_CMD_LOCK_TIGHT
 101 #define NAND_CMD_LOCK_TIGHT 0x2c
 102 #endif
 103
 104 #ifndef NAND_CMD_LOCK_STATUS
 105 #define NAND_CMD_LOCK_STATUS 0x7a
 106 #endif
 107
 108 /* SMC register set */
 109 struct zynq_nand_smc_regs {
 110         u32 csr;                /* 0x00 */
 111         u32 reserved0[2];
 112         u32 cfr;                /* 0x0C */
 113         u32 dcr;                /* 0x10 */
 114         u32 scr;                /* 0x14 */
 115         u32 sor;                /* 0x18 */
 116         u32 reserved1[249];
 117         u32 esr;                /* 0x400 */
 118         u32 emcr;               /* 0x404 */
 119         u32 emcmd1r;            /* 0x408 */
 120         u32 emcmd2r;            /* 0x40C */
 121         u32 reserved2[2];
 122         u32 eval0r;             /* 0x418 */
 123 };
 124 #define zynq_nand_smc_base      ((struct zynq_nand_smc_regs __iomem *)\
 125                                 ZYNQ_SMC_BASEADDR)
 126
 127 /*
 128  * struct nand_config - Defines the NAND flash driver instance
 129  * @parts:              Pointer to the mtd_partition structure
 130  * @nand_base:          Virtual address of the NAND flash device
 131  * @end_cmd_pending:    End command is pending
 132  * @end_cmd:            End command
 133  */
 134 struct nand_config {
 135         void __iomem    *nand_base;
 136         u8              end_cmd_pending;
 137         u8              end_cmd;
 138 };
 139
 140 struct zynq_nand_info {
 141         struct udevice *dev;
 142         struct nand_chip nand_chip;
 143 };
 144
 145 /*
 146  * struct zynq_nand_command_format - Defines NAND flash command format
 147  * @start_cmd:          First cycle command (Start command)
 148  * @end_cmd:            Second cycle command (Last command)
 149  * @addr_cycles:        Number of address cycles required to send the address
 150  * @end_cmd_valid:      The second cycle command is valid for cmd or data phase
 151  */
 152 struct zynq_nand_command_format {
 153         u8 start_cmd;
 154         u8 end_cmd;
 155         u8 addr_cycles;
 156         u8 end_cmd_valid;
 157 };
 158
 159 /*  The NAND flash operations command format */
 160 static const struct zynq_nand_command_format zynq_nand_commands[] = {
 161         {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
 162         {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
 163         {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
 164         {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
 165         {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
 166         {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
 167         {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
 168         {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
 169         {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
 170         {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
 171         {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
 172         {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
 173         {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
 174         {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
 175         {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
 176         {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
 177         {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
 178         /* Add all the flash commands supported by the flash device */
 179 };
 180
 181 /* Define default oob placement schemes for large and small page devices */
 182 static struct nand_ecclayout nand_oob_16 = {
 183         .eccbytes = 3,
 184         .eccpos = {0, 1, 2},
 185         .oobfree = {
 186                 { .offset = 8, .length = 8 }
 187         }
 188 };
 189
 190 static struct nand_ecclayout nand_oob_64 = {
 191         .eccbytes = 12,
 192         .eccpos = {
 193                    52, 53, 54, 55, 56, 57,
 194                    58, 59, 60, 61, 62, 63},
 195         .oobfree = {
 196                 { .offset = 2, .length = 50 }
 197         }
 198 };
 199
 200 static struct nand_ecclayout ondie_nand_oob_64 = {
 201         .eccbytes = 32,
 202
 203         .eccpos = {
 204                 8, 9, 10, 11, 12, 13, 14, 15,
 205                 24, 25, 26, 27, 28, 29, 30, 31,
 206                 40, 41, 42, 43, 44, 45, 46, 47,
 207                 56, 57, 58, 59, 60, 61, 62, 63
 208         },
 209
 210         .oobfree = {
 211                 { .offset = 4, .length = 4 },
 212                 { .offset = 20, .length = 4 },
 213                 { .offset = 36, .length = 4 },
 214                 { .offset = 52, .length = 4 }
 215         }
 216 };
 217
 218 /* bbt decriptors for chips with on-die ECC and
 219    chips with 64-byte OOB */
 220 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 221 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 222
 223 static struct nand_bbt_descr bbt_main_descr = {
 224         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 225                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 226         .offs = 4,
 227         .len = 4,
 228         .veroffs = 20,
 229         .maxblocks = 4,
 230         .pattern = bbt_pattern
 231 };
 232
 233 static struct nand_bbt_descr bbt_mirror_descr = {
 234         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 235                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 236         .offs = 4,
 237         .len = 4,
 238         .veroffs = 20,
 239         .maxblocks = 4,
 240         .pattern = mirror_pattern
 241 };
 242
 243 /*
 244  * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
 245  *
 246  * returns: status for command completion, -1 for Timeout
 247  */
 248 static int zynq_nand_waitfor_ecc_completion(void)
 249 {
 250         unsigned long timeout;
 251         u32 status;
 252
 253         /* Wait max 10us */
 254         timeout = 10;
 255         status = readl(&zynq_nand_smc_base->esr);
 256         while (status & ZYNQ_NAND_ECC_BUSY) {
 257                 status = readl(&zynq_nand_smc_base->esr);
 258                 if (timeout == 0)
 259                         return -1;
 260                 timeout--;
 261                 udelay(1);
 262         }
 263
 264         return status;
 265 }
 266
 267 /*
 268  * zynq_nand_init_nand_flash - Initialize NAND controller
 269  * @option:     Device property flags
 270  *
 271  * This function initializes the NAND flash interface on the NAND controller.
 272  *
 273  * returns:     0 on success or error value on failure
 274  */
 275 static int zynq_nand_init_nand_flash(int option)
 276 {
 277         u32 status;
 278
 279         /* disable interrupts */
 280         writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
 281 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 282         /* Initialize the NAND interface by setting cycles and operation mode */
 283         writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
 284 #endif
 285         if (option & NAND_BUSWIDTH_16)
 286                 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
 287         else
 288                 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
 289
 290         writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
 291
 292         /* Wait till the ECC operation is complete */
 293         status = zynq_nand_waitfor_ecc_completion();
 294         if (status < 0) {
 295                 printf("%s: Timeout\n", __func__);
 296                 return status;
 297         }
 298
 299         /* Set the command1 and command2 register */
 300         writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
 301         writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
 302
 303         return 0;
 304 }
 305
 306 /*
 307  * zynq_nand_calculate_hwecc - Calculate Hardware ECC
 308  * @mtd:        Pointer to the mtd_info structure
 309  * @data:       Pointer to the page data
 310  * @ecc_code:   Pointer to the ECC buffer where ECC data needs to be stored
 311  *
 312  * This function retrieves the Hardware ECC data from the controller and returns
 313  * ECC data back to the MTD subsystem.
 314  *
 315  * returns:     0 on success or error value on failure
 316  */
 317 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 318                 u8 *ecc_code)
 319 {
 320         u32 ecc_value = 0;
 321         u8 ecc_reg, ecc_byte;
 322         u32 ecc_status;
 323
 324         /* Wait till the ECC operation is complete */
 325         ecc_status = zynq_nand_waitfor_ecc_completion();
 326         if (ecc_status < 0) {
 327                 printf("%s: Timeout\n", __func__);
 328                 return ecc_status;
 329         }
 330
 331         for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
 332                 /* Read ECC value for each block */
 333                 ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
 334
 335                 /* Get the ecc status from ecc read value */
 336                 ecc_status = (ecc_value >> 24) & 0xFF;
 337
 338                 /* ECC value valid */
 339                 if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
 340                         for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
 341                                 /* Copy ECC bytes to MTD buffer */
 342                                 *ecc_code = ecc_value & 0xFF;
 343                                 ecc_value = ecc_value >> 8;
 344                                 ecc_code++;
 345                         }
 346                 } else {
 347                         debug("%s: ecc status failed\n", __func__);
 348                 }
 349         }
 350
 351         return 0;
 352 }
 353
 354 /*
 355  * onehot - onehot function
 356  * @value:      value to check for onehot
 357  *
 358  * This function checks whether a value is onehot or not.
 359  * onehot is if and only if one bit is set.
 360  *
 361  * FIXME: Try to move this in common.h
 362  */
 363 static bool onehot(unsigned short value)
 364 {
 365         bool onehot;
 366
 367         onehot = value && !(value & (value - 1));
 368         return onehot;
 369 }
 370
 371 /*
 372  * zynq_nand_correct_data - ECC correction function
 373  * @mtd:        Pointer to the mtd_info structure
 374  * @buf:        Pointer to the page data
 375  * @read_ecc:   Pointer to the ECC value read from spare data area
 376  * @calc_ecc:   Pointer to the calculated ECC value
 377  *
 378  * This function corrects the ECC single bit errors & detects 2-bit errors.
 379  *
 380  * returns:     0 if no ECC errors found
 381  *              1 if single bit error found and corrected.
 382  *              -1 if multiple ECC errors found.
 383  */
 384 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
 385                         unsigned char *read_ecc, unsigned char *calc_ecc)
 386 {
 387         unsigned char bit_addr;
 388         unsigned int byte_addr;
 389         unsigned short ecc_odd, ecc_even;
 390         unsigned short read_ecc_lower, read_ecc_upper;
 391         unsigned short calc_ecc_lower, calc_ecc_upper;
 392
 393         read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
 394         read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
 395
 396         calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
 397         calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
 398
 399         ecc_odd = read_ecc_lower ^ calc_ecc_lower;
 400         ecc_even = read_ecc_upper ^ calc_ecc_upper;
 401
 402         if ((ecc_odd == 0) && (ecc_even == 0))
 403                 return 0;       /* no error */
 404
 405         if (ecc_odd == (~ecc_even & 0xfff)) {
 406                 /* bits [11:3] of error code is byte offset */
 407                 byte_addr = (ecc_odd >> 3) & 0x1ff;
 408                 /* bits [2:0] of error code is bit offset */
 409                 bit_addr = ecc_odd & 0x7;
 410                 /* Toggling error bit */
 411                 buf[byte_addr] ^= (1 << bit_addr);
 412                 return 1;
 413         }
 414
 415         if (onehot(ecc_odd | ecc_even))
 416                 return 1; /* one error in parity */
 417
 418         return -1; /* Uncorrectable error */
 419 }
 420
 421 /*
 422  * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
 423  * @mtd:        mtd info structure
 424  * @chip:       nand chip info structure
 425  * @page:       page number to read
 426  * @sndcmd:     flag whether to issue read command or not
 427  */
 428 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 429                         int page)
 430 {
 431         unsigned long data_phase_addr = 0;
 432         int data_width = 4;
 433         u8 *p;
 434
 435         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 436
 437         p = chip->oob_poi;
 438         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 439         p += mtd->oobsize - data_width;
 440
 441         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 442         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 443         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 444         chip->read_buf(mtd, p, data_width);
 445
 446         return 0;
 447 }
 448
 449 /*
 450  * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
 451  * @mtd:        mtd info structure
 452  * @chip:       nand chip info structure
 453  * @page:       page number to write
 454  */
 455 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 456                              int page)
 457 {
 458         int status = 0, data_width = 4;
 459         const u8 *buf = chip->oob_poi;
 460         unsigned long data_phase_addr = 0;
 461
 462         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 463
 464         chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
 465         buf += mtd->oobsize - data_width;
 466
 467         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 468         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 469         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 470         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 471         chip->write_buf(mtd, buf, data_width);
 472
 473         /* Send command to program the OOB data */
 474         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 475         status = chip->waitfunc(mtd, chip);
 476
 477         return status & NAND_STATUS_FAIL ? -EIO : 0;
 478 }
 479
 480 /*
 481  * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
 482  * @mtd:        mtd info structure
 483  * @chip:       nand chip info structure
 484  * @buf:        buffer to store read data
 485  * @oob_required: must write chip->oob_poi to OOB
 486  * @page:       page number to read
 487  */
 488 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 489                                    u8 *buf,  int oob_required, int page)
 490 {
 491         unsigned long data_width = 4;
 492         unsigned long data_phase_addr = 0;
 493         u8 *p;
 494
 495         chip->read_buf(mtd, buf, mtd->writesize);
 496
 497         p = chip->oob_poi;
 498         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 499         p += (mtd->oobsize - data_width);
 500
 501         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 502         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 503         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 504
 505         chip->read_buf(mtd, p, data_width);
 506         return 0;
 507 }
 508
 509 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
 510                 struct nand_chip *chip, u8 *buf, int oob_required, int page)
 511 {
 512         chip->read_buf(mtd, buf, mtd->writesize);
 513         return 0;
 514 }
 515
 516 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
 517                                     struct nand_chip *chip, u32 data_offs,
 518                                     u32 readlen, u8 *buf, int page)
 519 {
 520         if (data_offs != 0) {
 521                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
 522                 buf += data_offs;
 523         }
 524         chip->read_buf(mtd, buf, readlen);
 525
 526         return 0;
 527 }
 528
 529 /*
 530  * zynq_nand_write_page_raw - [Intern] raw page write function
 531  * @mtd:        mtd info structure
 532  * @chip:       nand chip info structure
 533  * @buf:        data buffer
 534  * @oob_required: must write chip->oob_poi to OOB
 535  */
 536 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
 537         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 538 {
 539         unsigned long data_width = 4;
 540         unsigned long data_phase_addr = 0;
 541         u8 *p;
 542
 543         chip->write_buf(mtd, buf, mtd->writesize);
 544
 545         p = chip->oob_poi;
 546         chip->write_buf(mtd, p, (mtd->oobsize - data_width));
 547         p += (mtd->oobsize - data_width);
 548
 549         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 550         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 551         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 552         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 553
 554         chip->write_buf(mtd, p, data_width);
 555
 556         return 0;
 557 }
 558
 559 /*
 560  * nand_write_page_hwecc - Hardware ECC based page write function
 561  * @mtd:        Pointer to the mtd info structure
 562  * @chip:       Pointer to the NAND chip info structure
 563  * @buf:        Pointer to the data buffer
 564  * @oob_required: must write chip->oob_poi to OOB
 565  *
 566  * This functions writes data and hardware generated ECC values in to the page.
 567  */
 568 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
 569         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 570 {
 571         int i, eccsteps, eccsize = chip->ecc.size;
 572         u8 *ecc_calc = chip->buffers->ecccalc;
 573         const u8 *p = buf;
 574         u32 *eccpos = chip->ecc.layout->eccpos;
 575         unsigned long data_phase_addr = 0;
 576         unsigned long data_width = 4;
 577         u8 *oob_ptr;
 578
 579         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 580                 chip->write_buf(mtd, p, eccsize);
 581                 p += eccsize;
 582         }
 583         chip->write_buf(mtd, p, (eccsize - data_width));
 584         p += eccsize - data_width;
 585
 586         /* Set ECC Last bit to 1 */
 587         data_phase_addr = (unsigned long) chip->IO_ADDR_W;
 588         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 589         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 590         chip->write_buf(mtd, p, data_width);
 591
 592         /* Wait for ECC to be calculated and read the error values */
 593         p = buf;
 594         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 595
 596         for (i = 0; i < chip->ecc.total; i++)
 597                 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
 598
 599         /* Clear ECC last bit */
 600         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 601         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 602         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 603
 604         /* Write the spare area with ECC bytes */
 605         oob_ptr = chip->oob_poi;
 606         chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 607
 608         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 609         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 610         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 611         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 612         oob_ptr += (mtd->oobsize - data_width);
 613         chip->write_buf(mtd, oob_ptr, data_width);
 614
 615         return 0;
 616 }
 617
 618 /*
 619  * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
 620  * write function
 621  * @mtd:        mtd info structure
 622  * @chip:       nand chip info structure
 623  * @buf:        data buffer
 624  * @oob_required: must write chip->oob_poi to OOB
 625  */
 626 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
 627         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 628 {
 629         int i, eccsize = chip->ecc.size;
 630         int eccbytes = chip->ecc.bytes;
 631         int eccsteps = chip->ecc.steps;
 632         u8 *ecc_calc = chip->buffers->ecccalc;
 633         const u8 *p = buf;
 634         u32 *eccpos = chip->ecc.layout->eccpos;
 635
 636         /* Software ecc calculation */
 637         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 638                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 639
 640         for (i = 0; i < chip->ecc.total; i++)
 641                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
 642
 643         return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
 644 }
 645
 646 /*
 647  * nand_read_page_hwecc - Hardware ECC based page read function
 648  * @mtd:        Pointer to the mtd info structure
 649  * @chip:       Pointer to the NAND chip info structure
 650  * @buf:        Pointer to the buffer to store read data
 651  * @oob_required: must write chip->oob_poi to OOB
 652  * @page:       page number to read
 653  *
 654  * This functions reads data and checks the data integrity by comparing hardware
 655  * generated ECC values and read ECC values from spare area.
 656  *
 657  * returns:     0 always and updates ECC operation status in to MTD structure
 658  */
 659 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
 660         struct nand_chip *chip, u8 *buf, int oob_required, int page)
 661 {
 662         int i, stat, eccsteps, eccsize = chip->ecc.size;
 663         int eccbytes = chip->ecc.bytes;
 664         u8 *p = buf;
 665         u8 *ecc_calc = chip->buffers->ecccalc;
 666         u8 *ecc_code = chip->buffers->ecccode;
 667         u32 *eccpos = chip->ecc.layout->eccpos;
 668         unsigned long data_phase_addr = 0;
 669         unsigned long data_width = 4;
 670         u8 *oob_ptr;
 671
 672         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 673                 chip->read_buf(mtd, p, eccsize);
 674                 p += eccsize;
 675         }
 676         chip->read_buf(mtd, p, (eccsize - data_width));
 677         p += eccsize - data_width;
 678
 679         /* Set ECC Last bit to 1 */
 680         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 681         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 682         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 683         chip->read_buf(mtd, p, data_width);
 684
 685         /* Read the calculated ECC value */
 686         p = buf;
 687         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 688
 689         /* Clear ECC last bit */
 690         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 691         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 692         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 693
 694         /* Read the stored ECC value */
 695         oob_ptr = chip->oob_poi;
 696         chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 697
 698         /* de-assert chip select */
 699         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 700         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 701         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 702
 703         oob_ptr += (mtd->oobsize - data_width);
 704         chip->read_buf(mtd, oob_ptr, data_width);
 705
 706         for (i = 0; i < chip->ecc.total; i++)
 707                 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
 708
 709         eccsteps = chip->ecc.steps;
 710         p = buf;
 711
 712         /* Check ECC error for all blocks and correct if it is correctable */
 713         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 714                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 715                 if (stat < 0)
 716                         mtd->ecc_stats.failed++;
 717                 else
 718                         mtd->ecc_stats.corrected += stat;
 719         }
 720         return 0;
 721 }
 722
 723 /*
 724  * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
 725  * read function
 726  * @mtd:        mtd info structure
 727  * @chip:       nand chip info structure
 728  * @buf:        buffer to store read data
 729  * @page:       page number to read
 730  */
 731 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
 732         struct nand_chip *chip, u8 *buf, int oob_required,  int page)
 733 {
 734         int i, eccsize = chip->ecc.size;
 735         int eccbytes = chip->ecc.bytes;
 736         int eccsteps = chip->ecc.steps;
 737         u8 *p = buf;
 738         u8 *ecc_calc = chip->buffers->ecccalc;
 739         u8 *ecc_code = chip->buffers->ecccode;
 740         u32 *eccpos = chip->ecc.layout->eccpos;
 741
 742         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 743
 744         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 745                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 746
 747         for (i = 0; i < chip->ecc.total; i++)
 748                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 749
 750         eccsteps = chip->ecc.steps;
 751         p = buf;
 752
 753         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 754                 int stat;
 755
 756                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 757                 if (stat < 0)
 758                         mtd->ecc_stats.failed++;
 759                 else
 760                         mtd->ecc_stats.corrected += stat;
 761         }
 762         return 0;
 763 }
 764
 765 /*
 766  * zynq_nand_select_chip - Select the flash device
 767  * @mtd:        Pointer to the mtd_info structure
 768  * @chip:       Chip number to be selected
 769  *
 770  * This function is empty as the NAND controller handles chip select line
 771  * internally based on the chip address passed in command and data phase.
 772  */
 773 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
 774 {
 775         /* Not support multiple chips yet */
 776 }
 777
 778 /*
 779  * zynq_nand_cmd_function - Send command to NAND device
 780  * @mtd:        Pointer to the mtd_info structure
 781  * @command:    The command to be sent to the flash device
 782  * @column:     The column address for this command, -1 if none
 783  * @page_addr:  The page address for this command, -1 if none
 784  */
 785 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 786                                  int column, int page_addr)
 787 {
 788         struct nand_chip *chip = mtd->priv;
 789         const struct zynq_nand_command_format *curr_cmd = NULL;
 790         u8 addr_cycles = 0;
 791         struct nand_config *xnand = (struct nand_config *)chip->priv;
 792         void *cmd_addr;
 793         unsigned long cmd_data = 0;
 794         unsigned long cmd_phase_addr = 0;
 795         unsigned long data_phase_addr = 0;
 796         u8 end_cmd = 0;
 797         u8 end_cmd_valid = 0;
 798         u32 index;
 799
 800         if (xnand->end_cmd_pending) {
 801                 /* Check for end command if this command request is same as the
 802                  * pending command then return
 803                  */
 804                 if (xnand->end_cmd == command) {
 805                         xnand->end_cmd = 0;
 806                         xnand->end_cmd_pending = 0;
 807                         return;
 808                 }
 809         }
 810
 811         /* Emulate NAND_CMD_READOOB for large page device */
 812         if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
 813             (command == NAND_CMD_READOOB)) {
 814                 column += mtd->writesize;
 815                 command = NAND_CMD_READ0;
 816         }
 817
 818         /* Get the command format */
 819         for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
 820                 if (command == zynq_nand_commands[index].start_cmd)
 821                         break;
 822
 823         if (index == ARRAY_SIZE(zynq_nand_commands)) {
 824                 printf("%s: Unsupported start cmd %02x\n", __func__, command);
 825                 return;
 826         }
 827         curr_cmd = &zynq_nand_commands[index];
 828
 829         /* Clear interrupt */
 830         writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
 831
 832         /* Get the command phase address */
 833         if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
 834                 end_cmd_valid = 1;
 835
 836         if (curr_cmd->end_cmd == NAND_CMD_NONE)
 837                 end_cmd = 0x0;
 838         else
 839                 end_cmd = curr_cmd->end_cmd;
 840
 841         if (command == NAND_CMD_READ0 ||
 842             command == NAND_CMD_SEQIN) {
 843                 addr_cycles = chip->onfi_params.addr_cycles &
 844                                 ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
 845                 addr_cycles += ((chip->onfi_params.addr_cycles &
 846                                 ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
 847         } else {
 848                 addr_cycles = curr_cmd->addr_cycles;
 849         }
 850
 851         cmd_phase_addr = (unsigned long)xnand->nand_base        |
 852                         (addr_cycles << ADDR_CYCLES_SHIFT)      |
 853                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 854                         (COMMAND_PHASE)                                 |
 855                         (end_cmd << END_CMD_SHIFT)                      |
 856                         (curr_cmd->start_cmd << START_CMD_SHIFT);
 857
 858         cmd_addr = (void __iomem *)cmd_phase_addr;
 859
 860         /* Get the data phase address */
 861         end_cmd_valid = 0;
 862
 863         data_phase_addr = (unsigned long)xnand->nand_base       |
 864                         (0x0 << CLEAR_CS_SHIFT)                         |
 865                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 866                         (DATA_PHASE)                                    |
 867                         (end_cmd << END_CMD_SHIFT)                      |
 868                         (0x0 << ECC_LAST_SHIFT);
 869
 870         chip->IO_ADDR_R = (void  __iomem *)data_phase_addr;
 871         chip->IO_ADDR_W = chip->IO_ADDR_R;
 872
 873         /* Command phase AXI Read & Write */
 874         if (column != -1 && page_addr != -1) {
 875                 /* Adjust columns for 16 bit bus width */
 876                 if (chip->options & NAND_BUSWIDTH_16)
 877                         column >>= 1;
 878                 cmd_data = column;
 879                 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
 880                         cmd_data |= page_addr << 16;
 881                         /* Another address cycle for devices > 128MiB */
 882                         if (chip->chipsize > (128 << 20)) {
 883                                 writel(cmd_data, cmd_addr);
 884                                 cmd_data = (page_addr >> 16);
 885                         }
 886                 } else {
 887                         cmd_data |= page_addr << 8;
 888                 }
 889         } else if (page_addr != -1)  { /* Erase */
 890                 cmd_data = page_addr;
 891         } else if (column != -1) { /* Change read/write column, read id etc */
 892                 /* Adjust columns for 16 bit bus width */
 893                 if ((chip->options & NAND_BUSWIDTH_16) &&
 894                     ((command == NAND_CMD_READ0) ||
 895                      (command == NAND_CMD_SEQIN) ||
 896                      (command == NAND_CMD_RNDOUT) ||
 897                      (command == NAND_CMD_RNDIN)))
 898                         column >>= 1;
 899                 cmd_data = column;
 900         }
 901
 902         writel(cmd_data, cmd_addr);
 903
 904         if (curr_cmd->end_cmd_valid) {
 905                 xnand->end_cmd = curr_cmd->end_cmd;
 906                 xnand->end_cmd_pending = 1;
 907         }
 908
 909         ndelay(100);
 910
 911         if ((command == NAND_CMD_READ0) ||
 912             (command == NAND_CMD_RESET) ||
 913             (command == NAND_CMD_PARAM) ||
 914             (command == NAND_CMD_GET_FEATURES))
 915                 /* wait until command is processed */
 916                 nand_wait_ready(mtd);
 917 }
 918
 919 /*
 920  * zynq_nand_read_buf - read chip data into buffer
 921  * @mtd:        MTD device structure
 922  * @buf:        buffer to store date
 923  * @len:        number of bytes to read
 924  */
 925 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 926 {
 927         struct nand_chip *chip = mtd->priv;
 928
 929         /* Make sure that buf is 32 bit aligned */
 930         if (((unsigned long)buf & 0x3) != 0) {
 931                 if (((unsigned long)buf & 0x1) != 0) {
 932                         if (len) {
 933                                 *buf = readb(chip->IO_ADDR_R);
 934                                 buf += 1;
 935                                 len--;
 936                         }
 937                 }
 938
 939                 if (((unsigned long)buf & 0x3) != 0) {
 940                         if (len >= 2) {
 941                                 *(u16 *)buf = readw(chip->IO_ADDR_R);
 942                                 buf += 2;
 943                                 len -= 2;
 944                         }
 945                 }
 946         }
 947
 948         /* copy aligned data */
 949         while (len >= 4) {
 950                 *(u32 *)buf = readl(chip->IO_ADDR_R);
 951                 buf += 4;
 952                 len -= 4;
 953         }
 954
 955         /* mop up any remaining bytes */
 956         if (len) {
 957                 if (len >= 2) {
 958                         *(u16 *)buf = readw(chip->IO_ADDR_R);
 959                         buf += 2;
 960                         len -= 2;
 961                 }
 962                 if (len)
 963                         *buf = readb(chip->IO_ADDR_R);
 964         }
 965 }
 966
 967 /*
 968  * zynq_nand_write_buf - write buffer to chip
 969  * @mtd:        MTD device structure
 970  * @buf:        data buffer
 971  * @len:        number of bytes to write
 972  */
 973 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 974 {
 975         struct nand_chip *chip = mtd->priv;
 976         const u32 *nand = chip->IO_ADDR_W;
 977
 978         /* Make sure that buf is 32 bit aligned */
 979         if (((unsigned long)buf & 0x3) != 0) {
 980                 if (((unsigned long)buf & 0x1) != 0) {
 981                         if (len) {
 982                                 writeb(*buf, nand);
 983                                 buf += 1;
 984                                 len--;
 985                         }
 986                 }
 987
 988                 if (((unsigned long)buf & 0x3) != 0) {
 989                         if (len >= 2) {
 990                                 writew(*(u16 *)buf, nand);
 991                                 buf += 2;
 992                                 len -= 2;
 993                         }
 994                 }
 995         }
 996
 997         /* copy aligned data */
 998         while (len >= 4) {
 999                 writel(*(u32 *)buf, nand);
1000                 buf += 4;
1001                 len -= 4;
1002         }
1003
1004         /* mop up any remaining bytes */
1005         if (len) {
1006                 if (len >= 2) {
1007                         writew(*(u16 *)buf, nand);
1008                         buf += 2;
1009                         len -= 2;
1010                 }
1011
1012                 if (len)
1013                         writeb(*buf, nand);
1014         }
1015 }
1016
1017 /*
1018  * zynq_nand_device_ready - Check device ready/busy line
1019  * @mtd:        Pointer to the mtd_info structure
1020  *
1021  * returns:     0 on busy or 1 on ready state
1022  */
1023 static int zynq_nand_device_ready(struct mtd_info *mtd)
1024 {
1025         u32 csr_val;
1026
1027         csr_val = readl(&zynq_nand_smc_base->csr);
1028         /* Check the raw_int_status1 bit */
1029         if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
1030                 /* Clear the interrupt condition */
1031                 writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
1032                 return 1;
1033         }
1034
1035         return 0;
1036 }
1037
1038 static int zynq_nand_check_is_16bit_bw_flash(void)
1039 {
1040         int is_16bit_bw = NAND_BW_UNKNOWN;
1041         int mio_num_8bit = 0, mio_num_16bit = 0;
1042
1043         mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
1044         if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
1045                 is_16bit_bw = NAND_BW_8BIT;
1046
1047         mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
1048         if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT &&
1049             mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)
1050                 is_16bit_bw = NAND_BW_16BIT;
1051
1052         return is_16bit_bw;
1053 }
1054
1055 static int zynq_nand_probe(struct udevice *dev)
1056 {
1057         struct zynq_nand_info *zynq = dev_get_priv(dev);
1058         struct nand_chip *nand_chip = &zynq->nand_chip;
1059         struct nand_config *xnand;
1060         struct mtd_info *mtd;
1061         unsigned long ecc_page_size;
1062         u8 maf_id, dev_id, i;
1063         u8 get_feature[4];
1064         u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1065         unsigned long ecc_cfg;
1066         int ondie_ecc_enabled = 0;
1067         int err = -1;
1068         int is_16bit_bw;
1069
1070         xnand = calloc(1, sizeof(struct nand_config));
1071         if (!xnand) {
1072                 printf("%s: failed to allocate\n", __func__);
1073                 goto fail;
1074         }
1075
1076         xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
1077         mtd = nand_to_mtd(nand_chip);
1078
1079         nand_chip->priv = xnand;
1080         mtd->priv = nand_chip;
1081
1082         /* Set address of NAND IO lines */
1083         nand_chip->IO_ADDR_R = xnand->nand_base;
1084         nand_chip->IO_ADDR_W = xnand->nand_base;
1085
1086         /* Set the driver entry points for MTD */
1087         nand_chip->cmdfunc = zynq_nand_cmd_function;
1088         nand_chip->dev_ready = zynq_nand_device_ready;
1089         nand_chip->select_chip = zynq_nand_select_chip;
1090
1091         /* If we don't set this delay driver sets 20us by default */
1092         nand_chip->chip_delay = 30;
1093
1094         /* Buffer read/write routines */
1095         nand_chip->read_buf = zynq_nand_read_buf;
1096         nand_chip->write_buf = zynq_nand_write_buf;
1097
1098         is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
1099         if (is_16bit_bw == NAND_BW_UNKNOWN) {
1100                 printf("%s: Unable detect NAND based on MIO settings\n",
1101                        __func__);
1102                 goto fail;
1103         }
1104
1105         if (is_16bit_bw == NAND_BW_16BIT)
1106                 nand_chip->options = NAND_BUSWIDTH_16;
1107
1108         nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1109
1110         /* Initialize the NAND flash interface on NAND controller */
1111         if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
1112                 printf("%s: nand flash init failed\n", __func__);
1113                 goto fail;
1114         }
1115
1116         /* first scan to find the device and get the page size */
1117         if (nand_scan_ident(mtd, 1, NULL)) {
1118                 printf("%s: nand_scan_ident failed\n", __func__);
1119                 goto fail;
1120         }
1121         /* Send the command for reading device ID */
1122         nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1123         nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1124
1125         /* Read manufacturer and device IDs */
1126         maf_id = nand_chip->read_byte(mtd);
1127         dev_id = nand_chip->read_byte(mtd);
1128
1129         if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1130                                  (dev_id == 0xa1) || (dev_id == 0xb1) ||
1131                                  (dev_id == 0xaa) || (dev_id == 0xba) ||
1132                                  (dev_id == 0xda) || (dev_id == 0xca) ||
1133                                  (dev_id == 0xac) || (dev_id == 0xbc) ||
1134                                  (dev_id == 0xdc) || (dev_id == 0xcc) ||
1135                                  (dev_id == 0xa3) || (dev_id == 0xb3) ||
1136                                  (dev_id == 0xd3) || (dev_id == 0xc3))) {
1137                 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1138                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1139                 for (i = 0; i < 4; i++)
1140                         writeb(set_feature[i], nand_chip->IO_ADDR_W);
1141
1142                 /* Wait for 1us after writing data with SET_FEATURES command */
1143                 ndelay(1000);
1144
1145                 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1146                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1147                 nand_chip->read_buf(mtd, get_feature, 4);
1148
1149                 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1150                         debug("%s: OnDie ECC flash\n", __func__);
1151                         ondie_ecc_enabled = 1;
1152                 } else {
1153                         printf("%s: Unable to detect OnDie ECC\n", __func__);
1154                 }
1155         }
1156
1157         if (ondie_ecc_enabled) {
1158                 /* Bypass the controller ECC block */
1159                 ecc_cfg = readl(&zynq_nand_smc_base->emcr);
1160                 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1161                 writel(ecc_cfg, &zynq_nand_smc_base->emcr);
1162
1163                 /* The software ECC routines won't work
1164                  * with the SMC controller
1165                  */
1166                 nand_chip->ecc.mode = NAND_ECC_HW;
1167                 nand_chip->ecc.strength = 1;
1168                 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1169                 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1170                 nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1171                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1172                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1173                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1174                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1175                 nand_chip->ecc.size = mtd->writesize;
1176                 nand_chip->ecc.bytes = 0;
1177
1178                 /* NAND with on-die ECC supports subpage reads */
1179                 nand_chip->options |= NAND_SUBPAGE_READ;
1180
1181                 /* On-Die ECC spare bytes offset 8 is used for ECC codes */
1182                 if (ondie_ecc_enabled) {
1183                         nand_chip->ecc.layout = &ondie_nand_oob_64;
1184                         /* Use the BBT pattern descriptors */
1185                         nand_chip->bbt_td = &bbt_main_descr;
1186                         nand_chip->bbt_md = &bbt_mirror_descr;
1187                 }
1188         } else {
1189                 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1190                 nand_chip->ecc.mode = NAND_ECC_HW;
1191                 nand_chip->ecc.strength = 1;
1192                 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1193                 nand_chip->ecc.bytes = 3;
1194                 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1195                 nand_chip->ecc.correct = zynq_nand_correct_data;
1196                 nand_chip->ecc.hwctl = NULL;
1197                 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1198                 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1199                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1200                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1201                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1202                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1203
1204                 switch (mtd->writesize) {
1205                 case 512:
1206                         ecc_page_size = 0x1;
1207                         /* Set the ECC memory config register */
1208                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1209                                &zynq_nand_smc_base->emcr);
1210                         break;
1211                 case 1024:
1212                         ecc_page_size = 0x2;
1213                         /* Set the ECC memory config register */
1214                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1215                                &zynq_nand_smc_base->emcr);
1216                         break;
1217                 case 2048:
1218                         ecc_page_size = 0x3;
1219                         /* Set the ECC memory config register */
1220                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1221                                &zynq_nand_smc_base->emcr);
1222                         break;
1223                 default:
1224                         nand_chip->ecc.mode = NAND_ECC_SOFT;
1225                         nand_chip->ecc.calculate = nand_calculate_ecc;
1226                         nand_chip->ecc.correct = nand_correct_data;
1227                         nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1228                         nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1229                         nand_chip->ecc.size = 256;
1230                         break;
1231                 }
1232
1233                 if (mtd->oobsize == 16)
1234                         nand_chip->ecc.layout = &nand_oob_16;
1235                 else if (mtd->oobsize == 64)
1236                         nand_chip->ecc.layout = &nand_oob_64;
1237                 else
1238                         printf("%s: No oob layout found\n", __func__);
1239         }
1240
1241         /* Second phase scan */
1242         if (nand_scan_tail(mtd)) {
1243                 printf("%s: nand_scan_tail failed\n", __func__);
1244                 goto fail;
1245         }
1246         if (nand_register(0, mtd))
1247                 goto fail;
1248         return 0;
1249 fail:
1250         free(xnand);
1251         return err;
1252 }
1253
1254 static const struct udevice_id zynq_nand_dt_ids[] = {
1255         {.compatible = "arm,pl353-smc-r2p1",},
1256         { /* sentinel */ }
1257 };
1258
1259 U_BOOT_DRIVER(zynq_nand) = {
1260         .name = "zynq-nand",
1261         .id = UCLASS_MTD,
1262         .of_match = zynq_nand_dt_ids,
1263         .probe = zynq_nand_probe,
1264         .priv_auto_alloc_size = sizeof(struct zynq_nand_info),
1265 };
1266
1267 void board_nand_init(void)
1268 {
1269         struct udevice *dev;
1270         int ret;
1271
1272         ret = uclass_get_device_by_driver(UCLASS_MTD,
1273                                           DM_GET_DRIVER(zynq_nand), &dev);
1274         if (ret && ret != -ENODEV)
1275                 pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
1276 }