drivers/mtd/nand/raw/zynq_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq NAND Flash Controller Driver
   6  * This driver is based on plat_nand.c and mxc_nand.c drivers
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <asm/io.h>
  12 #include <linux/errno.h>
  13 #include <nand.h>
  14 #include <linux/ioport.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/rawnand.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/mtd/nand_ecc.h>
  19 #include <asm/arch/hardware.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <dm.h>
  22
  23 /* The NAND flash driver defines */
  24 #define ZYNQ_NAND_CMD_PHASE             1
  25 #define ZYNQ_NAND_DATA_PHASE            2
  26 #define ZYNQ_NAND_ECC_SIZE              512
  27 #define ZYNQ_NAND_SET_OPMODE_8BIT       (0 << 0)
  28 #define ZYNQ_NAND_SET_OPMODE_16BIT      (1 << 0)
  29 #define ZYNQ_NAND_ECC_STATUS            (1 << 6)
  30 #define ZYNQ_MEMC_CLRCR_INT_CLR1        (1 << 4)
  31 #define ZYNQ_MEMC_SR_RAW_INT_ST1        (1 << 6)
  32 #define ZYNQ_MEMC_SR_INT_ST1            (1 << 4)
  33 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK    0xC
  34
  35 /* Flash memory controller operating parameters */
  36 #define ZYNQ_NAND_CLR_CONFIG    ((0x1 << 1)  |  /* Disable interrupt */ \
  37                                 (0x1 << 4)   |  /* Clear interrupt */ \
  38                                 (0x1 << 6))     /* Disable ECC interrupt */
  39
  40 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  41
  42 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  43 #define ZYNQ_NAND_SET_CYCLES    ((0x2 << 20) |  /* t_rr from nand_cycles */ \
  44                                 (0x2 << 17)  |  /* t_ar from nand_cycles */ \
  45                                 (0x1 << 14)  |  /* t_clr from nand_cycles */ \
  46                                 (0x3 << 11)  |  /* t_wp from nand_cycles */ \
  47                                 (0x2 << 8)   |  /* t_rea from nand_cycles */ \
  48                                 (0x5 << 4)   |  /* t_wc from nand_cycles */ \
  49                                 (0x5 << 0))     /* t_rc from nand_cycles */
  50 #endif
  51
  52
  53 #define ZYNQ_NAND_DIRECT_CMD    ((0x4 << 23) |  /* Chip 0 from interface 1 */ \
  54                                 (0x2 << 21))    /* UpdateRegs operation */
  55
  56 #define ZYNQ_NAND_ECC_CONFIG    ((0x1 << 2)  |  /* ECC available on APB */ \
  57                                 (0x1 << 4)   |  /* ECC read at end of page */ \
  58                                 (0x0 << 5))     /* No Jumping */
  59
  60 #define ZYNQ_NAND_ECC_CMD1      ((0x80)      |  /* Write command */ \
  61                                 (0x00 << 8)  |  /* Read command */ \
  62                                 (0x30 << 16) |  /* Read End command */ \
  63                                 (0x1 << 24))    /* Read End command calid */
  64
  65 #define ZYNQ_NAND_ECC_CMD2      ((0x85)      |  /* Write col change cmd */ \
  66                                 (0x05 << 8)  |  /* Read col change cmd */ \
  67                                 (0xE0 << 16) |  /* Read col change end cmd */ \
  68                                 (0x1 << 24))    /* Read col change
  69                                                         end cmd valid */
  70 /* AXI Address definitions */
  71 #define START_CMD_SHIFT                 3
  72 #define END_CMD_SHIFT                   11
  73 #define END_CMD_VALID_SHIFT             20
  74 #define ADDR_CYCLES_SHIFT               21
  75 #define CLEAR_CS_SHIFT                  21
  76 #define ECC_LAST_SHIFT                  10
  77 #define COMMAND_PHASE                   (0 << 19)
  78 #define DATA_PHASE                      (1 << 19)
  79 #define ONDIE_ECC_FEATURE_ADDR          0x90
  80 #define ONDIE_ECC_FEATURE_ENABLE        0x08
  81
  82 #define ZYNQ_NAND_ECC_LAST      (1 << ECC_LAST_SHIFT)   /* Set ECC_Last */
  83 #define ZYNQ_NAND_CLEAR_CS      (1 << CLEAR_CS_SHIFT)   /* Clear chip select */
  84
  85 /* ECC block registers bit position and bit mask */
  86 #define ZYNQ_NAND_ECC_BUSY      (1 << 6)        /* ECC block is busy */
  87 #define ZYNQ_NAND_ECC_MASK      0x00FFFFFF      /* ECC value mask */
  88
  89 #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK    0x0F
  90 #define ZYNQ_NAND_COL_ADDR_CYCL_MASK    0xF0
  91
  92 #define ZYNQ_NAND_MIO_NUM_NAND_8BIT     13
  93 #define ZYNQ_NAND_MIO_NUM_NAND_16BIT    8
  94
  95 enum zynq_nand_bus_width {
  96         NAND_BW_UNKNOWN = -1,
  97         NAND_BW_8BIT,
  98         NAND_BW_16BIT,
  99 };
 100
 101 #ifndef NAND_CMD_LOCK_TIGHT
 102 #define NAND_CMD_LOCK_TIGHT 0x2c
 103 #endif
 104
 105 #ifndef NAND_CMD_LOCK_STATUS
 106 #define NAND_CMD_LOCK_STATUS 0x7a
 107 #endif
 108
 109 /* SMC register set */
 110 struct zynq_nand_smc_regs {
 111         u32 csr;                /* 0x00 */
 112         u32 reserved0[2];
 113         u32 cfr;                /* 0x0C */
 114         u32 dcr;                /* 0x10 */
 115         u32 scr;                /* 0x14 */
 116         u32 sor;                /* 0x18 */
 117         u32 reserved1[249];
 118         u32 esr;                /* 0x400 */
 119         u32 emcr;               /* 0x404 */
 120         u32 emcmd1r;            /* 0x408 */
 121         u32 emcmd2r;            /* 0x40C */
 122         u32 reserved2[2];
 123         u32 eval0r;             /* 0x418 */
 124 };
 125
 126 /*
 127  * struct nand_config - Defines the NAND flash driver instance
 128  * @parts:              Pointer to the mtd_partition structure
 129  * @nand_base:          Virtual address of the NAND flash device
 130  * @end_cmd_pending:    End command is pending
 131  * @end_cmd:            End command
 132  */
 133 struct nand_config {
 134         void __iomem    *nand_base;
 135         u8              end_cmd_pending;
 136         u8              end_cmd;
 137 };
 138
 139 struct nand_drv {
 140         struct zynq_nand_smc_regs *reg;
 141         struct nand_config config;
 142 };
 143
 144 struct zynq_nand_info {
 145         struct udevice *dev;
 146         struct nand_drv nand_ctrl;
 147         struct nand_chip nand_chip;
 148 };
 149
 150 /*
 151  * struct zynq_nand_command_format - Defines NAND flash command format
 152  * @start_cmd:          First cycle command (Start command)
 153  * @end_cmd:            Second cycle command (Last command)
 154  * @addr_cycles:        Number of address cycles required to send the address
 155  * @end_cmd_valid:      The second cycle command is valid for cmd or data phase
 156  */
 157 struct zynq_nand_command_format {
 158         u8 start_cmd;
 159         u8 end_cmd;
 160         u8 addr_cycles;
 161         u8 end_cmd_valid;
 162 };
 163
 164 /*  The NAND flash operations command format */
 165 static const struct zynq_nand_command_format zynq_nand_commands[] = {
 166         {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
 167         {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
 168         {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
 169         {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
 170         {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
 171         {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
 172         {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
 173         {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
 174         {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
 175         {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
 176         {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
 177         {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
 178         {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
 179         {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
 180         {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
 181         {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
 182         {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
 183         /* Add all the flash commands supported by the flash device */
 184 };
 185
 186 /* Define default oob placement schemes for large and small page devices */
 187 static struct nand_ecclayout nand_oob_16 = {
 188         .eccbytes = 3,
 189         .eccpos = {0, 1, 2},
 190         .oobfree = {
 191                 { .offset = 8, .length = 8 }
 192         }
 193 };
 194
 195 static struct nand_ecclayout nand_oob_64 = {
 196         .eccbytes = 12,
 197         .eccpos = {
 198                    52, 53, 54, 55, 56, 57,
 199                    58, 59, 60, 61, 62, 63},
 200         .oobfree = {
 201                 { .offset = 2, .length = 50 }
 202         }
 203 };
 204
 205 static struct nand_ecclayout ondie_nand_oob_64 = {
 206         .eccbytes = 32,
 207
 208         .eccpos = {
 209                 8, 9, 10, 11, 12, 13, 14, 15,
 210                 24, 25, 26, 27, 28, 29, 30, 31,
 211                 40, 41, 42, 43, 44, 45, 46, 47,
 212                 56, 57, 58, 59, 60, 61, 62, 63
 213         },
 214
 215         .oobfree = {
 216                 { .offset = 4, .length = 4 },
 217                 { .offset = 20, .length = 4 },
 218                 { .offset = 36, .length = 4 },
 219                 { .offset = 52, .length = 4 }
 220         }
 221 };
 222
 223 /* bbt decriptors for chips with on-die ECC and
 224    chips with 64-byte OOB */
 225 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 226 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 227
 228 static struct nand_bbt_descr bbt_main_descr = {
 229         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 230                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 231         .offs = 4,
 232         .len = 4,
 233         .veroffs = 20,
 234         .maxblocks = 4,
 235         .pattern = bbt_pattern
 236 };
 237
 238 static struct nand_bbt_descr bbt_mirror_descr = {
 239         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 240                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 241         .offs = 4,
 242         .len = 4,
 243         .veroffs = 20,
 244         .maxblocks = 4,
 245         .pattern = mirror_pattern
 246 };
 247
 248 /*
 249  * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
 250  *
 251  * returns: status for command completion, -1 for Timeout
 252  */
 253 static int zynq_nand_waitfor_ecc_completion(struct mtd_info *mtd)
 254 {
 255         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 256         struct nand_drv *smc = nand_get_controller_data(nand_chip);
 257         unsigned long timeout;
 258         u32 status;
 259
 260         /* Wait max 10us */
 261         timeout = 10;
 262         status = readl(&smc->reg->esr);
 263         while (status & ZYNQ_NAND_ECC_BUSY) {
 264                 status = readl(&smc->reg->esr);
 265                 if (timeout == 0)
 266                         return -1;
 267                 timeout--;
 268                 udelay(1);
 269         }
 270
 271         return status;
 272 }
 273
 274 /*
 275  * zynq_nand_init_nand_flash - Initialize NAND controller
 276  * @option:     Device property flags
 277  *
 278  * This function initializes the NAND flash interface on the NAND controller.
 279  *
 280  * returns:     0 on success or error value on failure
 281  */
 282 static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option)
 283 {
 284         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 285         struct nand_drv *smc = nand_get_controller_data(nand_chip);
 286         u32 status;
 287
 288         /* disable interrupts */
 289         writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr);
 290 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 291         /* Initialize the NAND interface by setting cycles and operation mode */
 292         writel(ZYNQ_NAND_SET_CYCLES, &smc->reg->scr);
 293 #endif
 294         if (option & NAND_BUSWIDTH_16)
 295                 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &smc->reg->sor);
 296         else
 297                 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &smc->reg->sor);
 298
 299         writel(ZYNQ_NAND_DIRECT_CMD, &smc->reg->dcr);
 300
 301         /* Wait till the ECC operation is complete */
 302         status = zynq_nand_waitfor_ecc_completion(mtd);
 303         if (status < 0) {
 304                 printf("%s: Timeout\n", __func__);
 305                 return status;
 306         }
 307
 308         /* Set the command1 and command2 register */
 309         writel(ZYNQ_NAND_ECC_CMD1, &smc->reg->emcmd1r);
 310         writel(ZYNQ_NAND_ECC_CMD2, &smc->reg->emcmd2r);
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * zynq_nand_calculate_hwecc - Calculate Hardware ECC
 317  * @mtd:        Pointer to the mtd_info structure
 318  * @data:       Pointer to the page data
 319  * @ecc_code:   Pointer to the ECC buffer where ECC data needs to be stored
 320  *
 321  * This function retrieves the Hardware ECC data from the controller and returns
 322  * ECC data back to the MTD subsystem.
 323  *
 324  * returns:     0 on success or error value on failure
 325  */
 326 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 327                 u8 *ecc_code)
 328 {
 329         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 330         struct nand_drv *smc = nand_get_controller_data(nand_chip);
 331         u32 ecc_value = 0;
 332         u8 ecc_reg, ecc_byte;
 333         u32 ecc_status;
 334
 335         /* Wait till the ECC operation is complete */
 336         ecc_status = zynq_nand_waitfor_ecc_completion(mtd);
 337         if (ecc_status < 0) {
 338                 printf("%s: Timeout\n", __func__);
 339                 return ecc_status;
 340         }
 341
 342         for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
 343                 /* Read ECC value for each block */
 344                 ecc_value = readl(&smc->reg->eval0r + ecc_reg);
 345
 346                 /* Get the ecc status from ecc read value */
 347                 ecc_status = (ecc_value >> 24) & 0xFF;
 348
 349                 /* ECC value valid */
 350                 if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
 351                         for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
 352                                 /* Copy ECC bytes to MTD buffer */
 353                                 *ecc_code = ecc_value & 0xFF;
 354                                 ecc_value = ecc_value >> 8;
 355                                 ecc_code++;
 356                         }
 357                 } else {
 358                         debug("%s: ecc status failed\n", __func__);
 359                 }
 360         }
 361
 362         return 0;
 363 }
 364
 365 /*
 366  * onehot - onehot function
 367  * @value:      value to check for onehot
 368  *
 369  * This function checks whether a value is onehot or not.
 370  * onehot is if and only if one bit is set.
 371  *
 372  * FIXME: Try to move this in common.h
 373  */
 374 static bool onehot(unsigned short value)
 375 {
 376         bool onehot;
 377
 378         onehot = value && !(value & (value - 1));
 379         return onehot;
 380 }
 381
 382 /*
 383  * zynq_nand_correct_data - ECC correction function
 384  * @mtd:        Pointer to the mtd_info structure
 385  * @buf:        Pointer to the page data
 386  * @read_ecc:   Pointer to the ECC value read from spare data area
 387  * @calc_ecc:   Pointer to the calculated ECC value
 388  *
 389  * This function corrects the ECC single bit errors & detects 2-bit errors.
 390  *
 391  * returns:     0 if no ECC errors found
 392  *              1 if single bit error found and corrected.
 393  *              -1 if multiple ECC errors found.
 394  */
 395 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
 396                         unsigned char *read_ecc, unsigned char *calc_ecc)
 397 {
 398         unsigned char bit_addr;
 399         unsigned int byte_addr;
 400         unsigned short ecc_odd, ecc_even;
 401         unsigned short read_ecc_lower, read_ecc_upper;
 402         unsigned short calc_ecc_lower, calc_ecc_upper;
 403
 404         read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
 405         read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
 406
 407         calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
 408         calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
 409
 410         ecc_odd = read_ecc_lower ^ calc_ecc_lower;
 411         ecc_even = read_ecc_upper ^ calc_ecc_upper;
 412
 413         if ((ecc_odd == 0) && (ecc_even == 0))
 414                 return 0;       /* no error */
 415
 416         if (ecc_odd == (~ecc_even & 0xfff)) {
 417                 /* bits [11:3] of error code is byte offset */
 418                 byte_addr = (ecc_odd >> 3) & 0x1ff;
 419                 /* bits [2:0] of error code is bit offset */
 420                 bit_addr = ecc_odd & 0x7;
 421                 /* Toggling error bit */
 422                 buf[byte_addr] ^= (1 << bit_addr);
 423                 return 1;
 424         }
 425
 426         if (onehot(ecc_odd | ecc_even))
 427                 return 1; /* one error in parity */
 428
 429         return -1; /* Uncorrectable error */
 430 }
 431
 432 /*
 433  * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
 434  * @mtd:        mtd info structure
 435  * @chip:       nand chip info structure
 436  * @page:       page number to read
 437  * @sndcmd:     flag whether to issue read command or not
 438  */
 439 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 440                         int page)
 441 {
 442         unsigned long data_phase_addr = 0;
 443         int data_width = 4;
 444         u8 *p;
 445
 446         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 447
 448         p = chip->oob_poi;
 449         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 450         p += mtd->oobsize - data_width;
 451
 452         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 453         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 454         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 455         chip->read_buf(mtd, p, data_width);
 456
 457         return 0;
 458 }
 459
 460 /*
 461  * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
 462  * @mtd:        mtd info structure
 463  * @chip:       nand chip info structure
 464  * @page:       page number to write
 465  */
 466 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 467                              int page)
 468 {
 469         int status = 0, data_width = 4;
 470         const u8 *buf = chip->oob_poi;
 471         unsigned long data_phase_addr = 0;
 472
 473         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 474
 475         chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
 476         buf += mtd->oobsize - data_width;
 477
 478         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 479         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 480         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 481         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 482         chip->write_buf(mtd, buf, data_width);
 483
 484         /* Send command to program the OOB data */
 485         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 486         status = chip->waitfunc(mtd, chip);
 487
 488         return status & NAND_STATUS_FAIL ? -EIO : 0;
 489 }
 490
 491 /*
 492  * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
 493  * @mtd:        mtd info structure
 494  * @chip:       nand chip info structure
 495  * @buf:        buffer to store read data
 496  * @oob_required: must write chip->oob_poi to OOB
 497  * @page:       page number to read
 498  */
 499 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 500                                    u8 *buf,  int oob_required, int page)
 501 {
 502         unsigned long data_width = 4;
 503         unsigned long data_phase_addr = 0;
 504         u8 *p;
 505
 506         chip->read_buf(mtd, buf, mtd->writesize);
 507
 508         p = chip->oob_poi;
 509         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 510         p += (mtd->oobsize - data_width);
 511
 512         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 513         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 514         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 515
 516         chip->read_buf(mtd, p, data_width);
 517         return 0;
 518 }
 519
 520 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
 521                 struct nand_chip *chip, u8 *buf, int oob_required, int page)
 522 {
 523         chip->read_buf(mtd, buf, mtd->writesize);
 524         return 0;
 525 }
 526
 527 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
 528                                     struct nand_chip *chip, u32 data_offs,
 529                                     u32 readlen, u8 *buf, int page)
 530 {
 531         if (data_offs != 0) {
 532                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
 533                 buf += data_offs;
 534         }
 535         chip->read_buf(mtd, buf, readlen);
 536
 537         return 0;
 538 }
 539
 540 /*
 541  * zynq_nand_write_page_raw - [Intern] raw page write function
 542  * @mtd:        mtd info structure
 543  * @chip:       nand chip info structure
 544  * @buf:        data buffer
 545  * @oob_required: must write chip->oob_poi to OOB
 546  */
 547 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
 548         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 549 {
 550         unsigned long data_width = 4;
 551         unsigned long data_phase_addr = 0;
 552         u8 *p;
 553
 554         chip->write_buf(mtd, buf, mtd->writesize);
 555
 556         p = chip->oob_poi;
 557         chip->write_buf(mtd, p, (mtd->oobsize - data_width));
 558         p += (mtd->oobsize - data_width);
 559
 560         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 561         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 562         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 563         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 564
 565         chip->write_buf(mtd, p, data_width);
 566
 567         return 0;
 568 }
 569
 570 /*
 571  * nand_write_page_hwecc - Hardware ECC based page write function
 572  * @mtd:        Pointer to the mtd info structure
 573  * @chip:       Pointer to the NAND chip info structure
 574  * @buf:        Pointer to the data buffer
 575  * @oob_required: must write chip->oob_poi to OOB
 576  *
 577  * This functions writes data and hardware generated ECC values in to the page.
 578  */
 579 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
 580         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 581 {
 582         int i, eccsteps, eccsize = chip->ecc.size;
 583         u8 *ecc_calc = chip->buffers->ecccalc;
 584         const u8 *p = buf;
 585         u32 *eccpos = chip->ecc.layout->eccpos;
 586         unsigned long data_phase_addr = 0;
 587         unsigned long data_width = 4;
 588         u8 *oob_ptr;
 589
 590         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 591                 chip->write_buf(mtd, p, eccsize);
 592                 p += eccsize;
 593         }
 594         chip->write_buf(mtd, p, (eccsize - data_width));
 595         p += eccsize - data_width;
 596
 597         /* Set ECC Last bit to 1 */
 598         data_phase_addr = (unsigned long) chip->IO_ADDR_W;
 599         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 600         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 601         chip->write_buf(mtd, p, data_width);
 602
 603         /* Wait for ECC to be calculated and read the error values */
 604         p = buf;
 605         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 606
 607         for (i = 0; i < chip->ecc.total; i++)
 608                 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
 609
 610         /* Clear ECC last bit */
 611         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 612         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 613         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 614
 615         /* Write the spare area with ECC bytes */
 616         oob_ptr = chip->oob_poi;
 617         chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 618
 619         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 620         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 621         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 622         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 623         oob_ptr += (mtd->oobsize - data_width);
 624         chip->write_buf(mtd, oob_ptr, data_width);
 625
 626         return 0;
 627 }
 628
 629 /*
 630  * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
 631  * write function
 632  * @mtd:        mtd info structure
 633  * @chip:       nand chip info structure
 634  * @buf:        data buffer
 635  * @oob_required: must write chip->oob_poi to OOB
 636  */
 637 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
 638         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 639 {
 640         int i, eccsize = chip->ecc.size;
 641         int eccbytes = chip->ecc.bytes;
 642         int eccsteps = chip->ecc.steps;
 643         u8 *ecc_calc = chip->buffers->ecccalc;
 644         const u8 *p = buf;
 645         u32 *eccpos = chip->ecc.layout->eccpos;
 646
 647         /* Software ecc calculation */
 648         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 649                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 650
 651         for (i = 0; i < chip->ecc.total; i++)
 652                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
 653
 654         return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
 655 }
 656
 657 /*
 658  * nand_read_page_hwecc - Hardware ECC based page read function
 659  * @mtd:        Pointer to the mtd info structure
 660  * @chip:       Pointer to the NAND chip info structure
 661  * @buf:        Pointer to the buffer to store read data
 662  * @oob_required: must write chip->oob_poi to OOB
 663  * @page:       page number to read
 664  *
 665  * This functions reads data and checks the data integrity by comparing hardware
 666  * generated ECC values and read ECC values from spare area.
 667  *
 668  * returns:     0 always and updates ECC operation status in to MTD structure
 669  */
 670 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
 671         struct nand_chip *chip, u8 *buf, int oob_required, int page)
 672 {
 673         int i, stat, eccsteps, eccsize = chip->ecc.size;
 674         int eccbytes = chip->ecc.bytes;
 675         u8 *p = buf;
 676         u8 *ecc_calc = chip->buffers->ecccalc;
 677         u8 *ecc_code = chip->buffers->ecccode;
 678         u32 *eccpos = chip->ecc.layout->eccpos;
 679         unsigned long data_phase_addr = 0;
 680         unsigned long data_width = 4;
 681         u8 *oob_ptr;
 682
 683         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 684                 chip->read_buf(mtd, p, eccsize);
 685                 p += eccsize;
 686         }
 687         chip->read_buf(mtd, p, (eccsize - data_width));
 688         p += eccsize - data_width;
 689
 690         /* Set ECC Last bit to 1 */
 691         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 692         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 693         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 694         chip->read_buf(mtd, p, data_width);
 695
 696         /* Read the calculated ECC value */
 697         p = buf;
 698         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 699
 700         /* Clear ECC last bit */
 701         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 702         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 703         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 704
 705         /* Read the stored ECC value */
 706         oob_ptr = chip->oob_poi;
 707         chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 708
 709         /* de-assert chip select */
 710         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 711         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 712         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 713
 714         oob_ptr += (mtd->oobsize - data_width);
 715         chip->read_buf(mtd, oob_ptr, data_width);
 716
 717         for (i = 0; i < chip->ecc.total; i++)
 718                 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
 719
 720         eccsteps = chip->ecc.steps;
 721         p = buf;
 722
 723         /* Check ECC error for all blocks and correct if it is correctable */
 724         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 725                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 726                 if (stat < 0)
 727                         mtd->ecc_stats.failed++;
 728                 else
 729                         mtd->ecc_stats.corrected += stat;
 730         }
 731         return 0;
 732 }
 733
 734 /*
 735  * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
 736  * read function
 737  * @mtd:        mtd info structure
 738  * @chip:       nand chip info structure
 739  * @buf:        buffer to store read data
 740  * @page:       page number to read
 741  */
 742 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
 743         struct nand_chip *chip, u8 *buf, int oob_required,  int page)
 744 {
 745         int i, eccsize = chip->ecc.size;
 746         int eccbytes = chip->ecc.bytes;
 747         int eccsteps = chip->ecc.steps;
 748         u8 *p = buf;
 749         u8 *ecc_calc = chip->buffers->ecccalc;
 750         u8 *ecc_code = chip->buffers->ecccode;
 751         u32 *eccpos = chip->ecc.layout->eccpos;
 752
 753         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 754
 755         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 756                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 757
 758         for (i = 0; i < chip->ecc.total; i++)
 759                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 760
 761         eccsteps = chip->ecc.steps;
 762         p = buf;
 763
 764         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 765                 int stat;
 766
 767                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 768                 if (stat < 0)
 769                         mtd->ecc_stats.failed++;
 770                 else
 771                         mtd->ecc_stats.corrected += stat;
 772         }
 773         return 0;
 774 }
 775
 776 /*
 777  * zynq_nand_select_chip - Select the flash device
 778  * @mtd:        Pointer to the mtd_info structure
 779  * @chip:       Chip number to be selected
 780  *
 781  * This function is empty as the NAND controller handles chip select line
 782  * internally based on the chip address passed in command and data phase.
 783  */
 784 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
 785 {
 786         /* Not support multiple chips yet */
 787 }
 788
 789 /*
 790  * zynq_nand_cmd_function - Send command to NAND device
 791  * @mtd:        Pointer to the mtd_info structure
 792  * @command:    The command to be sent to the flash device
 793  * @column:     The column address for this command, -1 if none
 794  * @page_addr:  The page address for this command, -1 if none
 795  */
 796 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 797                                  int column, int page_addr)
 798 {
 799         struct nand_chip *chip = mtd_to_nand(mtd);
 800         struct nand_drv *smc = nand_get_controller_data(chip);
 801         const struct zynq_nand_command_format *curr_cmd = NULL;
 802         u8 addr_cycles = 0;
 803         struct nand_config *xnand = &smc->config;
 804         void *cmd_addr;
 805         unsigned long cmd_data = 0;
 806         unsigned long cmd_phase_addr = 0;
 807         unsigned long data_phase_addr = 0;
 808         u8 end_cmd = 0;
 809         u8 end_cmd_valid = 0;
 810         u32 index;
 811
 812         if (xnand->end_cmd_pending) {
 813                 /* Check for end command if this command request is same as the
 814                  * pending command then return
 815                  */
 816                 if (xnand->end_cmd == command) {
 817                         xnand->end_cmd = 0;
 818                         xnand->end_cmd_pending = 0;
 819                         return;
 820                 }
 821         }
 822
 823         /* Emulate NAND_CMD_READOOB for large page device */
 824         if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
 825             (command == NAND_CMD_READOOB)) {
 826                 column += mtd->writesize;
 827                 command = NAND_CMD_READ0;
 828         }
 829
 830         /* Get the command format */
 831         for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
 832                 if (command == zynq_nand_commands[index].start_cmd)
 833                         break;
 834
 835         if (index == ARRAY_SIZE(zynq_nand_commands)) {
 836                 printf("%s: Unsupported start cmd %02x\n", __func__, command);
 837                 return;
 838         }
 839         curr_cmd = &zynq_nand_commands[index];
 840
 841         /* Clear interrupt */
 842         writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &smc->reg->cfr);
 843
 844         /* Get the command phase address */
 845         if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
 846                 end_cmd_valid = 1;
 847
 848         if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE)
 849                 end_cmd = 0x0;
 850         else
 851                 end_cmd = curr_cmd->end_cmd;
 852
 853         if (command == NAND_CMD_READ0 ||
 854             command == NAND_CMD_SEQIN) {
 855                 addr_cycles = chip->onfi_params.addr_cycles &
 856                                 ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
 857                 addr_cycles += ((chip->onfi_params.addr_cycles &
 858                                 ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
 859         } else {
 860                 addr_cycles = curr_cmd->addr_cycles;
 861         }
 862
 863         cmd_phase_addr = (unsigned long)xnand->nand_base        |
 864                         (addr_cycles << ADDR_CYCLES_SHIFT)      |
 865                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 866                         (COMMAND_PHASE)                                 |
 867                         (end_cmd << END_CMD_SHIFT)                      |
 868                         (curr_cmd->start_cmd << START_CMD_SHIFT);
 869
 870         cmd_addr = (void __iomem *)cmd_phase_addr;
 871
 872         /* Get the data phase address */
 873         end_cmd_valid = 0;
 874
 875         data_phase_addr = (unsigned long)xnand->nand_base       |
 876                         (0x0 << CLEAR_CS_SHIFT)                         |
 877                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 878                         (DATA_PHASE)                                    |
 879                         (end_cmd << END_CMD_SHIFT)                      |
 880                         (0x0 << ECC_LAST_SHIFT);
 881
 882         chip->IO_ADDR_R = (void  __iomem *)data_phase_addr;
 883         chip->IO_ADDR_W = chip->IO_ADDR_R;
 884
 885         /* Command phase AXI Read & Write */
 886         if (column != -1 && page_addr != -1) {
 887                 /* Adjust columns for 16 bit bus width */
 888                 if (chip->options & NAND_BUSWIDTH_16)
 889                         column >>= 1;
 890                 cmd_data = column;
 891                 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
 892                         cmd_data |= page_addr << 16;
 893                         /* Another address cycle for devices > 128MiB */
 894                         if (chip->chipsize > (128 << 20)) {
 895                                 writel(cmd_data, cmd_addr);
 896                                 cmd_data = (page_addr >> 16);
 897                         }
 898                 } else {
 899                         cmd_data |= page_addr << 8;
 900                 }
 901         } else if (page_addr != -1)  { /* Erase */
 902                 cmd_data = page_addr;
 903         } else if (column != -1) { /* Change read/write column, read id etc */
 904                 /* Adjust columns for 16 bit bus width */
 905                 if ((chip->options & NAND_BUSWIDTH_16) &&
 906                     ((command == NAND_CMD_READ0) ||
 907                      (command == NAND_CMD_SEQIN) ||
 908                      (command == NAND_CMD_RNDOUT) ||
 909                      (command == NAND_CMD_RNDIN)))
 910                         column >>= 1;
 911                 cmd_data = column;
 912         }
 913
 914         writel(cmd_data, cmd_addr);
 915
 916         if (curr_cmd->end_cmd_valid) {
 917                 xnand->end_cmd = curr_cmd->end_cmd;
 918                 xnand->end_cmd_pending = 1;
 919         }
 920
 921         ndelay(100);
 922
 923         if ((command == NAND_CMD_READ0) ||
 924             (command == NAND_CMD_RESET) ||
 925             (command == NAND_CMD_PARAM) ||
 926             (command == NAND_CMD_GET_FEATURES))
 927                 /* wait until command is processed */
 928                 nand_wait_ready(mtd);
 929 }
 930
 931 /*
 932  * zynq_nand_read_buf - read chip data into buffer
 933  * @mtd:        MTD device structure
 934  * @buf:        buffer to store date
 935  * @len:        number of bytes to read
 936  */
 937 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 938 {
 939         struct nand_chip *chip = mtd_to_nand(mtd);
 940
 941         /* Make sure that buf is 32 bit aligned */
 942         if (((unsigned long)buf & 0x3) != 0) {
 943                 if (((unsigned long)buf & 0x1) != 0) {
 944                         if (len) {
 945                                 *buf = readb(chip->IO_ADDR_R);
 946                                 buf += 1;
 947                                 len--;
 948                         }
 949                 }
 950
 951                 if (((unsigned long)buf & 0x3) != 0) {
 952                         if (len >= 2) {
 953                                 *(u16 *)buf = readw(chip->IO_ADDR_R);
 954                                 buf += 2;
 955                                 len -= 2;
 956                         }
 957                 }
 958         }
 959
 960         /* copy aligned data */
 961         while (len >= 4) {
 962                 *(u32 *)buf = readl(chip->IO_ADDR_R);
 963                 buf += 4;
 964                 len -= 4;
 965         }
 966
 967         /* mop up any remaining bytes */
 968         if (len) {
 969                 if (len >= 2) {
 970                         *(u16 *)buf = readw(chip->IO_ADDR_R);
 971                         buf += 2;
 972                         len -= 2;
 973                 }
 974                 if (len)
 975                         *buf = readb(chip->IO_ADDR_R);
 976         }
 977 }
 978
 979 /*
 980  * zynq_nand_write_buf - write buffer to chip
 981  * @mtd:        MTD device structure
 982  * @buf:        data buffer
 983  * @len:        number of bytes to write
 984  */
 985 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 986 {
 987         struct nand_chip *chip = mtd_to_nand(mtd);
 988         const u32 *nand = chip->IO_ADDR_W;
 989
 990         /* Make sure that buf is 32 bit aligned */
 991         if (((unsigned long)buf & 0x3) != 0) {
 992                 if (((unsigned long)buf & 0x1) != 0) {
 993                         if (len) {
 994                                 writeb(*buf, nand);
 995                                 buf += 1;
 996                                 len--;
 997                         }
 998                 }
 999
1000                 if (((unsigned long)buf & 0x3) != 0) {
1001                         if (len >= 2) {
1002                                 writew(*(u16 *)buf, nand);
1003                                 buf += 2;
1004                                 len -= 2;
1005                         }
1006                 }
1007         }
1008
1009         /* copy aligned data */
1010         while (len >= 4) {
1011                 writel(*(u32 *)buf, nand);
1012                 buf += 4;
1013                 len -= 4;
1014         }
1015
1016         /* mop up any remaining bytes */
1017         if (len) {
1018                 if (len >= 2) {
1019                         writew(*(u16 *)buf, nand);
1020                         buf += 2;
1021                         len -= 2;
1022                 }
1023
1024                 if (len)
1025                         writeb(*buf, nand);
1026         }
1027 }
1028
1029 /*
1030  * zynq_nand_device_ready - Check device ready/busy line
1031  * @mtd:        Pointer to the mtd_info structure
1032  *
1033  * returns:     0 on busy or 1 on ready state
1034  */
1035 static int zynq_nand_device_ready(struct mtd_info *mtd)
1036 {
1037         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1038         struct nand_drv *smc = nand_get_controller_data(nand_chip);
1039         u32 csr_val;
1040
1041         csr_val = readl(&smc->reg->csr);
1042         /* Check the raw_int_status1 bit */
1043         if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
1044                 /* Clear the interrupt condition */
1045                 writel(ZYNQ_MEMC_SR_INT_ST1, &smc->reg->cfr);
1046                 return 1;
1047         }
1048
1049         return 0;
1050 }
1051
1052 static int zynq_nand_check_is_16bit_bw_flash(void)
1053 {
1054         int is_16bit_bw = NAND_BW_UNKNOWN;
1055         int mio_num_8bit = 0, mio_num_16bit = 0;
1056
1057         mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
1058         if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
1059                 is_16bit_bw = NAND_BW_8BIT;
1060
1061         mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
1062         if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT &&
1063             mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)
1064                 is_16bit_bw = NAND_BW_16BIT;
1065
1066         return is_16bit_bw;
1067 }
1068
1069 static int zynq_nand_probe(struct udevice *dev)
1070 {
1071         struct zynq_nand_info *zynq = dev_get_priv(dev);
1072         struct nand_chip *nand_chip = &zynq->nand_chip;
1073         struct nand_drv *smc = &zynq->nand_ctrl;
1074         struct nand_config *xnand = &smc->config;
1075         struct mtd_info *mtd;
1076         struct resource res;
1077         ofnode of_nand;
1078         unsigned long ecc_page_size;
1079         u8 maf_id, dev_id, i;
1080         u8 get_feature[4];
1081         u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1082         unsigned long ecc_cfg;
1083         int ondie_ecc_enabled = 0;
1084         int is_16bit_bw;
1085
1086         smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
1087         of_nand = dev_read_subnode(dev, "flash@e1000000");
1088         if (!ofnode_valid(of_nand)) {
1089                 printf("Failed to find nand node in dt\n");
1090                 return -ENODEV;
1091         }
1092
1093         if (!ofnode_is_available(of_nand)) {
1094                 debug("Nand node in dt disabled\n");
1095                 return dm_scan_fdt_dev(dev);
1096         }
1097
1098         if (ofnode_read_resource(of_nand, 0, &res)) {
1099                 printf("Failed to get nand resource\n");
1100                 return -ENODEV;
1101         }
1102
1103         xnand->nand_base = (void __iomem *)res.start;
1104         mtd = nand_to_mtd(nand_chip);
1105         nand_set_controller_data(nand_chip, &zynq->nand_ctrl);
1106
1107         /* Set address of NAND IO lines */
1108         nand_chip->IO_ADDR_R = xnand->nand_base;
1109         nand_chip->IO_ADDR_W = xnand->nand_base;
1110
1111         /* Set the driver entry points for MTD */
1112         nand_chip->cmdfunc = zynq_nand_cmd_function;
1113         nand_chip->dev_ready = zynq_nand_device_ready;
1114         nand_chip->select_chip = zynq_nand_select_chip;
1115
1116         /* If we don't set this delay driver sets 20us by default */
1117         nand_chip->chip_delay = 30;
1118
1119         /* Buffer read/write routines */
1120         nand_chip->read_buf = zynq_nand_read_buf;
1121         nand_chip->write_buf = zynq_nand_write_buf;
1122
1123         is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
1124         if (is_16bit_bw == NAND_BW_UNKNOWN) {
1125                 printf("%s: Unable detect NAND based on MIO settings\n",
1126                        __func__);
1127                 return -EINVAL;
1128         }
1129
1130         if (is_16bit_bw == NAND_BW_16BIT)
1131                 nand_chip->options = NAND_BUSWIDTH_16;
1132
1133         nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1134
1135         /* Initialize the NAND flash interface on NAND controller */
1136         if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) {
1137                 printf("%s: nand flash init failed\n", __func__);
1138                 return -EINVAL;
1139         }
1140
1141         /* first scan to find the device and get the page size */
1142         if (nand_scan_ident(mtd, 1, NULL)) {
1143                 printf("%s: nand_scan_ident failed\n", __func__);
1144                 return -EINVAL;
1145         }
1146         /* Send the command for reading device ID */
1147         nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1148         nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1149
1150         /* Read manufacturer and device IDs */
1151         maf_id = nand_chip->read_byte(mtd);
1152         dev_id = nand_chip->read_byte(mtd);
1153
1154         if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1155                                  (dev_id == 0xa1) || (dev_id == 0xb1) ||
1156                                  (dev_id == 0xaa) || (dev_id == 0xba) ||
1157                                  (dev_id == 0xda) || (dev_id == 0xca) ||
1158                                  (dev_id == 0xac) || (dev_id == 0xbc) ||
1159                                  (dev_id == 0xdc) || (dev_id == 0xcc) ||
1160                                  (dev_id == 0xa3) || (dev_id == 0xb3) ||
1161                                  (dev_id == 0xd3) || (dev_id == 0xc3))) {
1162                 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1163                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1164                 for (i = 0; i < 4; i++)
1165                         writeb(set_feature[i], nand_chip->IO_ADDR_W);
1166
1167                 /* Wait for 1us after writing data with SET_FEATURES command */
1168                 ndelay(1000);
1169
1170                 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1171                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1172                 nand_chip->read_buf(mtd, get_feature, 4);
1173
1174                 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1175                         debug("%s: OnDie ECC flash\n", __func__);
1176                         ondie_ecc_enabled = 1;
1177                 } else {
1178                         printf("%s: Unable to detect OnDie ECC\n", __func__);
1179                 }
1180         }
1181
1182         if (ondie_ecc_enabled) {
1183                 /* Bypass the controller ECC block */
1184                 ecc_cfg = readl(&smc->reg->emcr);
1185                 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1186                 writel(ecc_cfg, &smc->reg->emcr);
1187
1188                 /* The software ECC routines won't work
1189                  * with the SMC controller
1190                  */
1191                 nand_chip->ecc.mode = NAND_ECC_HW;
1192                 nand_chip->ecc.strength = 1;
1193                 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1194                 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1195                 nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1196                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1197                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1198                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1199                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1200                 nand_chip->ecc.size = mtd->writesize;
1201                 nand_chip->ecc.bytes = 0;
1202
1203                 /* NAND with on-die ECC supports subpage reads */
1204                 nand_chip->options |= NAND_SUBPAGE_READ;
1205
1206                 /* On-Die ECC spare bytes offset 8 is used for ECC codes */
1207                 if (ondie_ecc_enabled) {
1208                         nand_chip->ecc.layout = &ondie_nand_oob_64;
1209                         /* Use the BBT pattern descriptors */
1210                         nand_chip->bbt_td = &bbt_main_descr;
1211                         nand_chip->bbt_md = &bbt_mirror_descr;
1212                 }
1213         } else {
1214                 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1215                 nand_chip->ecc.mode = NAND_ECC_HW;
1216                 nand_chip->ecc.strength = 1;
1217                 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1218                 nand_chip->ecc.bytes = 3;
1219                 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1220                 nand_chip->ecc.correct = zynq_nand_correct_data;
1221                 nand_chip->ecc.hwctl = NULL;
1222                 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1223                 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1224                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1225                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1226                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1227                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1228
1229                 switch (mtd->writesize) {
1230                 case 512:
1231                         ecc_page_size = 0x1;
1232                         /* Set the ECC memory config register */
1233                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1234                                &smc->reg->emcr);
1235                         break;
1236                 case 1024:
1237                         ecc_page_size = 0x2;
1238                         /* Set the ECC memory config register */
1239                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1240                                &smc->reg->emcr);
1241                         break;
1242                 case 2048:
1243                         ecc_page_size = 0x3;
1244                         /* Set the ECC memory config register */
1245                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1246                                &smc->reg->emcr);
1247                         break;
1248                 default:
1249                         nand_chip->ecc.mode = NAND_ECC_SOFT;
1250                         nand_chip->ecc.calculate = nand_calculate_ecc;
1251                         nand_chip->ecc.correct = nand_correct_data;
1252                         nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1253                         nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1254                         nand_chip->ecc.size = 256;
1255                         break;
1256                 }
1257
1258                 if (mtd->oobsize == 16)
1259                         nand_chip->ecc.layout = &nand_oob_16;
1260                 else if (mtd->oobsize == 64)
1261                         nand_chip->ecc.layout = &nand_oob_64;
1262                 else
1263                         printf("%s: No oob layout found\n", __func__);
1264         }
1265
1266         /* Second phase scan */
1267         if (nand_scan_tail(mtd)) {
1268                 printf("%s: nand_scan_tail failed\n", __func__);
1269                 return -EINVAL;
1270         }
1271         if (nand_register(0, mtd))
1272                 return -EINVAL;
1273
1274         return 0;
1275 }
1276
1277 static const struct udevice_id zynq_nand_dt_ids[] = {
1278         {.compatible = "arm,pl353-smc-r2p1",},
1279         { /* sentinel */ }
1280 };
1281
1282 U_BOOT_DRIVER(zynq_nand) = {
1283         .name = "zynq-nand",
1284         .id = UCLASS_MTD,
1285         .of_match = zynq_nand_dt_ids,
1286         .probe = zynq_nand_probe,
1287         .priv_auto_alloc_size = sizeof(struct zynq_nand_info),
1288 };
1289
1290 void board_nand_init(void)
1291 {
1292         struct udevice *dev;
1293         int ret;
1294
1295         ret = uclass_get_device_by_driver(UCLASS_MTD,
1296                                           DM_GET_DRIVER(zynq_nand), &dev);
1297         if (ret && ret != -ENODEV)
1298                 pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
1299 }