drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2019
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #define LOG_CATEGORY UCLASS_MTD
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <log.h>
  13 #include <nand.h>
  14 #include <reset.h>
  15 #include <dm/device_compat.h>
  16 #include <linux/bitfield.h>
  17 #include <linux/bitops.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/ioport.h>
  22
  23 /* Bad block marker length */
  24 #define FMC2_BBM_LEN                    2
  25
  26 /* ECC step size */
  27 #define FMC2_ECC_STEP_SIZE              512
  28
  29 /* Command delay */
  30 #define FMC2_RB_DELAY_US                30
  31
  32 /* Max chip enable */
  33 #define FMC2_MAX_CE                     2
  34
  35 /* Timings */
  36 #define FMC2_THIZ                       1
  37 #define FMC2_TIO                        8000
  38 #define FMC2_TSYNC                      3000
  39 #define FMC2_PCR_TIMING_MASK            0xf
  40 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  41
  42 /* FMC2 Controller Registers */
  43 #define FMC2_BCR1                       0x0
  44 #define FMC2_PCR                        0x80
  45 #define FMC2_SR                         0x84
  46 #define FMC2_PMEM                       0x88
  47 #define FMC2_PATT                       0x8c
  48 #define FMC2_HECCR                      0x94
  49 #define FMC2_BCHISR                     0x254
  50 #define FMC2_BCHICR                     0x258
  51 #define FMC2_BCHPBR1                    0x260
  52 #define FMC2_BCHPBR2                    0x264
  53 #define FMC2_BCHPBR3                    0x268
  54 #define FMC2_BCHPBR4                    0x26c
  55 #define FMC2_BCHDSR0                    0x27c
  56 #define FMC2_BCHDSR1                    0x280
  57 #define FMC2_BCHDSR2                    0x284
  58 #define FMC2_BCHDSR3                    0x288
  59 #define FMC2_BCHDSR4                    0x28c
  60
  61 /* Register: FMC2_BCR1 */
  62 #define FMC2_BCR1_FMC2EN                BIT(31)
  63
  64 /* Register: FMC2_PCR */
  65 #define FMC2_PCR_PWAITEN                BIT(1)
  66 #define FMC2_PCR_PBKEN                  BIT(2)
  67 #define FMC2_PCR_PWID                   GENMASK(5, 4)
  68 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  69 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  70 #define FMC2_PCR_ECCEN                  BIT(6)
  71 #define FMC2_PCR_ECCALG                 BIT(8)
  72 #define FMC2_PCR_TCLR                   GENMASK(12, 9)
  73 #define FMC2_PCR_TCLR_DEFAULT           0xf
  74 #define FMC2_PCR_TAR                    GENMASK(16, 13)
  75 #define FMC2_PCR_TAR_DEFAULT            0xf
  76 #define FMC2_PCR_ECCSS                  GENMASK(19, 17)
  77 #define FMC2_PCR_ECCSS_512              1
  78 #define FMC2_PCR_ECCSS_2048             3
  79 #define FMC2_PCR_BCHECC                 BIT(24)
  80 #define FMC2_PCR_WEN                    BIT(25)
  81
  82 /* Register: FMC2_SR */
  83 #define FMC2_SR_NWRF                    BIT(6)
  84
  85 /* Register: FMC2_PMEM */
  86 #define FMC2_PMEM_MEMSET                GENMASK(7, 0)
  87 #define FMC2_PMEM_MEMWAIT               GENMASK(15, 8)
  88 #define FMC2_PMEM_MEMHOLD               GENMASK(23, 16)
  89 #define FMC2_PMEM_MEMHIZ                GENMASK(31, 24)
  90 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
  91
  92 /* Register: FMC2_PATT */
  93 #define FMC2_PATT_ATTSET                GENMASK(7, 0)
  94 #define FMC2_PATT_ATTWAIT               GENMASK(15, 8)
  95 #define FMC2_PATT_ATTHOLD               GENMASK(23, 16)
  96 #define FMC2_PATT_ATTHIZ                GENMASK(31, 24)
  97 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
  98
  99 /* Register: FMC2_BCHISR */
 100 #define FMC2_BCHISR_DERF                BIT(1)
 101 #define FMC2_BCHISR_EPBRF               BIT(4)
 102
 103 /* Register: FMC2_BCHICR */
 104 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 105
 106 /* Register: FMC2_BCHDSR0 */
 107 #define FMC2_BCHDSR0_DUE                BIT(0)
 108 #define FMC2_BCHDSR0_DEF                BIT(1)
 109 #define FMC2_BCHDSR0_DEN                GENMASK(7, 4)
 110
 111 /* Register: FMC2_BCHDSR1 */
 112 #define FMC2_BCHDSR1_EBP1               GENMASK(12, 0)
 113 #define FMC2_BCHDSR1_EBP2               GENMASK(28, 16)
 114
 115 /* Register: FMC2_BCHDSR2 */
 116 #define FMC2_BCHDSR2_EBP3               GENMASK(12, 0)
 117 #define FMC2_BCHDSR2_EBP4               GENMASK(28, 16)
 118
 119 /* Register: FMC2_BCHDSR3 */
 120 #define FMC2_BCHDSR3_EBP5               GENMASK(12, 0)
 121 #define FMC2_BCHDSR3_EBP6               GENMASK(28, 16)
 122
 123 /* Register: FMC2_BCHDSR4 */
 124 #define FMC2_BCHDSR4_EBP7               GENMASK(12, 0)
 125 #define FMC2_BCHDSR4_EBP8               GENMASK(28, 16)
 126
 127 #define FMC2_NSEC_PER_SEC               1000000000L
 128
 129 #define FMC2_TIMEOUT_5S                 5000000
 130
 131 enum stm32_fmc2_ecc {
 132         FMC2_ECC_HAM = 1,
 133         FMC2_ECC_BCH4 = 4,
 134         FMC2_ECC_BCH8 = 8
 135 };
 136
 137 struct stm32_fmc2_timings {
 138         u8 tclr;
 139         u8 tar;
 140         u8 thiz;
 141         u8 twait;
 142         u8 thold_mem;
 143         u8 tset_mem;
 144         u8 thold_att;
 145         u8 tset_att;
 146 };
 147
 148 struct stm32_fmc2_nand {
 149         struct nand_chip chip;
 150         struct stm32_fmc2_timings timings;
 151         int ncs;
 152         int cs_used[FMC2_MAX_CE];
 153 };
 154
 155 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 156 {
 157         return container_of(chip, struct stm32_fmc2_nand, chip);
 158 }
 159
 160 struct stm32_fmc2_nfc {
 161         struct nand_hw_control base;
 162         struct stm32_fmc2_nand nand;
 163         struct nand_ecclayout ecclayout;
 164         fdt_addr_t io_base;
 165         fdt_addr_t data_base[FMC2_MAX_CE];
 166         fdt_addr_t cmd_base[FMC2_MAX_CE];
 167         fdt_addr_t addr_base[FMC2_MAX_CE];
 168         struct clk clk;
 169
 170         u8 cs_assigned;
 171         int cs_sel;
 172 };
 173
 174 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
 175 {
 176         return container_of(base, struct stm32_fmc2_nfc, base);
 177 }
 178
 179 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
 180 {
 181         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 182         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 183         struct stm32_fmc2_timings *timings = &nand->timings;
 184         u32 pmem, patt;
 185
 186         /* Set tclr/tar timings */
 187         clrsetbits_le32(nfc->io_base + FMC2_PCR,
 188                         FMC2_PCR_TCLR | FMC2_PCR_TAR,
 189                         FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
 190                         FIELD_PREP(FMC2_PCR_TAR, timings->tar));
 191
 192         /* Set tset/twait/thold/thiz timings in common bank */
 193         pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
 194         pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
 195         pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
 196         pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
 197         writel(pmem, nfc->io_base + FMC2_PMEM);
 198
 199         /* Set tset/twait/thold/thiz timings in attribut bank */
 200         patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
 201         patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
 202         patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
 203         patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
 204         writel(patt, nfc->io_base + FMC2_PATT);
 205 }
 206
 207 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
 208 {
 209         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 210         u32 pcr = 0, pcr_mask;
 211
 212         /* Configure ECC algorithm (default configuration is Hamming) */
 213         pcr_mask = FMC2_PCR_ECCALG;
 214         pcr_mask |= FMC2_PCR_BCHECC;
 215         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 216                 pcr |= FMC2_PCR_ECCALG;
 217                 pcr |= FMC2_PCR_BCHECC;
 218         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 219                 pcr |= FMC2_PCR_ECCALG;
 220         }
 221
 222         /* Set buswidth */
 223         pcr_mask |= FMC2_PCR_PWID;
 224         if (chip->options & NAND_BUSWIDTH_16)
 225                 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
 226
 227         /* Set ECC sector size */
 228         pcr_mask |= FMC2_PCR_ECCSS;
 229         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
 230
 231         clrsetbits_le32(nfc->io_base + FMC2_PCR, pcr_mask, pcr);
 232 }
 233
 234 static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr)
 235 {
 236         struct nand_chip *chip = mtd_to_nand(mtd);
 237         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 238         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 239
 240         if (chipnr < 0 || chipnr >= nand->ncs)
 241                 return;
 242
 243         if (nand->cs_used[chipnr] == nfc->cs_sel)
 244                 return;
 245
 246         nfc->cs_sel = nand->cs_used[chipnr];
 247         chip->IO_ADDR_R = (void __iomem *)nfc->data_base[nfc->cs_sel];
 248         chip->IO_ADDR_W = (void __iomem *)nfc->data_base[nfc->cs_sel];
 249
 250         stm32_fmc2_nfc_setup(chip);
 251         stm32_fmc2_nfc_timings_init(chip);
 252 }
 253
 254 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc,
 255                                            bool set)
 256 {
 257         u32 pcr;
 258
 259         pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
 260                     FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
 261
 262         clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_PWID, pcr);
 263 }
 264
 265 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
 266 {
 267         clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_ECCEN,
 268                         enable ? FMC2_PCR_ECCEN : 0);
 269 }
 270
 271 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
 272 {
 273         writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
 274 }
 275
 276 static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd,
 277                                     unsigned int ctrl)
 278 {
 279         struct nand_chip *chip = mtd_to_nand(mtd);
 280         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 281
 282         if (cmd == NAND_CMD_NONE)
 283                 return;
 284
 285         if (ctrl & NAND_CLE) {
 286                 writeb(cmd, nfc->cmd_base[nfc->cs_sel]);
 287                 return;
 288         }
 289
 290         writeb(cmd, nfc->addr_base[nfc->cs_sel]);
 291 }
 292
 293 /*
 294  * Enable ECC logic and reset syndrome/parity bits previously calculated
 295  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 296  */
 297 static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode)
 298 {
 299         struct nand_chip *chip = mtd_to_nand(mtd);
 300         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 301
 302         stm32_fmc2_nfc_set_ecc(nfc, false);
 303
 304         if (chip->ecc.strength != FMC2_ECC_HAM) {
 305                 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_WEN,
 306                                 mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
 307
 308                 stm32_fmc2_nfc_clear_bch_irq(nfc);
 309         }
 310
 311         stm32_fmc2_nfc_set_ecc(nfc, true);
 312 }
 313
 314 /*
 315  * ECC Hamming calculation
 316  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 317  * max of 1-bit)
 318  */
 319 static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data,
 320                                         u8 *ecc)
 321 {
 322         struct nand_chip *chip = mtd_to_nand(mtd);
 323         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 324         u32 heccr, sr;
 325         int ret;
 326
 327         ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
 328                                  sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
 329         if (ret < 0) {
 330                 log_err("Ham timeout\n");
 331                 return ret;
 332         }
 333
 334         heccr = readl(nfc->io_base + FMC2_HECCR);
 335
 336         ecc[0] = heccr;
 337         ecc[1] = heccr >> 8;
 338         ecc[2] = heccr >> 16;
 339
 340         stm32_fmc2_nfc_set_ecc(nfc, false);
 341
 342         return 0;
 343 }
 344
 345 static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat,
 346                                       u8 *read_ecc, u8 *calc_ecc)
 347 {
 348         u8 bit_position = 0, b0, b1, b2;
 349         u32 byte_addr = 0, b;
 350         u32 i, shifting = 1;
 351
 352         /* Indicate which bit and byte is faulty (if any) */
 353         b0 = read_ecc[0] ^ calc_ecc[0];
 354         b1 = read_ecc[1] ^ calc_ecc[1];
 355         b2 = read_ecc[2] ^ calc_ecc[2];
 356         b = b0 | (b1 << 8) | (b2 << 16);
 357
 358         /* No errors */
 359         if (likely(!b))
 360                 return 0;
 361
 362         /* Calculate bit position */
 363         for (i = 0; i < 3; i++) {
 364                 switch (b % 4) {
 365                 case 2:
 366                         bit_position += shifting;
 367                 case 1:
 368                         break;
 369                 default:
 370                         return -EBADMSG;
 371                 }
 372                 shifting <<= 1;
 373                 b >>= 2;
 374         }
 375
 376         /* Calculate byte position */
 377         shifting = 1;
 378         for (i = 0; i < 9; i++) {
 379                 switch (b % 4) {
 380                 case 2:
 381                         byte_addr += shifting;
 382                 case 1:
 383                         break;
 384                 default:
 385                         return -EBADMSG;
 386                 }
 387                 shifting <<= 1;
 388                 b >>= 2;
 389         }
 390
 391         /* Flip the bit */
 392         dat[byte_addr] ^= (1 << bit_position);
 393
 394         return 1;
 395 }
 396
 397 /*
 398  * ECC BCH calculation and correction
 399  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 400  * max of 4-bit/8-bit)
 401  */
 402
 403 static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data,
 404                                         u8 *ecc)
 405 {
 406         struct nand_chip *chip = mtd_to_nand(mtd);
 407         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 408         u32 bchpbr, bchisr;
 409         int ret;
 410
 411         /* Wait until the BCH code is ready */
 412         ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
 413                                  bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
 414         if (ret < 0) {
 415                 log_err("Bch timeout\n");
 416                 return ret;
 417         }
 418
 419         /* Read parity bits */
 420         bchpbr = readl(nfc->io_base + FMC2_BCHPBR1);
 421         ecc[0] = bchpbr;
 422         ecc[1] = bchpbr >> 8;
 423         ecc[2] = bchpbr >> 16;
 424         ecc[3] = bchpbr >> 24;
 425
 426         bchpbr = readl(nfc->io_base + FMC2_BCHPBR2);
 427         ecc[4] = bchpbr;
 428         ecc[5] = bchpbr >> 8;
 429         ecc[6] = bchpbr >> 16;
 430
 431         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 432                 ecc[7] = bchpbr >> 24;
 433
 434                 bchpbr = readl(nfc->io_base + FMC2_BCHPBR3);
 435                 ecc[8] = bchpbr;
 436                 ecc[9] = bchpbr >> 8;
 437                 ecc[10] = bchpbr >> 16;
 438                 ecc[11] = bchpbr >> 24;
 439
 440                 bchpbr = readl(nfc->io_base + FMC2_BCHPBR4);
 441                 ecc[12] = bchpbr;
 442         }
 443
 444         stm32_fmc2_nfc_set_ecc(nfc, false);
 445
 446         return 0;
 447 }
 448
 449 static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat,
 450                                       u8 *read_ecc, u8 *calc_ecc)
 451 {
 452         struct nand_chip *chip = mtd_to_nand(mtd);
 453         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 454         u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
 455         u16 pos[8];
 456         int i, ret, den, eccsize = chip->ecc.size;
 457         unsigned int nb_errs = 0;
 458
 459         /* Wait until the decoding error is ready */
 460         ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
 461                                  bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
 462         if (ret < 0) {
 463                 log_err("Bch timeout\n");
 464                 return ret;
 465         }
 466
 467         bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0);
 468         bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1);
 469         bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2);
 470         bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3);
 471         bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4);
 472
 473         stm32_fmc2_nfc_set_ecc(nfc, false);
 474
 475         /* No errors found */
 476         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 477                 return 0;
 478
 479         /* Too many errors detected */
 480         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 481                 return -EBADMSG;
 482
 483         pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
 484         pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
 485         pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
 486         pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
 487         pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
 488         pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
 489         pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
 490         pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
 491
 492         den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
 493         for (i = 0; i < den; i++) {
 494                 if (pos[i] < eccsize * 8) {
 495                         __change_bit(pos[i], (unsigned long *)dat);
 496                         nb_errs++;
 497                 }
 498         }
 499
 500         return nb_errs;
 501 }
 502
 503 static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd,
 504                                     struct nand_chip *chip, u8 *buf,
 505                                     int oob_required, int page)
 506 {
 507         int i, s, stat, eccsize = chip->ecc.size;
 508         int eccbytes = chip->ecc.bytes;
 509         int eccsteps = chip->ecc.steps;
 510         int eccstrength = chip->ecc.strength;
 511         u8 *p = buf;
 512         u8 *ecc_calc = chip->buffers->ecccalc;
 513         u8 *ecc_code = chip->buffers->ecccode;
 514         unsigned int max_bitflips = 0;
 515
 516         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 517              s++, i += eccbytes, p += eccsize) {
 518                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 519
 520                 /* Read the nand page sector (512 bytes) */
 521                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
 522                 chip->read_buf(mtd, p, eccsize);
 523
 524                 /* Read the corresponding ECC bytes */
 525                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
 526                 chip->read_buf(mtd, ecc_code, eccbytes);
 527
 528                 /* Correct the data */
 529                 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
 530                 if (stat == -EBADMSG)
 531                         /* Check for empty pages with bitflips */
 532                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 533                                                            ecc_code, eccbytes,
 534                                                            NULL, 0,
 535                                                            eccstrength);
 536
 537                 if (stat < 0) {
 538                         mtd->ecc_stats.failed++;
 539                 } else {
 540                         mtd->ecc_stats.corrected += stat;
 541                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 542                 }
 543         }
 544
 545         /* Read oob */
 546         if (oob_required) {
 547                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 548                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 549         }
 550
 551         return max_bitflips;
 552 }
 553
 554 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc, bool has_parent)
 555 {
 556         u32 pcr = readl(nfc->io_base + FMC2_PCR);
 557
 558         /* Set CS used to undefined */
 559         nfc->cs_sel = -1;
 560
 561         /* Enable wait feature and nand flash memory bank */
 562         pcr |= FMC2_PCR_PWAITEN;
 563         pcr |= FMC2_PCR_PBKEN;
 564
 565         /* Set buswidth to 8 bits mode for identification */
 566         pcr &= ~FMC2_PCR_PWID;
 567
 568         /* ECC logic is disabled */
 569         pcr &= ~FMC2_PCR_ECCEN;
 570
 571         /* Default mode */
 572         pcr &= ~FMC2_PCR_ECCALG;
 573         pcr &= ~FMC2_PCR_BCHECC;
 574         pcr &= ~FMC2_PCR_WEN;
 575
 576         /* Set default ECC sector size */
 577         pcr &= ~FMC2_PCR_ECCSS;
 578         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
 579
 580         /* Set default tclr/tar timings */
 581         pcr &= ~FMC2_PCR_TCLR;
 582         pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
 583         pcr &= ~FMC2_PCR_TAR;
 584         pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
 585
 586         /* Enable FMC2 controller */
 587         if (!has_parent)
 588                 setbits_le32(nfc->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
 589
 590         writel(pcr, nfc->io_base + FMC2_PCR);
 591         writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
 592         writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
 593 }
 594
 595 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
 596                                         const struct nand_sdr_timings *sdrt)
 597 {
 598         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 599         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 600         struct stm32_fmc2_timings *tims = &nand->timings;
 601         unsigned long hclk = clk_get_rate(&nfc->clk);
 602         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 603         unsigned long timing, tar, tclr, thiz, twait;
 604         unsigned long tset_mem, tset_att, thold_mem, thold_att;
 605
 606         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
 607         timing = DIV_ROUND_UP(tar, hclkp) - 1;
 608         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 609
 610         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
 611         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
 612         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 613
 614         tims->thiz = FMC2_THIZ;
 615         thiz = (tims->thiz + 1) * hclkp;
 616
 617         /*
 618          * tWAIT > tRP
 619          * tWAIT > tWP
 620          * tWAIT > tREA + tIO
 621          */
 622         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
 623         twait = max_t(unsigned long, twait, sdrt->tWP_min);
 624         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
 625         timing = DIV_ROUND_UP(twait, hclkp);
 626         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 627
 628         /*
 629          * tSETUP_MEM > tCS - tWAIT
 630          * tSETUP_MEM > tALS - tWAIT
 631          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
 632          */
 633         tset_mem = hclkp;
 634         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
 635                 tset_mem = sdrt->tCS_min - twait;
 636         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
 637                 tset_mem = sdrt->tALS_min - twait;
 638         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 639             (tset_mem < sdrt->tDS_min - (twait - thiz)))
 640                 tset_mem = sdrt->tDS_min - (twait - thiz);
 641         timing = DIV_ROUND_UP(tset_mem, hclkp);
 642         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 643
 644         /*
 645          * tHOLD_MEM > tCH
 646          * tHOLD_MEM > tREH - tSETUP_MEM
 647          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
 648          */
 649         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
 650         if (sdrt->tREH_min > tset_mem &&
 651             (thold_mem < sdrt->tREH_min - tset_mem))
 652                 thold_mem = sdrt->tREH_min - tset_mem;
 653         if ((sdrt->tRC_min > tset_mem + twait) &&
 654             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
 655                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
 656         if ((sdrt->tWC_min > tset_mem + twait) &&
 657             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
 658                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
 659         timing = DIV_ROUND_UP(thold_mem, hclkp);
 660         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 661
 662         /*
 663          * tSETUP_ATT > tCS - tWAIT
 664          * tSETUP_ATT > tCLS - tWAIT
 665          * tSETUP_ATT > tALS - tWAIT
 666          * tSETUP_ATT > tRHW - tHOLD_MEM
 667          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
 668          */
 669         tset_att = hclkp;
 670         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
 671                 tset_att = sdrt->tCS_min - twait;
 672         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
 673                 tset_att = sdrt->tCLS_min - twait;
 674         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
 675                 tset_att = sdrt->tALS_min - twait;
 676         if (sdrt->tRHW_min > thold_mem &&
 677             (tset_att < sdrt->tRHW_min - thold_mem))
 678                 tset_att = sdrt->tRHW_min - thold_mem;
 679         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 680             (tset_att < sdrt->tDS_min - (twait - thiz)))
 681                 tset_att = sdrt->tDS_min - (twait - thiz);
 682         timing = DIV_ROUND_UP(tset_att, hclkp);
 683         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 684
 685         /*
 686          * tHOLD_ATT > tALH
 687          * tHOLD_ATT > tCH
 688          * tHOLD_ATT > tCLH
 689          * tHOLD_ATT > tCOH
 690          * tHOLD_ATT > tDH
 691          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
 692          * tHOLD_ATT > tADL - tSETUP_MEM
 693          * tHOLD_ATT > tWH - tSETUP_MEM
 694          * tHOLD_ATT > tWHR - tSETUP_MEM
 695          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
 696          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
 697          */
 698         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
 699         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
 700         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
 701         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
 702         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
 703         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
 704             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
 705                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
 706         if (sdrt->tADL_min > tset_mem &&
 707             (thold_att < sdrt->tADL_min - tset_mem))
 708                 thold_att = sdrt->tADL_min - tset_mem;
 709         if (sdrt->tWH_min > tset_mem &&
 710             (thold_att < sdrt->tWH_min - tset_mem))
 711                 thold_att = sdrt->tWH_min - tset_mem;
 712         if (sdrt->tWHR_min > tset_mem &&
 713             (thold_att < sdrt->tWHR_min - tset_mem))
 714                 thold_att = sdrt->tWHR_min - tset_mem;
 715         if ((sdrt->tRC_min > tset_att + twait) &&
 716             (thold_att < sdrt->tRC_min - (tset_att + twait)))
 717                 thold_att = sdrt->tRC_min - (tset_att + twait);
 718         if ((sdrt->tWC_min > tset_att + twait) &&
 719             (thold_att < sdrt->tWC_min - (tset_att + twait)))
 720                 thold_att = sdrt->tWC_min - (tset_att + twait);
 721         timing = DIV_ROUND_UP(thold_att, hclkp);
 722         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 723 }
 724
 725 static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr,
 726                                           const struct nand_data_interface *cf)
 727 {
 728         struct nand_chip *chip = mtd_to_nand(mtd);
 729         const struct nand_sdr_timings *sdrt;
 730
 731         sdrt = nand_get_sdr_timings(cf);
 732         if (IS_ERR(sdrt))
 733                 return PTR_ERR(sdrt);
 734
 735         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
 736                 return 0;
 737
 738         stm32_fmc2_nfc_calc_timings(chip, sdrt);
 739         stm32_fmc2_nfc_timings_init(chip);
 740
 741         return 0;
 742 }
 743
 744 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
 745 {
 746         chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
 747
 748         /*
 749          * Specific callbacks to read/write a page depending on
 750          * the algo used (Hamming, BCH).
 751          */
 752         if (chip->ecc.strength == FMC2_ECC_HAM) {
 753                 /* Hamming is used */
 754                 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
 755                 chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
 756                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
 757                 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
 758                 return;
 759         }
 760
 761         /* BCH is used */
 762         chip->ecc.read_page = stm32_fmc2_nfc_read_page;
 763         chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
 764         chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
 765
 766         if (chip->ecc.strength == FMC2_ECC_BCH8)
 767                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
 768         else
 769                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
 770 }
 771
 772 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
 773 {
 774         /* Hamming */
 775         if (strength == FMC2_ECC_HAM)
 776                 return 4;
 777
 778         /* BCH8 */
 779         if (strength == FMC2_ECC_BCH8)
 780                 return 14;
 781
 782         /* BCH4 */
 783         return 8;
 784 }
 785
 786 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
 787                      FMC2_ECC_STEP_SIZE,
 788                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
 789
 790 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node)
 791 {
 792         struct stm32_fmc2_nand *nand = &nfc->nand;
 793         u32 cs[FMC2_MAX_CE];
 794         int ret, i;
 795
 796         if (!ofnode_get_property(node, "reg", &nand->ncs))
 797                 return -EINVAL;
 798
 799         nand->ncs /= sizeof(u32);
 800         if (!nand->ncs) {
 801                 log_err("Invalid reg property size\n");
 802                 return -EINVAL;
 803         }
 804
 805         ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
 806         if (ret < 0) {
 807                 log_err("Could not retrieve reg property\n");
 808                 return -EINVAL;
 809         }
 810
 811         for (i = 0; i < nand->ncs; i++) {
 812                 if (cs[i] >= FMC2_MAX_CE) {
 813                         log_err("Invalid reg value: %d\n", nand->cs_used[i]);
 814                         return -EINVAL;
 815                 }
 816
 817                 if (nfc->cs_assigned & BIT(cs[i])) {
 818                         log_err("Cs already assigned: %d\n", nand->cs_used[i]);
 819                         return -EINVAL;
 820                 }
 821
 822                 nfc->cs_assigned |= BIT(cs[i]);
 823                 nand->cs_used[i] = cs[i];
 824         }
 825
 826         nand->chip.flash_node = ofnode_to_offset(node);
 827
 828         return 0;
 829 }
 830
 831 static int stm32_fmc2_nfc_parse_dt(struct udevice *dev,
 832                                    struct stm32_fmc2_nfc *nfc)
 833 {
 834         ofnode child;
 835         int ret, nchips = 0;
 836
 837         dev_for_each_subnode(child, dev)
 838                 nchips++;
 839
 840         if (!nchips) {
 841                 log_err("NAND chip not defined\n");
 842                 return -EINVAL;
 843         }
 844
 845         if (nchips > 1) {
 846                 log_err("Too many NAND chips defined\n");
 847                 return -EINVAL;
 848         }
 849
 850         dev_for_each_subnode(child, dev) {
 851                 ret = stm32_fmc2_nfc_parse_child(nfc, child);
 852                 if (ret)
 853                         return ret;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static struct udevice *stm32_fmc2_nfc_get_cdev(struct udevice *dev)
 860 {
 861         struct udevice *pdev = dev_get_parent(dev);
 862         struct udevice *cdev = NULL;
 863         bool ebi_found = false;
 864
 865         if (pdev && ofnode_device_is_compatible(dev_ofnode(pdev),
 866                                                 "st,stm32mp1-fmc2-ebi"))
 867                 ebi_found = true;
 868
 869         if (ofnode_device_is_compatible(dev_ofnode(dev),
 870                                         "st,stm32mp1-fmc2-nfc")) {
 871                 if (ebi_found)
 872                         cdev = pdev;
 873
 874                 return cdev;
 875         }
 876
 877         if (!ebi_found)
 878                 cdev = dev;
 879
 880         return cdev;
 881 }
 882
 883 static int stm32_fmc2_nfc_probe(struct udevice *dev)
 884 {
 885         struct stm32_fmc2_nfc *nfc = dev_get_priv(dev);
 886         struct stm32_fmc2_nand *nand = &nfc->nand;
 887         struct nand_chip *chip = &nand->chip;
 888         struct mtd_info *mtd = &chip->mtd;
 889         struct nand_ecclayout *ecclayout;
 890         struct udevice *cdev;
 891         struct reset_ctl reset;
 892         int oob_index, chip_cs, mem_region, ret;
 893         unsigned int i;
 894         int start_region = 0;
 895         fdt_addr_t addr;
 896
 897         spin_lock_init(&nfc->controller.lock);
 898         init_waitqueue_head(&nfc->controller.wq);
 899
 900         cdev = stm32_fmc2_nfc_get_cdev(dev);
 901         if (!cdev)
 902                 return -EINVAL;
 903
 904         ret = stm32_fmc2_nfc_parse_dt(dev, nfc);
 905         if (ret)
 906                 return ret;
 907
 908         nfc->io_base = dev_read_addr(cdev);
 909         if (nfc->io_base == FDT_ADDR_T_NONE)
 910                 return -EINVAL;
 911
 912         if (dev == cdev)
 913                 start_region = 1;
 914
 915         for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
 916              chip_cs++, mem_region += 3) {
 917                 if (!(nfc->cs_assigned & BIT(chip_cs)))
 918                         continue;
 919
 920                 addr = dev_read_addr_index(dev, mem_region);
 921                 if (addr == FDT_ADDR_T_NONE) {
 922                         dev_err(dev, "Resource data_base not found for cs%d", chip_cs);
 923                         return ret;
 924                 }
 925                 nfc->data_base[chip_cs] = addr;
 926
 927                 addr = dev_read_addr_index(dev, mem_region + 1);
 928                 if (addr == FDT_ADDR_T_NONE) {
 929                         dev_err(dev, "Resource cmd_base not found for cs%d", chip_cs);
 930                         return ret;
 931                 }
 932                 nfc->cmd_base[chip_cs] = addr;
 933
 934                 addr = dev_read_addr_index(dev, mem_region + 2);
 935                 if (addr == FDT_ADDR_T_NONE) {
 936                         dev_err(dev, "Resource addr_base not found for cs%d", chip_cs);
 937                         return ret;
 938                 }
 939                 nfc->addr_base[chip_cs] = addr;
 940         }
 941
 942         /* Enable the clock */
 943         ret = clk_get_by_index(cdev, 0, &nfc->clk);
 944         if (ret)
 945                 return ret;
 946
 947         ret = clk_enable(&nfc->clk);
 948         if (ret)
 949                 return ret;
 950
 951         /* Reset */
 952         ret = reset_get_by_index(dev, 0, &reset);
 953         if (!ret) {
 954                 reset_assert(&reset);
 955                 udelay(2);
 956                 reset_deassert(&reset);
 957         }
 958
 959         stm32_fmc2_nfc_init(nfc, dev != cdev);
 960
 961         chip->controller = &nfc->base;
 962         chip->select_chip = stm32_fmc2_nfc_select_chip;
 963         chip->setup_data_interface = stm32_fmc2_nfc_setup_interface;
 964         chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl;
 965         chip->chip_delay = FMC2_RB_DELAY_US;
 966         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
 967                          NAND_USE_BOUNCE_BUFFER;
 968
 969         /* Default ECC settings */
 970         chip->ecc.mode = NAND_ECC_HW;
 971         chip->ecc.size = FMC2_ECC_STEP_SIZE;
 972         chip->ecc.strength = FMC2_ECC_BCH8;
 973
 974         ret = nand_scan_ident(mtd, nand->ncs, NULL);
 975         if (ret)
 976                 return ret;
 977
 978         /*
 979          * Only NAND_ECC_HW mode is actually supported
 980          * Hamming => ecc.strength = 1
 981          * BCH4 => ecc.strength = 4
 982          * BCH8 => ecc.strength = 8
 983          * ECC sector size = 512
 984          */
 985         if (chip->ecc.mode != NAND_ECC_HW) {
 986                 dev_err(dev, "Nand_ecc_mode is not well defined in the DT\n");
 987                 return -EINVAL;
 988         }
 989
 990         ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
 991                                   mtd->oobsize - FMC2_BBM_LEN);
 992         if (ret) {
 993                 dev_err(dev, "No valid ECC settings set\n");
 994                 return ret;
 995         }
 996
 997         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 998                 chip->bbt_options |= NAND_BBT_NO_OOB;
 999
1000         stm32_fmc2_nfc_nand_callbacks_setup(chip);
1001
1002         /* Define ECC layout */
1003         ecclayout = &nfc->ecclayout;
1004         ecclayout->eccbytes = chip->ecc.bytes *
1005                               (mtd->writesize / chip->ecc.size);
1006         oob_index = FMC2_BBM_LEN;
1007         for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1008                 ecclayout->eccpos[i] = oob_index;
1009         ecclayout->oobfree->offset = oob_index;
1010         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1011         chip->ecc.layout = ecclayout;
1012
1013         if (chip->options & NAND_BUSWIDTH_16)
1014                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1015
1016         ret = nand_scan_tail(mtd);
1017         if (ret)
1018                 return ret;
1019
1020         return nand_register(0, mtd);
1021 }
1022
1023 static const struct udevice_id stm32_fmc2_nfc_match[] = {
1024         { .compatible = "st,stm32mp15-fmc2" },
1025         { .compatible = "st,stm32mp1-fmc2-nfc" },
1026         { /* Sentinel */ }
1027 };
1028
1029 U_BOOT_DRIVER(stm32_fmc2_nfc) = {
1030         .name = "stm32_fmc2_nfc",
1031         .id = UCLASS_MTD,
1032         .of_match = stm32_fmc2_nfc_match,
1033         .probe = stm32_fmc2_nfc_probe,
1034         .priv_auto      = sizeof(struct stm32_fmc2_nfc),
1035 };
1036
1037 void board_nand_init(void)
1038 {
1039         struct udevice *dev;
1040         int ret;
1041
1042         ret = uclass_get_device_by_driver(UCLASS_MTD,
1043                                           DM_DRIVER_GET(stm32_fmc2_nfc),
1044                                           &dev);
1045         if (ret && ret != -ENODEV)
1046                 log_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
1047                         ret);
1048 }