drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2019
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <nand.h>
  12 #include <reset.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/ioport.h>
  19
  20 /* Bad block marker length */
  21 #define FMC2_BBM_LEN                    2
  22
  23 /* ECC step size */
  24 #define FMC2_ECC_STEP_SIZE              512
  25
  26 /* Command delay */
  27 #define FMC2_RB_DELAY_US                30
  28
  29 /* Max chip enable */
  30 #define FMC2_MAX_CE                     2
  31
  32 /* Timings */
  33 #define FMC2_THIZ                       1
  34 #define FMC2_TIO                        8000
  35 #define FMC2_TSYNC                      3000
  36 #define FMC2_PCR_TIMING_MASK            0xf
  37 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  38
  39 /* FMC2 Controller Registers */
  40 #define FMC2_BCR1                       0x0
  41 #define FMC2_PCR                        0x80
  42 #define FMC2_SR                         0x84
  43 #define FMC2_PMEM                       0x88
  44 #define FMC2_PATT                       0x8c
  45 #define FMC2_HECCR                      0x94
  46 #define FMC2_BCHISR                     0x254
  47 #define FMC2_BCHICR                     0x258
  48 #define FMC2_BCHPBR1                    0x260
  49 #define FMC2_BCHPBR2                    0x264
  50 #define FMC2_BCHPBR3                    0x268
  51 #define FMC2_BCHPBR4                    0x26c
  52 #define FMC2_BCHDSR0                    0x27c
  53 #define FMC2_BCHDSR1                    0x280
  54 #define FMC2_BCHDSR2                    0x284
  55 #define FMC2_BCHDSR3                    0x288
  56 #define FMC2_BCHDSR4                    0x28c
  57
  58 /* Register: FMC2_BCR1 */
  59 #define FMC2_BCR1_FMC2EN                BIT(31)
  60
  61 /* Register: FMC2_PCR */
  62 #define FMC2_PCR_PWAITEN                BIT(1)
  63 #define FMC2_PCR_PBKEN                  BIT(2)
  64 #define FMC2_PCR_PWID                   GENMASK(5, 4)
  65 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  66 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  67 #define FMC2_PCR_ECCEN                  BIT(6)
  68 #define FMC2_PCR_ECCALG                 BIT(8)
  69 #define FMC2_PCR_TCLR                   GENMASK(12, 9)
  70 #define FMC2_PCR_TCLR_DEFAULT           0xf
  71 #define FMC2_PCR_TAR                    GENMASK(16, 13)
  72 #define FMC2_PCR_TAR_DEFAULT            0xf
  73 #define FMC2_PCR_ECCSS                  GENMASK(19, 17)
  74 #define FMC2_PCR_ECCSS_512              1
  75 #define FMC2_PCR_ECCSS_2048             3
  76 #define FMC2_PCR_BCHECC                 BIT(24)
  77 #define FMC2_PCR_WEN                    BIT(25)
  78
  79 /* Register: FMC2_SR */
  80 #define FMC2_SR_NWRF                    BIT(6)
  81
  82 /* Register: FMC2_PMEM */
  83 #define FMC2_PMEM_MEMSET                GENMASK(7, 0)
  84 #define FMC2_PMEM_MEMWAIT               GENMASK(15, 8)
  85 #define FMC2_PMEM_MEMHOLD               GENMASK(23, 16)
  86 #define FMC2_PMEM_MEMHIZ                GENMASK(31, 24)
  87 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
  88
  89 /* Register: FMC2_PATT */
  90 #define FMC2_PATT_ATTSET                GENMASK(7, 0)
  91 #define FMC2_PATT_ATTWAIT               GENMASK(15, 8)
  92 #define FMC2_PATT_ATTHOLD               GENMASK(23, 16)
  93 #define FMC2_PATT_ATTHIZ                GENMASK(31, 24)
  94 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
  95
  96 /* Register: FMC2_BCHISR */
  97 #define FMC2_BCHISR_DERF                BIT(1)
  98 #define FMC2_BCHISR_EPBRF               BIT(4)
  99
 100 /* Register: FMC2_BCHICR */
 101 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 102
 103 /* Register: FMC2_BCHDSR0 */
 104 #define FMC2_BCHDSR0_DUE                BIT(0)
 105 #define FMC2_BCHDSR0_DEF                BIT(1)
 106 #define FMC2_BCHDSR0_DEN                GENMASK(7, 4)
 107
 108 /* Register: FMC2_BCHDSR1 */
 109 #define FMC2_BCHDSR1_EBP1               GENMASK(12, 0)
 110 #define FMC2_BCHDSR1_EBP2               GENMASK(28, 16)
 111
 112 /* Register: FMC2_BCHDSR2 */
 113 #define FMC2_BCHDSR2_EBP3               GENMASK(12, 0)
 114 #define FMC2_BCHDSR2_EBP4               GENMASK(28, 16)
 115
 116 /* Register: FMC2_BCHDSR3 */
 117 #define FMC2_BCHDSR3_EBP5               GENMASK(12, 0)
 118 #define FMC2_BCHDSR3_EBP6               GENMASK(28, 16)
 119
 120 /* Register: FMC2_BCHDSR4 */
 121 #define FMC2_BCHDSR4_EBP7               GENMASK(12, 0)
 122 #define FMC2_BCHDSR4_EBP8               GENMASK(28, 16)
 123
 124 #define FMC2_NSEC_PER_SEC               1000000000L
 125
 126 #define FMC2_TIMEOUT_5S                 5000000
 127
 128 enum stm32_fmc2_ecc {
 129         FMC2_ECC_HAM = 1,
 130         FMC2_ECC_BCH4 = 4,
 131         FMC2_ECC_BCH8 = 8
 132 };
 133
 134 struct stm32_fmc2_timings {
 135         u8 tclr;
 136         u8 tar;
 137         u8 thiz;
 138         u8 twait;
 139         u8 thold_mem;
 140         u8 tset_mem;
 141         u8 thold_att;
 142         u8 tset_att;
 143 };
 144
 145 struct stm32_fmc2_nand {
 146         struct nand_chip chip;
 147         struct stm32_fmc2_timings timings;
 148         int ncs;
 149         int cs_used[FMC2_MAX_CE];
 150 };
 151
 152 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 153 {
 154         return container_of(chip, struct stm32_fmc2_nand, chip);
 155 }
 156
 157 struct stm32_fmc2_nfc {
 158         struct nand_hw_control base;
 159         struct stm32_fmc2_nand nand;
 160         struct nand_ecclayout ecclayout;
 161         void __iomem *io_base;
 162         void __iomem *data_base[FMC2_MAX_CE];
 163         void __iomem *cmd_base[FMC2_MAX_CE];
 164         void __iomem *addr_base[FMC2_MAX_CE];
 165         struct clk clk;
 166
 167         u8 cs_assigned;
 168         int cs_sel;
 169 };
 170
 171 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
 172 {
 173         return container_of(base, struct stm32_fmc2_nfc, base);
 174 }
 175
 176 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
 177 {
 178         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 179         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 180         struct stm32_fmc2_timings *timings = &nand->timings;
 181         u32 pcr = readl(nfc->io_base + FMC2_PCR);
 182         u32 pmem, patt;
 183
 184         /* Set tclr/tar timings */
 185         pcr &= ~FMC2_PCR_TCLR;
 186         pcr |= FIELD_PREP(FMC2_PCR_TCLR, timings->tclr);
 187         pcr &= ~FMC2_PCR_TAR;
 188         pcr |= FIELD_PREP(FMC2_PCR_TAR, timings->tar);
 189
 190         /* Set tset/twait/thold/thiz timings in common bank */
 191         pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
 192         pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
 193         pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
 194         pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
 195
 196         /* Set tset/twait/thold/thiz timings in attribut bank */
 197         patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
 198         patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
 199         patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
 200         patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
 201
 202         writel(pcr, nfc->io_base + FMC2_PCR);
 203         writel(pmem, nfc->io_base + FMC2_PMEM);
 204         writel(patt, nfc->io_base + FMC2_PATT);
 205 }
 206
 207 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
 208 {
 209         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 210         u32 pcr = readl(nfc->io_base + FMC2_PCR);
 211
 212         /* Configure ECC algorithm (default configuration is Hamming) */
 213         pcr &= ~FMC2_PCR_ECCALG;
 214         pcr &= ~FMC2_PCR_BCHECC;
 215         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 216                 pcr |= FMC2_PCR_ECCALG;
 217                 pcr |= FMC2_PCR_BCHECC;
 218         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 219                 pcr |= FMC2_PCR_ECCALG;
 220         }
 221
 222         /* Set buswidth */
 223         pcr &= ~FMC2_PCR_PWID;
 224         if (chip->options & NAND_BUSWIDTH_16)
 225                 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
 226
 227         /* Set ECC sector size */
 228         pcr &= ~FMC2_PCR_ECCSS;
 229         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
 230
 231         writel(pcr, nfc->io_base + FMC2_PCR);
 232 }
 233
 234 static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr)
 235 {
 236         struct nand_chip *chip = mtd_to_nand(mtd);
 237         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 238         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 239
 240         if (chipnr < 0 || chipnr >= nand->ncs)
 241                 return;
 242
 243         if (nand->cs_used[chipnr] == nfc->cs_sel)
 244                 return;
 245
 246         nfc->cs_sel = nand->cs_used[chipnr];
 247         chip->IO_ADDR_R = nfc->data_base[nfc->cs_sel];
 248         chip->IO_ADDR_W = nfc->data_base[nfc->cs_sel];
 249
 250         stm32_fmc2_nfc_setup(chip);
 251         stm32_fmc2_nfc_timings_init(chip);
 252 }
 253
 254 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc,
 255                                            bool set)
 256 {
 257         u32 pcr = readl(nfc->io_base + FMC2_PCR);
 258
 259         pcr &= ~FMC2_PCR_PWID;
 260         if (set)
 261                 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
 262         writel(pcr, nfc->io_base + FMC2_PCR);
 263 }
 264
 265 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
 266 {
 267         u32 pcr = readl(nfc->io_base + FMC2_PCR);
 268
 269         pcr &= ~FMC2_PCR_ECCEN;
 270         if (enable)
 271                 pcr |= FMC2_PCR_ECCEN;
 272         writel(pcr, nfc->io_base + FMC2_PCR);
 273 }
 274
 275 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
 276 {
 277         writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
 278 }
 279
 280 static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd,
 281                                     unsigned int ctrl)
 282 {
 283         struct nand_chip *chip = mtd_to_nand(mtd);
 284         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 285
 286         if (cmd == NAND_CMD_NONE)
 287                 return;
 288
 289         if (ctrl & NAND_CLE) {
 290                 writeb(cmd, nfc->cmd_base[nfc->cs_sel]);
 291                 return;
 292         }
 293
 294         writeb(cmd, nfc->addr_base[nfc->cs_sel]);
 295 }
 296
 297 /*
 298  * Enable ECC logic and reset syndrome/parity bits previously calculated
 299  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 300  */
 301 static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode)
 302 {
 303         struct nand_chip *chip = mtd_to_nand(mtd);
 304         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 305
 306         stm32_fmc2_nfc_set_ecc(nfc, false);
 307
 308         if (chip->ecc.strength != FMC2_ECC_HAM) {
 309                 u32 pcr = readl(nfc->io_base + FMC2_PCR);
 310
 311                 if (mode == NAND_ECC_WRITE)
 312                         pcr |= FMC2_PCR_WEN;
 313                 else
 314                         pcr &= ~FMC2_PCR_WEN;
 315                 writel(pcr, nfc->io_base + FMC2_PCR);
 316
 317                 stm32_fmc2_nfc_clear_bch_irq(nfc);
 318         }
 319
 320         stm32_fmc2_nfc_set_ecc(nfc, true);
 321 }
 322
 323 /*
 324  * ECC Hamming calculation
 325  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 326  * max of 1-bit)
 327  */
 328 static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data,
 329                                         u8 *ecc)
 330 {
 331         struct nand_chip *chip = mtd_to_nand(mtd);
 332         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 333         u32 heccr, sr;
 334         int ret;
 335
 336         ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
 337                                  sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
 338         if (ret < 0) {
 339                 pr_err("Ham timeout\n");
 340                 return ret;
 341         }
 342
 343         heccr = readl(nfc->io_base + FMC2_HECCR);
 344
 345         ecc[0] = heccr;
 346         ecc[1] = heccr >> 8;
 347         ecc[2] = heccr >> 16;
 348
 349         stm32_fmc2_nfc_set_ecc(nfc, false);
 350
 351         return 0;
 352 }
 353
 354 static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat,
 355                                       u8 *read_ecc, u8 *calc_ecc)
 356 {
 357         u8 bit_position = 0, b0, b1, b2;
 358         u32 byte_addr = 0, b;
 359         u32 i, shifting = 1;
 360
 361         /* Indicate which bit and byte is faulty (if any) */
 362         b0 = read_ecc[0] ^ calc_ecc[0];
 363         b1 = read_ecc[1] ^ calc_ecc[1];
 364         b2 = read_ecc[2] ^ calc_ecc[2];
 365         b = b0 | (b1 << 8) | (b2 << 16);
 366
 367         /* No errors */
 368         if (likely(!b))
 369                 return 0;
 370
 371         /* Calculate bit position */
 372         for (i = 0; i < 3; i++) {
 373                 switch (b % 4) {
 374                 case 2:
 375                         bit_position += shifting;
 376                 case 1:
 377                         break;
 378                 default:
 379                         return -EBADMSG;
 380                 }
 381                 shifting <<= 1;
 382                 b >>= 2;
 383         }
 384
 385         /* Calculate byte position */
 386         shifting = 1;
 387         for (i = 0; i < 9; i++) {
 388                 switch (b % 4) {
 389                 case 2:
 390                         byte_addr += shifting;
 391                 case 1:
 392                         break;
 393                 default:
 394                         return -EBADMSG;
 395                 }
 396                 shifting <<= 1;
 397                 b >>= 2;
 398         }
 399
 400         /* Flip the bit */
 401         dat[byte_addr] ^= (1 << bit_position);
 402
 403         return 1;
 404 }
 405
 406 /*
 407  * ECC BCH calculation and correction
 408  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 409  * max of 4-bit/8-bit)
 410  */
 411
 412 static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data,
 413                                         u8 *ecc)
 414 {
 415         struct nand_chip *chip = mtd_to_nand(mtd);
 416         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 417         u32 bchpbr, bchisr;
 418         int ret;
 419
 420         /* Wait until the BCH code is ready */
 421         ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
 422                                  bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
 423         if (ret < 0) {
 424                 pr_err("Bch timeout\n");
 425                 return ret;
 426         }
 427
 428         /* Read parity bits */
 429         bchpbr = readl(nfc->io_base + FMC2_BCHPBR1);
 430         ecc[0] = bchpbr;
 431         ecc[1] = bchpbr >> 8;
 432         ecc[2] = bchpbr >> 16;
 433         ecc[3] = bchpbr >> 24;
 434
 435         bchpbr = readl(nfc->io_base + FMC2_BCHPBR2);
 436         ecc[4] = bchpbr;
 437         ecc[5] = bchpbr >> 8;
 438         ecc[6] = bchpbr >> 16;
 439
 440         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 441                 ecc[7] = bchpbr >> 24;
 442
 443                 bchpbr = readl(nfc->io_base + FMC2_BCHPBR3);
 444                 ecc[8] = bchpbr;
 445                 ecc[9] = bchpbr >> 8;
 446                 ecc[10] = bchpbr >> 16;
 447                 ecc[11] = bchpbr >> 24;
 448
 449                 bchpbr = readl(nfc->io_base + FMC2_BCHPBR4);
 450                 ecc[12] = bchpbr;
 451         }
 452
 453         stm32_fmc2_nfc_set_ecc(nfc, false);
 454
 455         return 0;
 456 }
 457
 458 static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat,
 459                                       u8 *read_ecc, u8 *calc_ecc)
 460 {
 461         struct nand_chip *chip = mtd_to_nand(mtd);
 462         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 463         u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
 464         u16 pos[8];
 465         int i, ret, den, eccsize = chip->ecc.size;
 466         unsigned int nb_errs = 0;
 467
 468         /* Wait until the decoding error is ready */
 469         ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
 470                                  bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
 471         if (ret < 0) {
 472                 pr_err("Bch timeout\n");
 473                 return ret;
 474         }
 475
 476         bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0);
 477         bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1);
 478         bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2);
 479         bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3);
 480         bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4);
 481
 482         stm32_fmc2_nfc_set_ecc(nfc, false);
 483
 484         /* No errors found */
 485         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 486                 return 0;
 487
 488         /* Too many errors detected */
 489         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 490                 return -EBADMSG;
 491
 492         pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
 493         pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
 494         pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
 495         pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
 496         pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
 497         pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
 498         pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
 499         pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
 500
 501         den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
 502         for (i = 0; i < den; i++) {
 503                 if (pos[i] < eccsize * 8) {
 504                         __change_bit(pos[i], (unsigned long *)dat);
 505                         nb_errs++;
 506                 }
 507         }
 508
 509         return nb_errs;
 510 }
 511
 512 static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd,
 513                                     struct nand_chip *chip, u8 *buf,
 514                                     int oob_required, int page)
 515 {
 516         int i, s, stat, eccsize = chip->ecc.size;
 517         int eccbytes = chip->ecc.bytes;
 518         int eccsteps = chip->ecc.steps;
 519         int eccstrength = chip->ecc.strength;
 520         u8 *p = buf;
 521         u8 *ecc_calc = chip->buffers->ecccalc;
 522         u8 *ecc_code = chip->buffers->ecccode;
 523         unsigned int max_bitflips = 0;
 524
 525         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 526              s++, i += eccbytes, p += eccsize) {
 527                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 528
 529                 /* Read the nand page sector (512 bytes) */
 530                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
 531                 chip->read_buf(mtd, p, eccsize);
 532
 533                 /* Read the corresponding ECC bytes */
 534                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
 535                 chip->read_buf(mtd, ecc_code, eccbytes);
 536
 537                 /* Correct the data */
 538                 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
 539                 if (stat == -EBADMSG)
 540                         /* Check for empty pages with bitflips */
 541                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 542                                                            ecc_code, eccbytes,
 543                                                            NULL, 0,
 544                                                            eccstrength);
 545
 546                 if (stat < 0) {
 547                         mtd->ecc_stats.failed++;
 548                 } else {
 549                         mtd->ecc_stats.corrected += stat;
 550                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 551                 }
 552         }
 553
 554         /* Read oob */
 555         if (oob_required) {
 556                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 557                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 558         }
 559
 560         return max_bitflips;
 561 }
 562
 563 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
 564 {
 565         u32 pcr = readl(nfc->io_base + FMC2_PCR);
 566         u32 bcr1 = readl(nfc->io_base + FMC2_BCR1);
 567
 568         /* Set CS used to undefined */
 569         nfc->cs_sel = -1;
 570
 571         /* Enable wait feature and nand flash memory bank */
 572         pcr |= FMC2_PCR_PWAITEN;
 573         pcr |= FMC2_PCR_PBKEN;
 574
 575         /* Set buswidth to 8 bits mode for identification */
 576         pcr &= ~FMC2_PCR_PWID;
 577
 578         /* ECC logic is disabled */
 579         pcr &= ~FMC2_PCR_ECCEN;
 580
 581         /* Default mode */
 582         pcr &= ~FMC2_PCR_ECCALG;
 583         pcr &= ~FMC2_PCR_BCHECC;
 584         pcr &= ~FMC2_PCR_WEN;
 585
 586         /* Set default ECC sector size */
 587         pcr &= ~FMC2_PCR_ECCSS;
 588         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
 589
 590         /* Set default tclr/tar timings */
 591         pcr &= ~FMC2_PCR_TCLR;
 592         pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
 593         pcr &= ~FMC2_PCR_TAR;
 594         pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
 595
 596         /* Enable FMC2 controller */
 597         bcr1 |= FMC2_BCR1_FMC2EN;
 598
 599         writel(bcr1, nfc->io_base + FMC2_BCR1);
 600         writel(pcr, nfc->io_base + FMC2_PCR);
 601         writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
 602         writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
 603 }
 604
 605 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
 606                                         const struct nand_sdr_timings *sdrt)
 607 {
 608         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 609         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 610         struct stm32_fmc2_timings *tims = &nand->timings;
 611         unsigned long hclk = clk_get_rate(&nfc->clk);
 612         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 613         unsigned long timing, tar, tclr, thiz, twait;
 614         unsigned long tset_mem, tset_att, thold_mem, thold_att;
 615
 616         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
 617         timing = DIV_ROUND_UP(tar, hclkp) - 1;
 618         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 619
 620         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
 621         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
 622         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 623
 624         tims->thiz = FMC2_THIZ;
 625         thiz = (tims->thiz + 1) * hclkp;
 626
 627         /*
 628          * tWAIT > tRP
 629          * tWAIT > tWP
 630          * tWAIT > tREA + tIO
 631          */
 632         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
 633         twait = max_t(unsigned long, twait, sdrt->tWP_min);
 634         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
 635         timing = DIV_ROUND_UP(twait, hclkp);
 636         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 637
 638         /*
 639          * tSETUP_MEM > tCS - tWAIT
 640          * tSETUP_MEM > tALS - tWAIT
 641          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
 642          */
 643         tset_mem = hclkp;
 644         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
 645                 tset_mem = sdrt->tCS_min - twait;
 646         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
 647                 tset_mem = sdrt->tALS_min - twait;
 648         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 649             (tset_mem < sdrt->tDS_min - (twait - thiz)))
 650                 tset_mem = sdrt->tDS_min - (twait - thiz);
 651         timing = DIV_ROUND_UP(tset_mem, hclkp);
 652         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 653
 654         /*
 655          * tHOLD_MEM > tCH
 656          * tHOLD_MEM > tREH - tSETUP_MEM
 657          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
 658          */
 659         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
 660         if (sdrt->tREH_min > tset_mem &&
 661             (thold_mem < sdrt->tREH_min - tset_mem))
 662                 thold_mem = sdrt->tREH_min - tset_mem;
 663         if ((sdrt->tRC_min > tset_mem + twait) &&
 664             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
 665                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
 666         if ((sdrt->tWC_min > tset_mem + twait) &&
 667             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
 668                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
 669         timing = DIV_ROUND_UP(thold_mem, hclkp);
 670         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 671
 672         /*
 673          * tSETUP_ATT > tCS - tWAIT
 674          * tSETUP_ATT > tCLS - tWAIT
 675          * tSETUP_ATT > tALS - tWAIT
 676          * tSETUP_ATT > tRHW - tHOLD_MEM
 677          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
 678          */
 679         tset_att = hclkp;
 680         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
 681                 tset_att = sdrt->tCS_min - twait;
 682         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
 683                 tset_att = sdrt->tCLS_min - twait;
 684         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
 685                 tset_att = sdrt->tALS_min - twait;
 686         if (sdrt->tRHW_min > thold_mem &&
 687             (tset_att < sdrt->tRHW_min - thold_mem))
 688                 tset_att = sdrt->tRHW_min - thold_mem;
 689         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 690             (tset_att < sdrt->tDS_min - (twait - thiz)))
 691                 tset_att = sdrt->tDS_min - (twait - thiz);
 692         timing = DIV_ROUND_UP(tset_att, hclkp);
 693         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 694
 695         /*
 696          * tHOLD_ATT > tALH
 697          * tHOLD_ATT > tCH
 698          * tHOLD_ATT > tCLH
 699          * tHOLD_ATT > tCOH
 700          * tHOLD_ATT > tDH
 701          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
 702          * tHOLD_ATT > tADL - tSETUP_MEM
 703          * tHOLD_ATT > tWH - tSETUP_MEM
 704          * tHOLD_ATT > tWHR - tSETUP_MEM
 705          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
 706          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
 707          */
 708         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
 709         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
 710         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
 711         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
 712         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
 713         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
 714             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
 715                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
 716         if (sdrt->tADL_min > tset_mem &&
 717             (thold_att < sdrt->tADL_min - tset_mem))
 718                 thold_att = sdrt->tADL_min - tset_mem;
 719         if (sdrt->tWH_min > tset_mem &&
 720             (thold_att < sdrt->tWH_min - tset_mem))
 721                 thold_att = sdrt->tWH_min - tset_mem;
 722         if (sdrt->tWHR_min > tset_mem &&
 723             (thold_att < sdrt->tWHR_min - tset_mem))
 724                 thold_att = sdrt->tWHR_min - tset_mem;
 725         if ((sdrt->tRC_min > tset_att + twait) &&
 726             (thold_att < sdrt->tRC_min - (tset_att + twait)))
 727                 thold_att = sdrt->tRC_min - (tset_att + twait);
 728         if ((sdrt->tWC_min > tset_att + twait) &&
 729             (thold_att < sdrt->tWC_min - (tset_att + twait)))
 730                 thold_att = sdrt->tWC_min - (tset_att + twait);
 731         timing = DIV_ROUND_UP(thold_att, hclkp);
 732         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 733 }
 734
 735 static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr,
 736                                           const struct nand_data_interface *cf)
 737 {
 738         struct nand_chip *chip = mtd_to_nand(mtd);
 739         const struct nand_sdr_timings *sdrt;
 740
 741         sdrt = nand_get_sdr_timings(cf);
 742         if (IS_ERR(sdrt))
 743                 return PTR_ERR(sdrt);
 744
 745         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
 746                 return 0;
 747
 748         stm32_fmc2_nfc_calc_timings(chip, sdrt);
 749         stm32_fmc2_nfc_timings_init(chip);
 750
 751         return 0;
 752 }
 753
 754 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
 755 {
 756         chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
 757
 758         /*
 759          * Specific callbacks to read/write a page depending on
 760          * the algo used (Hamming, BCH).
 761          */
 762         if (chip->ecc.strength == FMC2_ECC_HAM) {
 763                 /* Hamming is used */
 764                 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
 765                 chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
 766                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
 767                 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
 768                 return;
 769         }
 770
 771         /* BCH is used */
 772         chip->ecc.read_page = stm32_fmc2_nfc_read_page;
 773         chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
 774         chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
 775
 776         if (chip->ecc.strength == FMC2_ECC_BCH8)
 777                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
 778         else
 779                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
 780 }
 781
 782 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
 783 {
 784         /* Hamming */
 785         if (strength == FMC2_ECC_HAM)
 786                 return 4;
 787
 788         /* BCH8 */
 789         if (strength == FMC2_ECC_BCH8)
 790                 return 14;
 791
 792         /* BCH4 */
 793         return 8;
 794 }
 795
 796 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
 797                      FMC2_ECC_STEP_SIZE,
 798                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
 799
 800 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node)
 801 {
 802         struct stm32_fmc2_nand *nand = &nfc->nand;
 803         u32 cs[FMC2_MAX_CE];
 804         int ret, i;
 805
 806         if (!ofnode_get_property(node, "reg", &nand->ncs))
 807                 return -EINVAL;
 808
 809         nand->ncs /= sizeof(u32);
 810         if (!nand->ncs) {
 811                 pr_err("Invalid reg property size\n");
 812                 return -EINVAL;
 813         }
 814
 815         ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
 816         if (ret < 0) {
 817                 pr_err("Could not retrieve reg property\n");
 818                 return -EINVAL;
 819         }
 820
 821         for (i = 0; i < nand->ncs; i++) {
 822                 if (cs[i] >= FMC2_MAX_CE) {
 823                         pr_err("Invalid reg value: %d\n",
 824                                nand->cs_used[i]);
 825                         return -EINVAL;
 826                 }
 827
 828                 if (nfc->cs_assigned & BIT(cs[i])) {
 829                         pr_err("Cs already assigned: %d\n",
 830                                nand->cs_used[i]);
 831                         return -EINVAL;
 832                 }
 833
 834                 nfc->cs_assigned |= BIT(cs[i]);
 835                 nand->cs_used[i] = cs[i];
 836         }
 837
 838         nand->chip.flash_node = ofnode_to_offset(node);
 839
 840         return 0;
 841 }
 842
 843 static int stm32_fmc2_nfc_parse_dt(struct udevice *dev,
 844                                    struct stm32_fmc2_nfc *nfc)
 845 {
 846         ofnode child;
 847         int ret, nchips = 0;
 848
 849         dev_for_each_subnode(child, dev)
 850                 nchips++;
 851
 852         if (!nchips) {
 853                 pr_err("NAND chip not defined\n");
 854                 return -EINVAL;
 855         }
 856
 857         if (nchips > 1) {
 858                 pr_err("Too many NAND chips defined\n");
 859                 return -EINVAL;
 860         }
 861
 862         dev_for_each_subnode(child, dev) {
 863                 ret = stm32_fmc2_nfc_parse_child(nfc, child);
 864                 if (ret)
 865                         return ret;
 866         }
 867
 868         return 0;
 869 }
 870
 871 static int stm32_fmc2_nfc_probe(struct udevice *dev)
 872 {
 873         struct stm32_fmc2_nfc *nfc = dev_get_priv(dev);
 874         struct stm32_fmc2_nand *nand = &nfc->nand;
 875         struct nand_chip *chip = &nand->chip;
 876         struct mtd_info *mtd = &chip->mtd;
 877         struct nand_ecclayout *ecclayout;
 878         struct resource resource;
 879         struct reset_ctl reset;
 880         int oob_index, chip_cs, mem_region, ret;
 881         unsigned int i;
 882
 883         spin_lock_init(&nfc->controller.lock);
 884         init_waitqueue_head(&nfc->controller.wq);
 885
 886         ret = stm32_fmc2_nfc_parse_dt(dev, nfc);
 887         if (ret)
 888                 return ret;
 889
 890         /* Get resources */
 891         ret = dev_read_resource(dev, 0, &resource);
 892         if (ret) {
 893                 pr_err("Resource io_base not found");
 894                 return ret;
 895         }
 896         nfc->io_base = (void __iomem *)resource.start;
 897
 898         for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
 899              chip_cs++, mem_region += 3) {
 900                 if (!(nfc->cs_assigned & BIT(chip_cs)))
 901                         continue;
 902
 903                 ret = dev_read_resource(dev, mem_region, &resource);
 904                 if (ret) {
 905                         pr_err("Resource data_base not found for cs%d",
 906                                chip_cs);
 907                         return ret;
 908                 }
 909                 nfc->data_base[chip_cs] = (void __iomem *)resource.start;
 910
 911                 ret = dev_read_resource(dev, mem_region + 1, &resource);
 912                 if (ret) {
 913                         pr_err("Resource cmd_base not found for cs%d",
 914                                chip_cs);
 915                         return ret;
 916                 }
 917                 nfc->cmd_base[chip_cs] = (void __iomem *)resource.start;
 918
 919                 ret = dev_read_resource(dev, mem_region + 2, &resource);
 920                 if (ret) {
 921                         pr_err("Resource addr_base not found for cs%d",
 922                                chip_cs);
 923                         return ret;
 924                 }
 925                 nfc->addr_base[chip_cs] = (void __iomem *)resource.start;
 926         }
 927
 928         /* Enable the clock */
 929         ret = clk_get_by_index(dev, 0, &nfc->clk);
 930         if (ret)
 931                 return ret;
 932
 933         ret = clk_enable(&nfc->clk);
 934         if (ret)
 935                 return ret;
 936
 937         /* Reset */
 938         ret = reset_get_by_index(dev, 0, &reset);
 939         if (!ret) {
 940                 reset_assert(&reset);
 941                 udelay(2);
 942                 reset_deassert(&reset);
 943         }
 944
 945         stm32_fmc2_nfc_init(nfc);
 946
 947         chip->controller = &nfc->base;
 948         chip->select_chip = stm32_fmc2_nfc_select_chip;
 949         chip->setup_data_interface = stm32_fmc2_nfc_setup_interface;
 950         chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl;
 951         chip->chip_delay = FMC2_RB_DELAY_US;
 952         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
 953                          NAND_USE_BOUNCE_BUFFER;
 954
 955         /* Default ECC settings */
 956         chip->ecc.mode = NAND_ECC_HW;
 957         chip->ecc.size = FMC2_ECC_STEP_SIZE;
 958         chip->ecc.strength = FMC2_ECC_BCH8;
 959
 960         ret = nand_scan_ident(mtd, nand->ncs, NULL);
 961         if (ret)
 962                 return ret;
 963
 964         /*
 965          * Only NAND_ECC_HW mode is actually supported
 966          * Hamming => ecc.strength = 1
 967          * BCH4 => ecc.strength = 4
 968          * BCH8 => ecc.strength = 8
 969          * ECC sector size = 512
 970          */
 971         if (chip->ecc.mode != NAND_ECC_HW) {
 972                 pr_err("Nand_ecc_mode is not well defined in the DT\n");
 973                 return -EINVAL;
 974         }
 975
 976         ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
 977                                   mtd->oobsize - FMC2_BBM_LEN);
 978         if (ret) {
 979                 pr_err("No valid ECC settings set\n");
 980                 return ret;
 981         }
 982
 983         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 984                 chip->bbt_options |= NAND_BBT_NO_OOB;
 985
 986         stm32_fmc2_nfc_nand_callbacks_setup(chip);
 987
 988         /* Define ECC layout */
 989         ecclayout = &nfc->ecclayout;
 990         ecclayout->eccbytes = chip->ecc.bytes *
 991                               (mtd->writesize / chip->ecc.size);
 992         oob_index = FMC2_BBM_LEN;
 993         for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
 994                 ecclayout->eccpos[i] = oob_index;
 995         ecclayout->oobfree->offset = oob_index;
 996         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
 997         chip->ecc.layout = ecclayout;
 998
 999         if (chip->options & NAND_BUSWIDTH_16)
1000                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1001
1002         ret = nand_scan_tail(mtd);
1003         if (ret)
1004                 return ret;
1005
1006         return nand_register(0, mtd);
1007 }
1008
1009 static const struct udevice_id stm32_fmc2_nfc_match[] = {
1010         { .compatible = "st,stm32mp15-fmc2" },
1011         { /* Sentinel */ }
1012 };
1013
1014 U_BOOT_DRIVER(stm32_fmc2_nfc) = {
1015         .name = "stm32_fmc2_nfc",
1016         .id = UCLASS_MTD,
1017         .of_match = stm32_fmc2_nfc_match,
1018         .probe = stm32_fmc2_nfc_probe,
1019         .priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc),
1020 };
1021
1022 void board_nand_init(void)
1023 {
1024         struct udevice *dev;
1025         int ret;
1026
1027         ret = uclass_get_device_by_driver(UCLASS_MTD,
1028                                           DM_GET_DRIVER(stm32_fmc2_nfc),
1029                                           &dev);
1030         if (ret && ret != -ENODEV)
1031                 pr_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
1032                        ret);
1033 }