drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2019
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <nand.h>
  12 #include <reset.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/ioport.h>
  19
  20 /* Bad block marker length */
  21 #define FMC2_BBM_LEN                    2
  22
  23 /* ECC step size */
  24 #define FMC2_ECC_STEP_SIZE              512
  25
  26 /* Command delay */
  27 #define FMC2_RB_DELAY_US                30
  28
  29 /* Max chip enable */
  30 #define FMC2_MAX_CE                     2
  31
  32 /* Timings */
  33 #define FMC2_THIZ                       1
  34 #define FMC2_TIO                        8000
  35 #define FMC2_TSYNC                      3000
  36 #define FMC2_PCR_TIMING_MASK            0xf
  37 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  38
  39 /* FMC2 Controller Registers */
  40 #define FMC2_BCR1                       0x0
  41 #define FMC2_PCR                        0x80
  42 #define FMC2_SR                         0x84
  43 #define FMC2_PMEM                       0x88
  44 #define FMC2_PATT                       0x8c
  45 #define FMC2_HECCR                      0x94
  46 #define FMC2_BCHISR                     0x254
  47 #define FMC2_BCHICR                     0x258
  48 #define FMC2_BCHPBR1                    0x260
  49 #define FMC2_BCHPBR2                    0x264
  50 #define FMC2_BCHPBR3                    0x268
  51 #define FMC2_BCHPBR4                    0x26c
  52 #define FMC2_BCHDSR0                    0x27c
  53 #define FMC2_BCHDSR1                    0x280
  54 #define FMC2_BCHDSR2                    0x284
  55 #define FMC2_BCHDSR3                    0x288
  56 #define FMC2_BCHDSR4                    0x28c
  57
  58 /* Register: FMC2_BCR1 */
  59 #define FMC2_BCR1_FMC2EN                BIT(31)
  60
  61 /* Register: FMC2_PCR */
  62 #define FMC2_PCR_PWAITEN                BIT(1)
  63 #define FMC2_PCR_PBKEN                  BIT(2)
  64 #define FMC2_PCR_PWID                   GENMASK(5, 4)
  65 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  66 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  67 #define FMC2_PCR_ECCEN                  BIT(6)
  68 #define FMC2_PCR_ECCALG                 BIT(8)
  69 #define FMC2_PCR_TCLR                   GENMASK(12, 9)
  70 #define FMC2_PCR_TCLR_DEFAULT           0xf
  71 #define FMC2_PCR_TAR                    GENMASK(16, 13)
  72 #define FMC2_PCR_TAR_DEFAULT            0xf
  73 #define FMC2_PCR_ECCSS                  GENMASK(19, 17)
  74 #define FMC2_PCR_ECCSS_512              1
  75 #define FMC2_PCR_ECCSS_2048             3
  76 #define FMC2_PCR_BCHECC                 BIT(24)
  77 #define FMC2_PCR_WEN                    BIT(25)
  78
  79 /* Register: FMC2_SR */
  80 #define FMC2_SR_NWRF                    BIT(6)
  81
  82 /* Register: FMC2_PMEM */
  83 #define FMC2_PMEM_MEMSET                GENMASK(7, 0)
  84 #define FMC2_PMEM_MEMWAIT               GENMASK(15, 8)
  85 #define FMC2_PMEM_MEMHOLD               GENMASK(23, 16)
  86 #define FMC2_PMEM_MEMHIZ                GENMASK(31, 24)
  87 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
  88
  89 /* Register: FMC2_PATT */
  90 #define FMC2_PATT_ATTSET                GENMASK(7, 0)
  91 #define FMC2_PATT_ATTWAIT               GENMASK(15, 8)
  92 #define FMC2_PATT_ATTHOLD               GENMASK(23, 16)
  93 #define FMC2_PATT_ATTHIZ                GENMASK(31, 24)
  94 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
  95
  96 /* Register: FMC2_BCHISR */
  97 #define FMC2_BCHISR_DERF                BIT(1)
  98 #define FMC2_BCHISR_EPBRF               BIT(4)
  99
 100 /* Register: FMC2_BCHICR */
 101 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 102
 103 /* Register: FMC2_BCHDSR0 */
 104 #define FMC2_BCHDSR0_DUE                BIT(0)
 105 #define FMC2_BCHDSR0_DEF                BIT(1)
 106 #define FMC2_BCHDSR0_DEN                GENMASK(7, 4)
 107
 108 /* Register: FMC2_BCHDSR1 */
 109 #define FMC2_BCHDSR1_EBP1               GENMASK(12, 0)
 110 #define FMC2_BCHDSR1_EBP2               GENMASK(28, 16)
 111
 112 /* Register: FMC2_BCHDSR2 */
 113 #define FMC2_BCHDSR2_EBP3               GENMASK(12, 0)
 114 #define FMC2_BCHDSR2_EBP4               GENMASK(28, 16)
 115
 116 /* Register: FMC2_BCHDSR3 */
 117 #define FMC2_BCHDSR3_EBP5               GENMASK(12, 0)
 118 #define FMC2_BCHDSR3_EBP6               GENMASK(28, 16)
 119
 120 /* Register: FMC2_BCHDSR4 */
 121 #define FMC2_BCHDSR4_EBP7               GENMASK(12, 0)
 122 #define FMC2_BCHDSR4_EBP8               GENMASK(28, 16)
 123
 124 #define FMC2_NSEC_PER_SEC               1000000000L
 125
 126 #define FMC2_TIMEOUT_5S                 5000000
 127
 128 enum stm32_fmc2_ecc {
 129         FMC2_ECC_HAM = 1,
 130         FMC2_ECC_BCH4 = 4,
 131         FMC2_ECC_BCH8 = 8
 132 };
 133
 134 struct stm32_fmc2_timings {
 135         u8 tclr;
 136         u8 tar;
 137         u8 thiz;
 138         u8 twait;
 139         u8 thold_mem;
 140         u8 tset_mem;
 141         u8 thold_att;
 142         u8 tset_att;
 143 };
 144
 145 struct stm32_fmc2_nand {
 146         struct nand_chip chip;
 147         struct stm32_fmc2_timings timings;
 148         int ncs;
 149         int cs_used[FMC2_MAX_CE];
 150 };
 151
 152 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 153 {
 154         return container_of(chip, struct stm32_fmc2_nand, chip);
 155 }
 156
 157 struct stm32_fmc2_nfc {
 158         struct nand_hw_control base;
 159         struct stm32_fmc2_nand nand;
 160         struct nand_ecclayout ecclayout;
 161         fdt_addr_t io_base;
 162         fdt_addr_t data_base[FMC2_MAX_CE];
 163         fdt_addr_t cmd_base[FMC2_MAX_CE];
 164         fdt_addr_t addr_base[FMC2_MAX_CE];
 165         struct clk clk;
 166
 167         u8 cs_assigned;
 168         int cs_sel;
 169 };
 170
 171 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
 172 {
 173         return container_of(base, struct stm32_fmc2_nfc, base);
 174 }
 175
 176 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
 177 {
 178         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 179         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 180         struct stm32_fmc2_timings *timings = &nand->timings;
 181         u32 pmem, patt;
 182
 183         /* Set tclr/tar timings */
 184         clrsetbits_le32(nfc->io_base + FMC2_PCR,
 185                         FMC2_PCR_TCLR | FMC2_PCR_TAR,
 186                         FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
 187                         FIELD_PREP(FMC2_PCR_TAR, timings->tar));
 188
 189         /* Set tset/twait/thold/thiz timings in common bank */
 190         pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
 191         pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
 192         pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
 193         pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
 194         writel(pmem, nfc->io_base + FMC2_PMEM);
 195
 196         /* Set tset/twait/thold/thiz timings in attribut bank */
 197         patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
 198         patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
 199         patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
 200         patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
 201         writel(patt, nfc->io_base + FMC2_PATT);
 202 }
 203
 204 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
 205 {
 206         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 207         u32 pcr = 0, pcr_mask;
 208
 209         /* Configure ECC algorithm (default configuration is Hamming) */
 210         pcr_mask = FMC2_PCR_ECCALG;
 211         pcr_mask |= FMC2_PCR_BCHECC;
 212         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 213                 pcr |= FMC2_PCR_ECCALG;
 214                 pcr |= FMC2_PCR_BCHECC;
 215         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 216                 pcr |= FMC2_PCR_ECCALG;
 217         }
 218
 219         /* Set buswidth */
 220         pcr_mask |= FMC2_PCR_PWID;
 221         if (chip->options & NAND_BUSWIDTH_16)
 222                 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
 223
 224         /* Set ECC sector size */
 225         pcr_mask |= FMC2_PCR_ECCSS;
 226         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
 227
 228         clrsetbits_le32(nfc->io_base + FMC2_PCR, pcr_mask, pcr);
 229 }
 230
 231 static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr)
 232 {
 233         struct nand_chip *chip = mtd_to_nand(mtd);
 234         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 235         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 236
 237         if (chipnr < 0 || chipnr >= nand->ncs)
 238                 return;
 239
 240         if (nand->cs_used[chipnr] == nfc->cs_sel)
 241                 return;
 242
 243         nfc->cs_sel = nand->cs_used[chipnr];
 244         chip->IO_ADDR_R = (void __iomem *)nfc->data_base[nfc->cs_sel];
 245         chip->IO_ADDR_W = (void __iomem *)nfc->data_base[nfc->cs_sel];
 246
 247         stm32_fmc2_nfc_setup(chip);
 248         stm32_fmc2_nfc_timings_init(chip);
 249 }
 250
 251 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc,
 252                                            bool set)
 253 {
 254         u32 pcr;
 255
 256         pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
 257                     FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
 258
 259         clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_PWID, pcr);
 260 }
 261
 262 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
 263 {
 264         clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_ECCEN,
 265                         enable ? FMC2_PCR_ECCEN : 0);
 266 }
 267
 268 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
 269 {
 270         writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
 271 }
 272
 273 static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd,
 274                                     unsigned int ctrl)
 275 {
 276         struct nand_chip *chip = mtd_to_nand(mtd);
 277         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 278
 279         if (cmd == NAND_CMD_NONE)
 280                 return;
 281
 282         if (ctrl & NAND_CLE) {
 283                 writeb(cmd, nfc->cmd_base[nfc->cs_sel]);
 284                 return;
 285         }
 286
 287         writeb(cmd, nfc->addr_base[nfc->cs_sel]);
 288 }
 289
 290 /*
 291  * Enable ECC logic and reset syndrome/parity bits previously calculated
 292  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 293  */
 294 static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode)
 295 {
 296         struct nand_chip *chip = mtd_to_nand(mtd);
 297         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 298
 299         stm32_fmc2_nfc_set_ecc(nfc, false);
 300
 301         if (chip->ecc.strength != FMC2_ECC_HAM) {
 302                 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_WEN,
 303                                 mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
 304
 305                 stm32_fmc2_nfc_clear_bch_irq(nfc);
 306         }
 307
 308         stm32_fmc2_nfc_set_ecc(nfc, true);
 309 }
 310
 311 /*
 312  * ECC Hamming calculation
 313  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 314  * max of 1-bit)
 315  */
 316 static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data,
 317                                         u8 *ecc)
 318 {
 319         struct nand_chip *chip = mtd_to_nand(mtd);
 320         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 321         u32 heccr, sr;
 322         int ret;
 323
 324         ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
 325                                  sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
 326         if (ret < 0) {
 327                 pr_err("Ham timeout\n");
 328                 return ret;
 329         }
 330
 331         heccr = readl(nfc->io_base + FMC2_HECCR);
 332
 333         ecc[0] = heccr;
 334         ecc[1] = heccr >> 8;
 335         ecc[2] = heccr >> 16;
 336
 337         stm32_fmc2_nfc_set_ecc(nfc, false);
 338
 339         return 0;
 340 }
 341
 342 static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat,
 343                                       u8 *read_ecc, u8 *calc_ecc)
 344 {
 345         u8 bit_position = 0, b0, b1, b2;
 346         u32 byte_addr = 0, b;
 347         u32 i, shifting = 1;
 348
 349         /* Indicate which bit and byte is faulty (if any) */
 350         b0 = read_ecc[0] ^ calc_ecc[0];
 351         b1 = read_ecc[1] ^ calc_ecc[1];
 352         b2 = read_ecc[2] ^ calc_ecc[2];
 353         b = b0 | (b1 << 8) | (b2 << 16);
 354
 355         /* No errors */
 356         if (likely(!b))
 357                 return 0;
 358
 359         /* Calculate bit position */
 360         for (i = 0; i < 3; i++) {
 361                 switch (b % 4) {
 362                 case 2:
 363                         bit_position += shifting;
 364                 case 1:
 365                         break;
 366                 default:
 367                         return -EBADMSG;
 368                 }
 369                 shifting <<= 1;
 370                 b >>= 2;
 371         }
 372
 373         /* Calculate byte position */
 374         shifting = 1;
 375         for (i = 0; i < 9; i++) {
 376                 switch (b % 4) {
 377                 case 2:
 378                         byte_addr += shifting;
 379                 case 1:
 380                         break;
 381                 default:
 382                         return -EBADMSG;
 383                 }
 384                 shifting <<= 1;
 385                 b >>= 2;
 386         }
 387
 388         /* Flip the bit */
 389         dat[byte_addr] ^= (1 << bit_position);
 390
 391         return 1;
 392 }
 393
 394 /*
 395  * ECC BCH calculation and correction
 396  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 397  * max of 4-bit/8-bit)
 398  */
 399
 400 static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data,
 401                                         u8 *ecc)
 402 {
 403         struct nand_chip *chip = mtd_to_nand(mtd);
 404         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 405         u32 bchpbr, bchisr;
 406         int ret;
 407
 408         /* Wait until the BCH code is ready */
 409         ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
 410                                  bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
 411         if (ret < 0) {
 412                 pr_err("Bch timeout\n");
 413                 return ret;
 414         }
 415
 416         /* Read parity bits */
 417         bchpbr = readl(nfc->io_base + FMC2_BCHPBR1);
 418         ecc[0] = bchpbr;
 419         ecc[1] = bchpbr >> 8;
 420         ecc[2] = bchpbr >> 16;
 421         ecc[3] = bchpbr >> 24;
 422
 423         bchpbr = readl(nfc->io_base + FMC2_BCHPBR2);
 424         ecc[4] = bchpbr;
 425         ecc[5] = bchpbr >> 8;
 426         ecc[6] = bchpbr >> 16;
 427
 428         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 429                 ecc[7] = bchpbr >> 24;
 430
 431                 bchpbr = readl(nfc->io_base + FMC2_BCHPBR3);
 432                 ecc[8] = bchpbr;
 433                 ecc[9] = bchpbr >> 8;
 434                 ecc[10] = bchpbr >> 16;
 435                 ecc[11] = bchpbr >> 24;
 436
 437                 bchpbr = readl(nfc->io_base + FMC2_BCHPBR4);
 438                 ecc[12] = bchpbr;
 439         }
 440
 441         stm32_fmc2_nfc_set_ecc(nfc, false);
 442
 443         return 0;
 444 }
 445
 446 static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat,
 447                                       u8 *read_ecc, u8 *calc_ecc)
 448 {
 449         struct nand_chip *chip = mtd_to_nand(mtd);
 450         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 451         u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
 452         u16 pos[8];
 453         int i, ret, den, eccsize = chip->ecc.size;
 454         unsigned int nb_errs = 0;
 455
 456         /* Wait until the decoding error is ready */
 457         ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
 458                                  bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
 459         if (ret < 0) {
 460                 pr_err("Bch timeout\n");
 461                 return ret;
 462         }
 463
 464         bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0);
 465         bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1);
 466         bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2);
 467         bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3);
 468         bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4);
 469
 470         stm32_fmc2_nfc_set_ecc(nfc, false);
 471
 472         /* No errors found */
 473         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 474                 return 0;
 475
 476         /* Too many errors detected */
 477         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 478                 return -EBADMSG;
 479
 480         pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
 481         pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
 482         pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
 483         pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
 484         pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
 485         pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
 486         pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
 487         pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
 488
 489         den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
 490         for (i = 0; i < den; i++) {
 491                 if (pos[i] < eccsize * 8) {
 492                         __change_bit(pos[i], (unsigned long *)dat);
 493                         nb_errs++;
 494                 }
 495         }
 496
 497         return nb_errs;
 498 }
 499
 500 static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd,
 501                                     struct nand_chip *chip, u8 *buf,
 502                                     int oob_required, int page)
 503 {
 504         int i, s, stat, eccsize = chip->ecc.size;
 505         int eccbytes = chip->ecc.bytes;
 506         int eccsteps = chip->ecc.steps;
 507         int eccstrength = chip->ecc.strength;
 508         u8 *p = buf;
 509         u8 *ecc_calc = chip->buffers->ecccalc;
 510         u8 *ecc_code = chip->buffers->ecccode;
 511         unsigned int max_bitflips = 0;
 512
 513         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 514              s++, i += eccbytes, p += eccsize) {
 515                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 516
 517                 /* Read the nand page sector (512 bytes) */
 518                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
 519                 chip->read_buf(mtd, p, eccsize);
 520
 521                 /* Read the corresponding ECC bytes */
 522                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
 523                 chip->read_buf(mtd, ecc_code, eccbytes);
 524
 525                 /* Correct the data */
 526                 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
 527                 if (stat == -EBADMSG)
 528                         /* Check for empty pages with bitflips */
 529                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 530                                                            ecc_code, eccbytes,
 531                                                            NULL, 0,
 532                                                            eccstrength);
 533
 534                 if (stat < 0) {
 535                         mtd->ecc_stats.failed++;
 536                 } else {
 537                         mtd->ecc_stats.corrected += stat;
 538                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 539                 }
 540         }
 541
 542         /* Read oob */
 543         if (oob_required) {
 544                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 545                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 546         }
 547
 548         return max_bitflips;
 549 }
 550
 551 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc, bool has_parent)
 552 {
 553         u32 pcr = readl(nfc->io_base + FMC2_PCR);
 554
 555         /* Set CS used to undefined */
 556         nfc->cs_sel = -1;
 557
 558         /* Enable wait feature and nand flash memory bank */
 559         pcr |= FMC2_PCR_PWAITEN;
 560         pcr |= FMC2_PCR_PBKEN;
 561
 562         /* Set buswidth to 8 bits mode for identification */
 563         pcr &= ~FMC2_PCR_PWID;
 564
 565         /* ECC logic is disabled */
 566         pcr &= ~FMC2_PCR_ECCEN;
 567
 568         /* Default mode */
 569         pcr &= ~FMC2_PCR_ECCALG;
 570         pcr &= ~FMC2_PCR_BCHECC;
 571         pcr &= ~FMC2_PCR_WEN;
 572
 573         /* Set default ECC sector size */
 574         pcr &= ~FMC2_PCR_ECCSS;
 575         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
 576
 577         /* Set default tclr/tar timings */
 578         pcr &= ~FMC2_PCR_TCLR;
 579         pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
 580         pcr &= ~FMC2_PCR_TAR;
 581         pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
 582
 583         /* Enable FMC2 controller */
 584         if (!has_parent)
 585                 setbits_le32(nfc->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
 586
 587         writel(pcr, nfc->io_base + FMC2_PCR);
 588         writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
 589         writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
 590 }
 591
 592 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
 593                                         const struct nand_sdr_timings *sdrt)
 594 {
 595         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 596         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 597         struct stm32_fmc2_timings *tims = &nand->timings;
 598         unsigned long hclk = clk_get_rate(&nfc->clk);
 599         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 600         unsigned long timing, tar, tclr, thiz, twait;
 601         unsigned long tset_mem, tset_att, thold_mem, thold_att;
 602
 603         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
 604         timing = DIV_ROUND_UP(tar, hclkp) - 1;
 605         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 606
 607         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
 608         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
 609         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 610
 611         tims->thiz = FMC2_THIZ;
 612         thiz = (tims->thiz + 1) * hclkp;
 613
 614         /*
 615          * tWAIT > tRP
 616          * tWAIT > tWP
 617          * tWAIT > tREA + tIO
 618          */
 619         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
 620         twait = max_t(unsigned long, twait, sdrt->tWP_min);
 621         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
 622         timing = DIV_ROUND_UP(twait, hclkp);
 623         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 624
 625         /*
 626          * tSETUP_MEM > tCS - tWAIT
 627          * tSETUP_MEM > tALS - tWAIT
 628          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
 629          */
 630         tset_mem = hclkp;
 631         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
 632                 tset_mem = sdrt->tCS_min - twait;
 633         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
 634                 tset_mem = sdrt->tALS_min - twait;
 635         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 636             (tset_mem < sdrt->tDS_min - (twait - thiz)))
 637                 tset_mem = sdrt->tDS_min - (twait - thiz);
 638         timing = DIV_ROUND_UP(tset_mem, hclkp);
 639         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 640
 641         /*
 642          * tHOLD_MEM > tCH
 643          * tHOLD_MEM > tREH - tSETUP_MEM
 644          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
 645          */
 646         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
 647         if (sdrt->tREH_min > tset_mem &&
 648             (thold_mem < sdrt->tREH_min - tset_mem))
 649                 thold_mem = sdrt->tREH_min - tset_mem;
 650         if ((sdrt->tRC_min > tset_mem + twait) &&
 651             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
 652                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
 653         if ((sdrt->tWC_min > tset_mem + twait) &&
 654             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
 655                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
 656         timing = DIV_ROUND_UP(thold_mem, hclkp);
 657         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 658
 659         /*
 660          * tSETUP_ATT > tCS - tWAIT
 661          * tSETUP_ATT > tCLS - tWAIT
 662          * tSETUP_ATT > tALS - tWAIT
 663          * tSETUP_ATT > tRHW - tHOLD_MEM
 664          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
 665          */
 666         tset_att = hclkp;
 667         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
 668                 tset_att = sdrt->tCS_min - twait;
 669         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
 670                 tset_att = sdrt->tCLS_min - twait;
 671         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
 672                 tset_att = sdrt->tALS_min - twait;
 673         if (sdrt->tRHW_min > thold_mem &&
 674             (tset_att < sdrt->tRHW_min - thold_mem))
 675                 tset_att = sdrt->tRHW_min - thold_mem;
 676         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 677             (tset_att < sdrt->tDS_min - (twait - thiz)))
 678                 tset_att = sdrt->tDS_min - (twait - thiz);
 679         timing = DIV_ROUND_UP(tset_att, hclkp);
 680         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 681
 682         /*
 683          * tHOLD_ATT > tALH
 684          * tHOLD_ATT > tCH
 685          * tHOLD_ATT > tCLH
 686          * tHOLD_ATT > tCOH
 687          * tHOLD_ATT > tDH
 688          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
 689          * tHOLD_ATT > tADL - tSETUP_MEM
 690          * tHOLD_ATT > tWH - tSETUP_MEM
 691          * tHOLD_ATT > tWHR - tSETUP_MEM
 692          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
 693          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
 694          */
 695         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
 696         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
 697         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
 698         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
 699         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
 700         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
 701             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
 702                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
 703         if (sdrt->tADL_min > tset_mem &&
 704             (thold_att < sdrt->tADL_min - tset_mem))
 705                 thold_att = sdrt->tADL_min - tset_mem;
 706         if (sdrt->tWH_min > tset_mem &&
 707             (thold_att < sdrt->tWH_min - tset_mem))
 708                 thold_att = sdrt->tWH_min - tset_mem;
 709         if (sdrt->tWHR_min > tset_mem &&
 710             (thold_att < sdrt->tWHR_min - tset_mem))
 711                 thold_att = sdrt->tWHR_min - tset_mem;
 712         if ((sdrt->tRC_min > tset_att + twait) &&
 713             (thold_att < sdrt->tRC_min - (tset_att + twait)))
 714                 thold_att = sdrt->tRC_min - (tset_att + twait);
 715         if ((sdrt->tWC_min > tset_att + twait) &&
 716             (thold_att < sdrt->tWC_min - (tset_att + twait)))
 717                 thold_att = sdrt->tWC_min - (tset_att + twait);
 718         timing = DIV_ROUND_UP(thold_att, hclkp);
 719         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 720 }
 721
 722 static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr,
 723                                           const struct nand_data_interface *cf)
 724 {
 725         struct nand_chip *chip = mtd_to_nand(mtd);
 726         const struct nand_sdr_timings *sdrt;
 727
 728         sdrt = nand_get_sdr_timings(cf);
 729         if (IS_ERR(sdrt))
 730                 return PTR_ERR(sdrt);
 731
 732         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
 733                 return 0;
 734
 735         stm32_fmc2_nfc_calc_timings(chip, sdrt);
 736         stm32_fmc2_nfc_timings_init(chip);
 737
 738         return 0;
 739 }
 740
 741 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
 742 {
 743         chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
 744
 745         /*
 746          * Specific callbacks to read/write a page depending on
 747          * the algo used (Hamming, BCH).
 748          */
 749         if (chip->ecc.strength == FMC2_ECC_HAM) {
 750                 /* Hamming is used */
 751                 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
 752                 chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
 753                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
 754                 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
 755                 return;
 756         }
 757
 758         /* BCH is used */
 759         chip->ecc.read_page = stm32_fmc2_nfc_read_page;
 760         chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
 761         chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
 762
 763         if (chip->ecc.strength == FMC2_ECC_BCH8)
 764                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
 765         else
 766                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
 767 }
 768
 769 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
 770 {
 771         /* Hamming */
 772         if (strength == FMC2_ECC_HAM)
 773                 return 4;
 774
 775         /* BCH8 */
 776         if (strength == FMC2_ECC_BCH8)
 777                 return 14;
 778
 779         /* BCH4 */
 780         return 8;
 781 }
 782
 783 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
 784                      FMC2_ECC_STEP_SIZE,
 785                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
 786
 787 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node)
 788 {
 789         struct stm32_fmc2_nand *nand = &nfc->nand;
 790         u32 cs[FMC2_MAX_CE];
 791         int ret, i;
 792
 793         if (!ofnode_get_property(node, "reg", &nand->ncs))
 794                 return -EINVAL;
 795
 796         nand->ncs /= sizeof(u32);
 797         if (!nand->ncs) {
 798                 pr_err("Invalid reg property size\n");
 799                 return -EINVAL;
 800         }
 801
 802         ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
 803         if (ret < 0) {
 804                 pr_err("Could not retrieve reg property\n");
 805                 return -EINVAL;
 806         }
 807
 808         for (i = 0; i < nand->ncs; i++) {
 809                 if (cs[i] >= FMC2_MAX_CE) {
 810                         pr_err("Invalid reg value: %d\n",
 811                                nand->cs_used[i]);
 812                         return -EINVAL;
 813                 }
 814
 815                 if (nfc->cs_assigned & BIT(cs[i])) {
 816                         pr_err("Cs already assigned: %d\n",
 817                                nand->cs_used[i]);
 818                         return -EINVAL;
 819                 }
 820
 821                 nfc->cs_assigned |= BIT(cs[i]);
 822                 nand->cs_used[i] = cs[i];
 823         }
 824
 825         nand->chip.flash_node = ofnode_to_offset(node);
 826
 827         return 0;
 828 }
 829
 830 static int stm32_fmc2_nfc_parse_dt(struct udevice *dev,
 831                                    struct stm32_fmc2_nfc *nfc)
 832 {
 833         ofnode child;
 834         int ret, nchips = 0;
 835
 836         dev_for_each_subnode(child, dev)
 837                 nchips++;
 838
 839         if (!nchips) {
 840                 pr_err("NAND chip not defined\n");
 841                 return -EINVAL;
 842         }
 843
 844         if (nchips > 1) {
 845                 pr_err("Too many NAND chips defined\n");
 846                 return -EINVAL;
 847         }
 848
 849         dev_for_each_subnode(child, dev) {
 850                 ret = stm32_fmc2_nfc_parse_child(nfc, child);
 851                 if (ret)
 852                         return ret;
 853         }
 854
 855         return 0;
 856 }
 857
 858 static struct udevice *stm32_fmc2_nfc_get_cdev(struct udevice *dev)
 859 {
 860         struct udevice *pdev = dev_get_parent(dev);
 861         struct udevice *cdev = NULL;
 862         bool ebi_found = false;
 863
 864         if (pdev && ofnode_device_is_compatible(dev_ofnode(pdev),
 865                                                 "st,stm32mp1-fmc2-ebi"))
 866                 ebi_found = true;
 867
 868         if (ofnode_device_is_compatible(dev_ofnode(dev),
 869                                         "st,stm32mp1-fmc2-nfc")) {
 870                 if (ebi_found)
 871                         cdev = pdev;
 872
 873                 return cdev;
 874         }
 875
 876         if (!ebi_found)
 877                 cdev = dev;
 878
 879         return cdev;
 880 }
 881
 882 static int stm32_fmc2_nfc_probe(struct udevice *dev)
 883 {
 884         struct stm32_fmc2_nfc *nfc = dev_get_priv(dev);
 885         struct stm32_fmc2_nand *nand = &nfc->nand;
 886         struct nand_chip *chip = &nand->chip;
 887         struct mtd_info *mtd = &chip->mtd;
 888         struct nand_ecclayout *ecclayout;
 889         struct udevice *cdev;
 890         struct reset_ctl reset;
 891         int oob_index, chip_cs, mem_region, ret;
 892         unsigned int i;
 893         int start_region = 0;
 894         fdt_addr_t addr;
 895
 896         spin_lock_init(&nfc->controller.lock);
 897         init_waitqueue_head(&nfc->controller.wq);
 898
 899         cdev = stm32_fmc2_nfc_get_cdev(dev);
 900         if (!cdev)
 901                 return -EINVAL;
 902
 903         ret = stm32_fmc2_nfc_parse_dt(dev, nfc);
 904         if (ret)
 905                 return ret;
 906
 907         nfc->io_base = dev_read_addr(cdev);
 908         if (nfc->io_base == FDT_ADDR_T_NONE)
 909                 return -EINVAL;
 910
 911         if (dev == cdev)
 912                 start_region = 1;
 913
 914         for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
 915              chip_cs++, mem_region += 3) {
 916                 if (!(nfc->cs_assigned & BIT(chip_cs)))
 917                         continue;
 918
 919                 addr = dev_read_addr_index(dev, mem_region);
 920                 if (addr == FDT_ADDR_T_NONE) {
 921                         pr_err("Resource data_base not found for cs%d",
 922                                chip_cs);
 923                         return ret;
 924                 }
 925                 nfc->data_base[chip_cs] = addr;
 926
 927                 addr = dev_read_addr_index(dev, mem_region + 1);
 928                 if (addr == FDT_ADDR_T_NONE) {
 929                         pr_err("Resource cmd_base not found for cs%d",
 930                                chip_cs);
 931                         return ret;
 932                 }
 933                 nfc->cmd_base[chip_cs] = addr;
 934
 935                 addr = dev_read_addr_index(dev, mem_region + 2);
 936                 if (addr == FDT_ADDR_T_NONE) {
 937                         pr_err("Resource addr_base not found for cs%d",
 938                                chip_cs);
 939                         return ret;
 940                 }
 941                 nfc->addr_base[chip_cs] = addr;
 942         }
 943
 944         /* Enable the clock */
 945         ret = clk_get_by_index(cdev, 0, &nfc->clk);
 946         if (ret)
 947                 return ret;
 948
 949         ret = clk_enable(&nfc->clk);
 950         if (ret)
 951                 return ret;
 952
 953         /* Reset */
 954         ret = reset_get_by_index(dev, 0, &reset);
 955         if (!ret) {
 956                 reset_assert(&reset);
 957                 udelay(2);
 958                 reset_deassert(&reset);
 959         }
 960
 961         stm32_fmc2_nfc_init(nfc, dev != cdev);
 962
 963         chip->controller = &nfc->base;
 964         chip->select_chip = stm32_fmc2_nfc_select_chip;
 965         chip->setup_data_interface = stm32_fmc2_nfc_setup_interface;
 966         chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl;
 967         chip->chip_delay = FMC2_RB_DELAY_US;
 968         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
 969                          NAND_USE_BOUNCE_BUFFER;
 970
 971         /* Default ECC settings */
 972         chip->ecc.mode = NAND_ECC_HW;
 973         chip->ecc.size = FMC2_ECC_STEP_SIZE;
 974         chip->ecc.strength = FMC2_ECC_BCH8;
 975
 976         ret = nand_scan_ident(mtd, nand->ncs, NULL);
 977         if (ret)
 978                 return ret;
 979
 980         /*
 981          * Only NAND_ECC_HW mode is actually supported
 982          * Hamming => ecc.strength = 1
 983          * BCH4 => ecc.strength = 4
 984          * BCH8 => ecc.strength = 8
 985          * ECC sector size = 512
 986          */
 987         if (chip->ecc.mode != NAND_ECC_HW) {
 988                 pr_err("Nand_ecc_mode is not well defined in the DT\n");
 989                 return -EINVAL;
 990         }
 991
 992         ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
 993                                   mtd->oobsize - FMC2_BBM_LEN);
 994         if (ret) {
 995                 pr_err("No valid ECC settings set\n");
 996                 return ret;
 997         }
 998
 999         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1000                 chip->bbt_options |= NAND_BBT_NO_OOB;
1001
1002         stm32_fmc2_nfc_nand_callbacks_setup(chip);
1003
1004         /* Define ECC layout */
1005         ecclayout = &nfc->ecclayout;
1006         ecclayout->eccbytes = chip->ecc.bytes *
1007                               (mtd->writesize / chip->ecc.size);
1008         oob_index = FMC2_BBM_LEN;
1009         for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1010                 ecclayout->eccpos[i] = oob_index;
1011         ecclayout->oobfree->offset = oob_index;
1012         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1013         chip->ecc.layout = ecclayout;
1014
1015         if (chip->options & NAND_BUSWIDTH_16)
1016                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1017
1018         ret = nand_scan_tail(mtd);
1019         if (ret)
1020                 return ret;
1021
1022         return nand_register(0, mtd);
1023 }
1024
1025 static const struct udevice_id stm32_fmc2_nfc_match[] = {
1026         { .compatible = "st,stm32mp15-fmc2" },
1027         { .compatible = "st,stm32mp1-fmc2-nfc" },
1028         { /* Sentinel */ }
1029 };
1030
1031 U_BOOT_DRIVER(stm32_fmc2_nfc) = {
1032         .name = "stm32_fmc2_nfc",
1033         .id = UCLASS_MTD,
1034         .of_match = stm32_fmc2_nfc_match,
1035         .probe = stm32_fmc2_nfc_probe,
1036         .priv_auto      = sizeof(struct stm32_fmc2_nfc),
1037 };
1038
1039 void board_nand_init(void)
1040 {
1041         struct udevice *dev;
1042         int ret;
1043
1044         ret = uclass_get_device_by_driver(UCLASS_MTD,
1045                                           DM_GET_DRIVER(stm32_fmc2_nfc),
1046                                           &dev);
1047         if (ret && ret != -ENODEV)
1048                 pr_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
1049                        ret);
1050 }