drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2019
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #define LOG_CATEGORY UCLASS_MTD
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <log.h>
  13 #include <nand.h>
  14 #include <reset.h>
  15 #include <asm/gpio.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/bitfield.h>
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/ioport.h>
  23 #include <linux/mtd/rawnand.h>
  24
  25 /* Bad block marker length */
  26 #define FMC2_BBM_LEN                    2
  27
  28 /* ECC step size */
  29 #define FMC2_ECC_STEP_SIZE              512
  30
  31 /* Command delay */
  32 #define FMC2_RB_DELAY_US                30
  33
  34 /* Max chip enable */
  35 #define FMC2_MAX_CE                     2
  36
  37 /* Timings */
  38 #define FMC2_THIZ                       1
  39 #define FMC2_TIO                        8000
  40 #define FMC2_TSYNC                      3000
  41 #define FMC2_PCR_TIMING_MASK            0xf
  42 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  43
  44 /* FMC2 Controller Registers */
  45 #define FMC2_BCR1                       0x0
  46 #define FMC2_PCR                        0x80
  47 #define FMC2_SR                         0x84
  48 #define FMC2_PMEM                       0x88
  49 #define FMC2_PATT                       0x8c
  50 #define FMC2_HECCR                      0x94
  51 #define FMC2_BCHISR                     0x254
  52 #define FMC2_BCHICR                     0x258
  53 #define FMC2_BCHPBR1                    0x260
  54 #define FMC2_BCHPBR2                    0x264
  55 #define FMC2_BCHPBR3                    0x268
  56 #define FMC2_BCHPBR4                    0x26c
  57 #define FMC2_BCHDSR0                    0x27c
  58 #define FMC2_BCHDSR1                    0x280
  59 #define FMC2_BCHDSR2                    0x284
  60 #define FMC2_BCHDSR3                    0x288
  61 #define FMC2_BCHDSR4                    0x28c
  62
  63 /* Register: FMC2_BCR1 */
  64 #define FMC2_BCR1_FMC2EN                BIT(31)
  65
  66 /* Register: FMC2_PCR */
  67 #define FMC2_PCR_PWAITEN                BIT(1)
  68 #define FMC2_PCR_PBKEN                  BIT(2)
  69 #define FMC2_PCR_PWID                   GENMASK(5, 4)
  70 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  71 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  72 #define FMC2_PCR_ECCEN                  BIT(6)
  73 #define FMC2_PCR_ECCALG                 BIT(8)
  74 #define FMC2_PCR_TCLR                   GENMASK(12, 9)
  75 #define FMC2_PCR_TCLR_DEFAULT           0xf
  76 #define FMC2_PCR_TAR                    GENMASK(16, 13)
  77 #define FMC2_PCR_TAR_DEFAULT            0xf
  78 #define FMC2_PCR_ECCSS                  GENMASK(19, 17)
  79 #define FMC2_PCR_ECCSS_512              1
  80 #define FMC2_PCR_ECCSS_2048             3
  81 #define FMC2_PCR_BCHECC                 BIT(24)
  82 #define FMC2_PCR_WEN                    BIT(25)
  83
  84 /* Register: FMC2_SR */
  85 #define FMC2_SR_NWRF                    BIT(6)
  86
  87 /* Register: FMC2_PMEM */
  88 #define FMC2_PMEM_MEMSET                GENMASK(7, 0)
  89 #define FMC2_PMEM_MEMWAIT               GENMASK(15, 8)
  90 #define FMC2_PMEM_MEMHOLD               GENMASK(23, 16)
  91 #define FMC2_PMEM_MEMHIZ                GENMASK(31, 24)
  92 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
  93
  94 /* Register: FMC2_PATT */
  95 #define FMC2_PATT_ATTSET                GENMASK(7, 0)
  96 #define FMC2_PATT_ATTWAIT               GENMASK(15, 8)
  97 #define FMC2_PATT_ATTHOLD               GENMASK(23, 16)
  98 #define FMC2_PATT_ATTHIZ                GENMASK(31, 24)
  99 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
 100
 101 /* Register: FMC2_BCHISR */
 102 #define FMC2_BCHISR_DERF                BIT(1)
 103 #define FMC2_BCHISR_EPBRF               BIT(4)
 104
 105 /* Register: FMC2_BCHICR */
 106 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 107
 108 /* Register: FMC2_BCHDSR0 */
 109 #define FMC2_BCHDSR0_DUE                BIT(0)
 110 #define FMC2_BCHDSR0_DEF                BIT(1)
 111 #define FMC2_BCHDSR0_DEN                GENMASK(7, 4)
 112
 113 /* Register: FMC2_BCHDSR1 */
 114 #define FMC2_BCHDSR1_EBP1               GENMASK(12, 0)
 115 #define FMC2_BCHDSR1_EBP2               GENMASK(28, 16)
 116
 117 /* Register: FMC2_BCHDSR2 */
 118 #define FMC2_BCHDSR2_EBP3               GENMASK(12, 0)
 119 #define FMC2_BCHDSR2_EBP4               GENMASK(28, 16)
 120
 121 /* Register: FMC2_BCHDSR3 */
 122 #define FMC2_BCHDSR3_EBP5               GENMASK(12, 0)
 123 #define FMC2_BCHDSR3_EBP6               GENMASK(28, 16)
 124
 125 /* Register: FMC2_BCHDSR4 */
 126 #define FMC2_BCHDSR4_EBP7               GENMASK(12, 0)
 127 #define FMC2_BCHDSR4_EBP8               GENMASK(28, 16)
 128
 129 #define FMC2_NSEC_PER_SEC               1000000000L
 130
 131 #define FMC2_TIMEOUT_5S                 5000000
 132
 133 enum stm32_fmc2_ecc {
 134         FMC2_ECC_HAM = 1,
 135         FMC2_ECC_BCH4 = 4,
 136         FMC2_ECC_BCH8 = 8
 137 };
 138
 139 struct stm32_fmc2_timings {
 140         u8 tclr;
 141         u8 tar;
 142         u8 thiz;
 143         u8 twait;
 144         u8 thold_mem;
 145         u8 tset_mem;
 146         u8 thold_att;
 147         u8 tset_att;
 148 };
 149
 150 struct stm32_fmc2_nand {
 151         struct nand_chip chip;
 152         struct stm32_fmc2_timings timings;
 153         struct gpio_desc wp_gpio;
 154         int ncs;
 155         int cs_used[FMC2_MAX_CE];
 156 };
 157
 158 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 159 {
 160         return container_of(chip, struct stm32_fmc2_nand, chip);
 161 }
 162
 163 struct stm32_fmc2_nfc {
 164         struct nand_hw_control base;
 165         struct stm32_fmc2_nand nand;
 166         struct nand_ecclayout ecclayout;
 167         fdt_addr_t io_base;
 168         fdt_addr_t data_base[FMC2_MAX_CE];
 169         fdt_addr_t cmd_base[FMC2_MAX_CE];
 170         fdt_addr_t addr_base[FMC2_MAX_CE];
 171         struct clk clk;
 172
 173         u8 cs_assigned;
 174         int cs_sel;
 175 };
 176
 177 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
 178 {
 179         return container_of(base, struct stm32_fmc2_nfc, base);
 180 }
 181
 182 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
 183 {
 184         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 185         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 186         struct stm32_fmc2_timings *timings = &nand->timings;
 187         u32 pmem, patt;
 188
 189         /* Set tclr/tar timings */
 190         clrsetbits_le32(nfc->io_base + FMC2_PCR,
 191                         FMC2_PCR_TCLR | FMC2_PCR_TAR,
 192                         FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
 193                         FIELD_PREP(FMC2_PCR_TAR, timings->tar));
 194
 195         /* Set tset/twait/thold/thiz timings in common bank */
 196         pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
 197         pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
 198         pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
 199         pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
 200         writel(pmem, nfc->io_base + FMC2_PMEM);
 201
 202         /* Set tset/twait/thold/thiz timings in attribut bank */
 203         patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
 204         patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
 205         patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
 206         patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
 207         writel(patt, nfc->io_base + FMC2_PATT);
 208 }
 209
 210 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
 211 {
 212         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 213         u32 pcr = 0, pcr_mask;
 214
 215         /* Configure ECC algorithm (default configuration is Hamming) */
 216         pcr_mask = FMC2_PCR_ECCALG;
 217         pcr_mask |= FMC2_PCR_BCHECC;
 218         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 219                 pcr |= FMC2_PCR_ECCALG;
 220                 pcr |= FMC2_PCR_BCHECC;
 221         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 222                 pcr |= FMC2_PCR_ECCALG;
 223         }
 224
 225         /* Set buswidth */
 226         pcr_mask |= FMC2_PCR_PWID;
 227         if (chip->options & NAND_BUSWIDTH_16)
 228                 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
 229
 230         /* Set ECC sector size */
 231         pcr_mask |= FMC2_PCR_ECCSS;
 232         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
 233
 234         clrsetbits_le32(nfc->io_base + FMC2_PCR, pcr_mask, pcr);
 235 }
 236
 237 static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr)
 238 {
 239         struct nand_chip *chip = mtd_to_nand(mtd);
 240         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 241         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 242
 243         if (chipnr < 0 || chipnr >= nand->ncs)
 244                 return;
 245
 246         if (nand->cs_used[chipnr] == nfc->cs_sel)
 247                 return;
 248
 249         nfc->cs_sel = nand->cs_used[chipnr];
 250         chip->IO_ADDR_R = (void __iomem *)nfc->data_base[nfc->cs_sel];
 251         chip->IO_ADDR_W = (void __iomem *)nfc->data_base[nfc->cs_sel];
 252
 253         stm32_fmc2_nfc_setup(chip);
 254         stm32_fmc2_nfc_timings_init(chip);
 255 }
 256
 257 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc,
 258                                            bool set)
 259 {
 260         u32 pcr;
 261
 262         pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
 263                     FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
 264
 265         clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_PWID, pcr);
 266 }
 267
 268 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
 269 {
 270         clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_ECCEN,
 271                         enable ? FMC2_PCR_ECCEN : 0);
 272 }
 273
 274 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
 275 {
 276         writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
 277 }
 278
 279 static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd,
 280                                     unsigned int ctrl)
 281 {
 282         struct nand_chip *chip = mtd_to_nand(mtd);
 283         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 284
 285         if (cmd == NAND_CMD_NONE)
 286                 return;
 287
 288         if (ctrl & NAND_CLE) {
 289                 writeb(cmd, nfc->cmd_base[nfc->cs_sel]);
 290                 return;
 291         }
 292
 293         writeb(cmd, nfc->addr_base[nfc->cs_sel]);
 294 }
 295
 296 /*
 297  * Enable ECC logic and reset syndrome/parity bits previously calculated
 298  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 299  */
 300 static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode)
 301 {
 302         struct nand_chip *chip = mtd_to_nand(mtd);
 303         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 304
 305         stm32_fmc2_nfc_set_ecc(nfc, false);
 306
 307         if (chip->ecc.strength != FMC2_ECC_HAM) {
 308                 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_WEN,
 309                                 mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
 310
 311                 stm32_fmc2_nfc_clear_bch_irq(nfc);
 312         }
 313
 314         stm32_fmc2_nfc_set_ecc(nfc, true);
 315 }
 316
 317 /*
 318  * ECC Hamming calculation
 319  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 320  * max of 1-bit)
 321  */
 322 static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data,
 323                                         u8 *ecc)
 324 {
 325         struct nand_chip *chip = mtd_to_nand(mtd);
 326         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 327         u32 heccr, sr;
 328         int ret;
 329
 330         ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
 331                                  sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
 332         if (ret < 0) {
 333                 log_err("Ham timeout\n");
 334                 return ret;
 335         }
 336
 337         heccr = readl(nfc->io_base + FMC2_HECCR);
 338
 339         ecc[0] = heccr;
 340         ecc[1] = heccr >> 8;
 341         ecc[2] = heccr >> 16;
 342
 343         stm32_fmc2_nfc_set_ecc(nfc, false);
 344
 345         return 0;
 346 }
 347
 348 static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat,
 349                                       u8 *read_ecc, u8 *calc_ecc)
 350 {
 351         u8 bit_position = 0, b0, b1, b2;
 352         u32 byte_addr = 0, b;
 353         u32 i, shifting = 1;
 354
 355         /* Indicate which bit and byte is faulty (if any) */
 356         b0 = read_ecc[0] ^ calc_ecc[0];
 357         b1 = read_ecc[1] ^ calc_ecc[1];
 358         b2 = read_ecc[2] ^ calc_ecc[2];
 359         b = b0 | (b1 << 8) | (b2 << 16);
 360
 361         /* No errors */
 362         if (likely(!b))
 363                 return 0;
 364
 365         /* Calculate bit position */
 366         for (i = 0; i < 3; i++) {
 367                 switch (b % 4) {
 368                 case 2:
 369                         bit_position += shifting;
 370                 case 1:
 371                         break;
 372                 default:
 373                         return -EBADMSG;
 374                 }
 375                 shifting <<= 1;
 376                 b >>= 2;
 377         }
 378
 379         /* Calculate byte position */
 380         shifting = 1;
 381         for (i = 0; i < 9; i++) {
 382                 switch (b % 4) {
 383                 case 2:
 384                         byte_addr += shifting;
 385                 case 1:
 386                         break;
 387                 default:
 388                         return -EBADMSG;
 389                 }
 390                 shifting <<= 1;
 391                 b >>= 2;
 392         }
 393
 394         /* Flip the bit */
 395         dat[byte_addr] ^= (1 << bit_position);
 396
 397         return 1;
 398 }
 399
 400 /*
 401  * ECC BCH calculation and correction
 402  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 403  * max of 4-bit/8-bit)
 404  */
 405
 406 static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data,
 407                                         u8 *ecc)
 408 {
 409         struct nand_chip *chip = mtd_to_nand(mtd);
 410         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 411         u32 bchpbr, bchisr;
 412         int ret;
 413
 414         /* Wait until the BCH code is ready */
 415         ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
 416                                  bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
 417         if (ret < 0) {
 418                 log_err("Bch timeout\n");
 419                 return ret;
 420         }
 421
 422         /* Read parity bits */
 423         bchpbr = readl(nfc->io_base + FMC2_BCHPBR1);
 424         ecc[0] = bchpbr;
 425         ecc[1] = bchpbr >> 8;
 426         ecc[2] = bchpbr >> 16;
 427         ecc[3] = bchpbr >> 24;
 428
 429         bchpbr = readl(nfc->io_base + FMC2_BCHPBR2);
 430         ecc[4] = bchpbr;
 431         ecc[5] = bchpbr >> 8;
 432         ecc[6] = bchpbr >> 16;
 433
 434         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 435                 ecc[7] = bchpbr >> 24;
 436
 437                 bchpbr = readl(nfc->io_base + FMC2_BCHPBR3);
 438                 ecc[8] = bchpbr;
 439                 ecc[9] = bchpbr >> 8;
 440                 ecc[10] = bchpbr >> 16;
 441                 ecc[11] = bchpbr >> 24;
 442
 443                 bchpbr = readl(nfc->io_base + FMC2_BCHPBR4);
 444                 ecc[12] = bchpbr;
 445         }
 446
 447         stm32_fmc2_nfc_set_ecc(nfc, false);
 448
 449         return 0;
 450 }
 451
 452 static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat,
 453                                       u8 *read_ecc, u8 *calc_ecc)
 454 {
 455         struct nand_chip *chip = mtd_to_nand(mtd);
 456         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 457         u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
 458         u16 pos[8];
 459         int i, ret, den, eccsize = chip->ecc.size;
 460         unsigned int nb_errs = 0;
 461
 462         /* Wait until the decoding error is ready */
 463         ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
 464                                  bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
 465         if (ret < 0) {
 466                 log_err("Bch timeout\n");
 467                 return ret;
 468         }
 469
 470         bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0);
 471         bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1);
 472         bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2);
 473         bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3);
 474         bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4);
 475
 476         stm32_fmc2_nfc_set_ecc(nfc, false);
 477
 478         /* No errors found */
 479         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 480                 return 0;
 481
 482         /* Too many errors detected */
 483         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 484                 return -EBADMSG;
 485
 486         pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
 487         pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
 488         pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
 489         pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
 490         pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
 491         pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
 492         pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
 493         pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
 494
 495         den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
 496         for (i = 0; i < den; i++) {
 497                 if (pos[i] < eccsize * 8) {
 498                         __change_bit(pos[i], (unsigned long *)dat);
 499                         nb_errs++;
 500                 }
 501         }
 502
 503         return nb_errs;
 504 }
 505
 506 static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd,
 507                                     struct nand_chip *chip, u8 *buf,
 508                                     int oob_required, int page)
 509 {
 510         int i, s, stat, eccsize = chip->ecc.size;
 511         int eccbytes = chip->ecc.bytes;
 512         int eccsteps = chip->ecc.steps;
 513         int eccstrength = chip->ecc.strength;
 514         u8 *p = buf;
 515         u8 *ecc_calc = chip->buffers->ecccalc;
 516         u8 *ecc_code = chip->buffers->ecccode;
 517         unsigned int max_bitflips = 0;
 518
 519         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 520              s++, i += eccbytes, p += eccsize) {
 521                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 522
 523                 /* Read the nand page sector (512 bytes) */
 524                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
 525                 chip->read_buf(mtd, p, eccsize);
 526
 527                 /* Read the corresponding ECC bytes */
 528                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
 529                 chip->read_buf(mtd, ecc_code, eccbytes);
 530
 531                 /* Correct the data */
 532                 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
 533                 if (stat == -EBADMSG)
 534                         /* Check for empty pages with bitflips */
 535                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 536                                                            ecc_code, eccbytes,
 537                                                            NULL, 0,
 538                                                            eccstrength);
 539
 540                 if (stat < 0) {
 541                         mtd->ecc_stats.failed++;
 542                 } else {
 543                         mtd->ecc_stats.corrected += stat;
 544                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 545                 }
 546         }
 547
 548         /* Read oob */
 549         if (oob_required) {
 550                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 551                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 552         }
 553
 554         return max_bitflips;
 555 }
 556
 557 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc, bool has_parent)
 558 {
 559         u32 pcr = readl(nfc->io_base + FMC2_PCR);
 560
 561         /* Set CS used to undefined */
 562         nfc->cs_sel = -1;
 563
 564         /* Enable wait feature and nand flash memory bank */
 565         pcr |= FMC2_PCR_PWAITEN;
 566         pcr |= FMC2_PCR_PBKEN;
 567
 568         /* Set buswidth to 8 bits mode for identification */
 569         pcr &= ~FMC2_PCR_PWID;
 570
 571         /* ECC logic is disabled */
 572         pcr &= ~FMC2_PCR_ECCEN;
 573
 574         /* Default mode */
 575         pcr &= ~FMC2_PCR_ECCALG;
 576         pcr &= ~FMC2_PCR_BCHECC;
 577         pcr &= ~FMC2_PCR_WEN;
 578
 579         /* Set default ECC sector size */
 580         pcr &= ~FMC2_PCR_ECCSS;
 581         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
 582
 583         /* Set default tclr/tar timings */
 584         pcr &= ~FMC2_PCR_TCLR;
 585         pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
 586         pcr &= ~FMC2_PCR_TAR;
 587         pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
 588
 589         /* Enable FMC2 controller */
 590         if (!has_parent)
 591                 setbits_le32(nfc->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
 592
 593         writel(pcr, nfc->io_base + FMC2_PCR);
 594         writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
 595         writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
 596 }
 597
 598 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
 599                                         const struct nand_sdr_timings *sdrt)
 600 {
 601         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 602         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 603         struct stm32_fmc2_timings *tims = &nand->timings;
 604         unsigned long hclk = clk_get_rate(&nfc->clk);
 605         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 606         unsigned long timing, tar, tclr, thiz, twait;
 607         unsigned long tset_mem, tset_att, thold_mem, thold_att;
 608
 609         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
 610         timing = DIV_ROUND_UP(tar, hclkp) - 1;
 611         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 612
 613         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
 614         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
 615         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 616
 617         tims->thiz = FMC2_THIZ;
 618         thiz = (tims->thiz + 1) * hclkp;
 619
 620         /*
 621          * tWAIT > tRP
 622          * tWAIT > tWP
 623          * tWAIT > tREA + tIO
 624          */
 625         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
 626         twait = max_t(unsigned long, twait, sdrt->tWP_min);
 627         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
 628         timing = DIV_ROUND_UP(twait, hclkp);
 629         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 630
 631         /*
 632          * tSETUP_MEM > tCS - tWAIT
 633          * tSETUP_MEM > tALS - tWAIT
 634          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
 635          */
 636         tset_mem = hclkp;
 637         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
 638                 tset_mem = sdrt->tCS_min - twait;
 639         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
 640                 tset_mem = sdrt->tALS_min - twait;
 641         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 642             (tset_mem < sdrt->tDS_min - (twait - thiz)))
 643                 tset_mem = sdrt->tDS_min - (twait - thiz);
 644         timing = DIV_ROUND_UP(tset_mem, hclkp);
 645         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 646
 647         /*
 648          * tHOLD_MEM > tCH
 649          * tHOLD_MEM > tREH - tSETUP_MEM
 650          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
 651          */
 652         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
 653         if (sdrt->tREH_min > tset_mem &&
 654             (thold_mem < sdrt->tREH_min - tset_mem))
 655                 thold_mem = sdrt->tREH_min - tset_mem;
 656         if ((sdrt->tRC_min > tset_mem + twait) &&
 657             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
 658                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
 659         if ((sdrt->tWC_min > tset_mem + twait) &&
 660             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
 661                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
 662         timing = DIV_ROUND_UP(thold_mem, hclkp);
 663         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 664
 665         /*
 666          * tSETUP_ATT > tCS - tWAIT
 667          * tSETUP_ATT > tCLS - tWAIT
 668          * tSETUP_ATT > tALS - tWAIT
 669          * tSETUP_ATT > tRHW - tHOLD_MEM
 670          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
 671          */
 672         tset_att = hclkp;
 673         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
 674                 tset_att = sdrt->tCS_min - twait;
 675         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
 676                 tset_att = sdrt->tCLS_min - twait;
 677         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
 678                 tset_att = sdrt->tALS_min - twait;
 679         if (sdrt->tRHW_min > thold_mem &&
 680             (tset_att < sdrt->tRHW_min - thold_mem))
 681                 tset_att = sdrt->tRHW_min - thold_mem;
 682         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 683             (tset_att < sdrt->tDS_min - (twait - thiz)))
 684                 tset_att = sdrt->tDS_min - (twait - thiz);
 685         timing = DIV_ROUND_UP(tset_att, hclkp);
 686         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 687
 688         /*
 689          * tHOLD_ATT > tALH
 690          * tHOLD_ATT > tCH
 691          * tHOLD_ATT > tCLH
 692          * tHOLD_ATT > tCOH
 693          * tHOLD_ATT > tDH
 694          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
 695          * tHOLD_ATT > tADL - tSETUP_MEM
 696          * tHOLD_ATT > tWH - tSETUP_MEM
 697          * tHOLD_ATT > tWHR - tSETUP_MEM
 698          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
 699          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
 700          */
 701         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
 702         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
 703         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
 704         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
 705         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
 706         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
 707             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
 708                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
 709         if (sdrt->tADL_min > tset_mem &&
 710             (thold_att < sdrt->tADL_min - tset_mem))
 711                 thold_att = sdrt->tADL_min - tset_mem;
 712         if (sdrt->tWH_min > tset_mem &&
 713             (thold_att < sdrt->tWH_min - tset_mem))
 714                 thold_att = sdrt->tWH_min - tset_mem;
 715         if (sdrt->tWHR_min > tset_mem &&
 716             (thold_att < sdrt->tWHR_min - tset_mem))
 717                 thold_att = sdrt->tWHR_min - tset_mem;
 718         if ((sdrt->tRC_min > tset_att + twait) &&
 719             (thold_att < sdrt->tRC_min - (tset_att + twait)))
 720                 thold_att = sdrt->tRC_min - (tset_att + twait);
 721         if ((sdrt->tWC_min > tset_att + twait) &&
 722             (thold_att < sdrt->tWC_min - (tset_att + twait)))
 723                 thold_att = sdrt->tWC_min - (tset_att + twait);
 724         timing = DIV_ROUND_UP(thold_att, hclkp);
 725         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 726 }
 727
 728 static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr,
 729                                           const struct nand_data_interface *cf)
 730 {
 731         struct nand_chip *chip = mtd_to_nand(mtd);
 732         const struct nand_sdr_timings *sdrt;
 733
 734         sdrt = nand_get_sdr_timings(cf);
 735         if (IS_ERR(sdrt))
 736                 return PTR_ERR(sdrt);
 737
 738         if (sdrt->tRC_min < 30000)
 739                 return -EOPNOTSUPP;
 740
 741         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
 742                 return 0;
 743
 744         stm32_fmc2_nfc_calc_timings(chip, sdrt);
 745         stm32_fmc2_nfc_timings_init(chip);
 746
 747         return 0;
 748 }
 749
 750 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
 751 {
 752         chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
 753
 754         /*
 755          * Specific callbacks to read/write a page depending on
 756          * the algo used (Hamming, BCH).
 757          */
 758         if (chip->ecc.strength == FMC2_ECC_HAM) {
 759                 /* Hamming is used */
 760                 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
 761                 chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
 762                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
 763                 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
 764                 return;
 765         }
 766
 767         /* BCH is used */
 768         chip->ecc.read_page = stm32_fmc2_nfc_read_page;
 769         chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
 770         chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
 771
 772         if (chip->ecc.strength == FMC2_ECC_BCH8)
 773                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
 774         else
 775                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
 776 }
 777
 778 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
 779 {
 780         /* Hamming */
 781         if (strength == FMC2_ECC_HAM)
 782                 return 4;
 783
 784         /* BCH8 */
 785         if (strength == FMC2_ECC_BCH8)
 786                 return 14;
 787
 788         /* BCH4 */
 789         return 8;
 790 }
 791
 792 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
 793                      FMC2_ECC_STEP_SIZE,
 794                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
 795
 796 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node)
 797 {
 798         struct stm32_fmc2_nand *nand = &nfc->nand;
 799         u32 cs[FMC2_MAX_CE];
 800         int ret, i;
 801
 802         if (!ofnode_get_property(node, "reg", &nand->ncs))
 803                 return -EINVAL;
 804
 805         nand->ncs /= sizeof(u32);
 806         if (!nand->ncs) {
 807                 log_err("Invalid reg property size\n");
 808                 return -EINVAL;
 809         }
 810
 811         ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
 812         if (ret < 0) {
 813                 log_err("Could not retrieve reg property\n");
 814                 return -EINVAL;
 815         }
 816
 817         for (i = 0; i < nand->ncs; i++) {
 818                 if (cs[i] >= FMC2_MAX_CE) {
 819                         log_err("Invalid reg value: %d\n", nand->cs_used[i]);
 820                         return -EINVAL;
 821                 }
 822
 823                 if (nfc->cs_assigned & BIT(cs[i])) {
 824                         log_err("Cs already assigned: %d\n", nand->cs_used[i]);
 825                         return -EINVAL;
 826                 }
 827
 828                 nfc->cs_assigned |= BIT(cs[i]);
 829                 nand->cs_used[i] = cs[i];
 830         }
 831
 832         gpio_request_by_name_nodev(node, "wp-gpios", 0, &nand->wp_gpio,
 833                                    GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 834
 835         nand->chip.flash_node = node;
 836
 837         return 0;
 838 }
 839
 840 static int stm32_fmc2_nfc_parse_dt(struct udevice *dev,
 841                                    struct stm32_fmc2_nfc *nfc)
 842 {
 843         ofnode child;
 844         int ret, nchips = 0;
 845
 846         dev_for_each_subnode(child, dev)
 847                 nchips++;
 848
 849         if (!nchips) {
 850                 log_err("NAND chip not defined\n");
 851                 return -EINVAL;
 852         }
 853
 854         if (nchips > 1) {
 855                 log_err("Too many NAND chips defined\n");
 856                 return -EINVAL;
 857         }
 858
 859         dev_for_each_subnode(child, dev) {
 860                 ret = stm32_fmc2_nfc_parse_child(nfc, child);
 861                 if (ret)
 862                         return ret;
 863         }
 864
 865         return 0;
 866 }
 867
 868 static struct udevice *stm32_fmc2_nfc_get_cdev(struct udevice *dev)
 869 {
 870         struct udevice *pdev = dev_get_parent(dev);
 871         struct udevice *cdev = NULL;
 872         bool ebi_found = false;
 873
 874         if (pdev && ofnode_device_is_compatible(dev_ofnode(pdev),
 875                                                 "st,stm32mp1-fmc2-ebi"))
 876                 ebi_found = true;
 877
 878         if (ofnode_device_is_compatible(dev_ofnode(dev),
 879                                         "st,stm32mp1-fmc2-nfc")) {
 880                 if (ebi_found)
 881                         cdev = pdev;
 882
 883                 return cdev;
 884         }
 885
 886         if (!ebi_found)
 887                 cdev = dev;
 888
 889         return cdev;
 890 }
 891
 892 static int stm32_fmc2_nfc_probe(struct udevice *dev)
 893 {
 894         struct stm32_fmc2_nfc *nfc = dev_get_priv(dev);
 895         struct stm32_fmc2_nand *nand = &nfc->nand;
 896         struct nand_chip *chip = &nand->chip;
 897         struct mtd_info *mtd = &chip->mtd;
 898         struct nand_ecclayout *ecclayout;
 899         struct udevice *cdev;
 900         struct reset_ctl reset;
 901         int oob_index, chip_cs, mem_region, ret;
 902         unsigned int i;
 903         int start_region = 0;
 904         fdt_addr_t addr;
 905
 906         spin_lock_init(&nfc->controller.lock);
 907         init_waitqueue_head(&nfc->controller.wq);
 908
 909         cdev = stm32_fmc2_nfc_get_cdev(dev);
 910         if (!cdev)
 911                 return -EINVAL;
 912
 913         ret = stm32_fmc2_nfc_parse_dt(dev, nfc);
 914         if (ret)
 915                 return ret;
 916
 917         nfc->io_base = dev_read_addr(cdev);
 918         if (nfc->io_base == FDT_ADDR_T_NONE)
 919                 return -EINVAL;
 920
 921         if (dev == cdev)
 922                 start_region = 1;
 923
 924         for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
 925              chip_cs++, mem_region += 3) {
 926                 if (!(nfc->cs_assigned & BIT(chip_cs)))
 927                         continue;
 928
 929                 addr = dev_read_addr_index(dev, mem_region);
 930                 if (addr == FDT_ADDR_T_NONE) {
 931                         dev_err(dev, "Resource data_base not found for cs%d", chip_cs);
 932                         return ret;
 933                 }
 934                 nfc->data_base[chip_cs] = addr;
 935
 936                 addr = dev_read_addr_index(dev, mem_region + 1);
 937                 if (addr == FDT_ADDR_T_NONE) {
 938                         dev_err(dev, "Resource cmd_base not found for cs%d", chip_cs);
 939                         return ret;
 940                 }
 941                 nfc->cmd_base[chip_cs] = addr;
 942
 943                 addr = dev_read_addr_index(dev, mem_region + 2);
 944                 if (addr == FDT_ADDR_T_NONE) {
 945                         dev_err(dev, "Resource addr_base not found for cs%d", chip_cs);
 946                         return ret;
 947                 }
 948                 nfc->addr_base[chip_cs] = addr;
 949         }
 950
 951         /* Enable the clock */
 952         ret = clk_get_by_index(cdev, 0, &nfc->clk);
 953         if (ret)
 954                 return ret;
 955
 956         ret = clk_enable(&nfc->clk);
 957         if (ret)
 958                 return ret;
 959
 960         /* Reset */
 961         ret = reset_get_by_index(dev, 0, &reset);
 962         if (!ret) {
 963                 reset_assert(&reset);
 964                 udelay(2);
 965                 reset_deassert(&reset);
 966         }
 967
 968         stm32_fmc2_nfc_init(nfc, dev != cdev);
 969
 970         chip->controller = &nfc->base;
 971         chip->select_chip = stm32_fmc2_nfc_select_chip;
 972         chip->setup_data_interface = stm32_fmc2_nfc_setup_interface;
 973         chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl;
 974         chip->chip_delay = FMC2_RB_DELAY_US;
 975         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
 976                          NAND_USE_BOUNCE_BUFFER;
 977
 978         /* Default ECC settings */
 979         chip->ecc.mode = NAND_ECC_HW;
 980         chip->ecc.size = FMC2_ECC_STEP_SIZE;
 981         chip->ecc.strength = FMC2_ECC_BCH8;
 982
 983         /* Disable Write Protect */
 984         if (dm_gpio_is_valid(&nand->wp_gpio))
 985                 dm_gpio_set_value(&nand->wp_gpio, 0);
 986
 987         ret = nand_scan_ident(mtd, nand->ncs, NULL);
 988         if (ret)
 989                 return ret;
 990
 991         /*
 992          * Only NAND_ECC_HW mode is actually supported
 993          * Hamming => ecc.strength = 1
 994          * BCH4 => ecc.strength = 4
 995          * BCH8 => ecc.strength = 8
 996          * ECC sector size = 512
 997          */
 998         if (chip->ecc.mode != NAND_ECC_HW) {
 999                 dev_err(dev, "Nand_ecc_mode is not well defined in the DT\n");
1000                 return -EINVAL;
1001         }
1002
1003         ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
1004                                   mtd->oobsize - FMC2_BBM_LEN);
1005         if (ret) {
1006                 dev_err(dev, "No valid ECC settings set\n");
1007                 return ret;
1008         }
1009
1010         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1011                 chip->bbt_options |= NAND_BBT_NO_OOB;
1012
1013         stm32_fmc2_nfc_nand_callbacks_setup(chip);
1014
1015         /* Define ECC layout */
1016         ecclayout = &nfc->ecclayout;
1017         ecclayout->eccbytes = chip->ecc.bytes *
1018                               (mtd->writesize / chip->ecc.size);
1019         oob_index = FMC2_BBM_LEN;
1020         for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1021                 ecclayout->eccpos[i] = oob_index;
1022         ecclayout->oobfree->offset = oob_index;
1023         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1024         chip->ecc.layout = ecclayout;
1025
1026         if (chip->options & NAND_BUSWIDTH_16)
1027                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1028
1029         ret = nand_scan_tail(mtd);
1030         if (ret)
1031                 return ret;
1032
1033         return nand_register(0, mtd);
1034 }
1035
1036 static const struct udevice_id stm32_fmc2_nfc_match[] = {
1037         { .compatible = "st,stm32mp15-fmc2" },
1038         { .compatible = "st,stm32mp1-fmc2-nfc" },
1039         { /* Sentinel */ }
1040 };
1041
1042 U_BOOT_DRIVER(stm32_fmc2_nfc) = {
1043         .name = "stm32_fmc2_nfc",
1044         .id = UCLASS_MTD,
1045         .of_match = stm32_fmc2_nfc_match,
1046         .probe = stm32_fmc2_nfc_probe,
1047         .priv_auto      = sizeof(struct stm32_fmc2_nfc),
1048 };
1049
1050 void board_nand_init(void)
1051 {
1052         struct udevice *dev;
1053         int ret;
1054
1055         ret = uclass_get_device_by_driver(UCLASS_MTD,
1056                                           DM_DRIVER_GET(stm32_fmc2_nfc),
1057                                           &dev);
1058         if (ret && ret != -ENODEV)
1059                 log_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
1060                         ret);
1061 }