1 // SPDX-License-Identifier: GPL-2.0-only
3 * MTK NAND Flash controller driver.
4 * Copyright (C) 2016 MediaTek Inc.
5 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
9 #include <linux/platform_device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/delay.h>
13 #include <linux/clk.h>
14 #include <linux/mtd/rawnand.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/module.h>
17 #include <linux/iopoll.h>
19 #include <linux/of_device.h>
22 /* NAND controller register definition */
23 #define NFI_CNFG (0x00)
24 #define CNFG_AHB BIT(0)
25 #define CNFG_READ_EN BIT(1)
26 #define CNFG_DMA_BURST_EN BIT(2)
27 #define CNFG_BYTE_RW BIT(6)
28 #define CNFG_HW_ECC_EN BIT(8)
29 #define CNFG_AUTO_FMT_EN BIT(9)
30 #define CNFG_OP_CUST (6 << 12)
31 #define NFI_PAGEFMT (0x04)
32 #define PAGEFMT_FDM_ECC_SHIFT (12)
33 #define PAGEFMT_FDM_SHIFT (8)
34 #define PAGEFMT_SEC_SEL_512 BIT(2)
35 #define PAGEFMT_512_2K (0)
36 #define PAGEFMT_2K_4K (1)
37 #define PAGEFMT_4K_8K (2)
38 #define PAGEFMT_8K_16K (3)
40 #define NFI_CON (0x08)
41 #define CON_FIFO_FLUSH BIT(0)
42 #define CON_NFI_RST BIT(1)
43 #define CON_BRD BIT(8) /* burst read */
44 #define CON_BWR BIT(9) /* burst write */
45 #define CON_SEC_SHIFT (12)
46 /* Timming control register */
47 #define NFI_ACCCON (0x0C)
48 #define NFI_INTR_EN (0x10)
49 #define INTR_AHB_DONE_EN BIT(6)
50 #define NFI_INTR_STA (0x14)
51 #define NFI_CMD (0x20)
52 #define NFI_ADDRNOB (0x30)
53 #define NFI_COLADDR (0x34)
54 #define NFI_ROWADDR (0x38)
55 #define NFI_STRDATA (0x40)
58 #define NFI_CNRNB (0x44)
59 #define NFI_DATAW (0x50)
60 #define NFI_DATAR (0x54)
61 #define NFI_PIO_DIRDY (0x58)
62 #define PIO_DI_RDY (0x01)
63 #define NFI_STA (0x60)
64 #define STA_CMD BIT(0)
65 #define STA_ADDR BIT(1)
66 #define STA_BUSY BIT(8)
67 #define STA_EMP_PAGE BIT(12)
68 #define NFI_FSM_CUSTDATA (0xe << 16)
69 #define NFI_FSM_MASK (0xf << 16)
70 #define NFI_ADDRCNTR (0x70)
71 #define CNTR_MASK GENMASK(16, 12)
72 #define ADDRCNTR_SEC_SHIFT (12)
73 #define ADDRCNTR_SEC(val) \
74 (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT)
75 #define NFI_STRADDR (0x80)
76 #define NFI_BYTELEN (0x84)
77 #define NFI_CSEL (0x90)
78 #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2)
79 #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2)
80 #define NFI_FDM_MAX_SIZE (8)
81 #define NFI_FDM_MIN_SIZE (1)
82 #define NFI_MASTER_STA (0x224)
83 #define MASTER_STA_MASK (0x0FFF)
84 #define NFI_EMPTY_THRESH (0x23C)
86 #define MTK_NAME "mtk-nand"
87 #define KB(x) ((x) * 1024UL)
88 #define MB(x) (KB(x) * 1024UL)
90 #define MTK_TIMEOUT (500000)
91 #define MTK_RESET_TIMEOUT (1000000)
92 #define MTK_NAND_MAX_NSELS (2)
93 #define MTK_NFC_MIN_SPARE (16)
94 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
95 ((tpoecs) << 28 | (tprecs) << 22 | (tc2r) << 16 | \
96 (tw2r) << 12 | (twh) << 8 | (twst) << 4 | (trlt))
101 u8 pageformat_spare_shift;
107 struct mtk_nfc_bad_mark_ctl {
108 void (*bm_swap)(struct mtd_info *, u8 *buf, int raw);
114 * FDM: region used to store free OOB data
121 struct mtk_nfc_nand_chip {
122 struct list_head node;
123 struct nand_chip nand;
125 struct mtk_nfc_bad_mark_ctl bad_mark;
126 struct mtk_nfc_fdm fdm;
127 u32 spare_per_sector;
131 /* nothing after this field */
140 struct nand_controller controller;
141 struct mtk_ecc_config ecc_cfg;
142 struct mtk_nfc_clk clk;
146 const struct mtk_nfc_caps *caps;
149 struct completion done;
150 struct list_head chips;
156 * supported spare size of each IP.
157 * order should be the same with the spare size bitfiled defination of
158 * register NFI_PAGEFMT.
160 static const u8 spare_size_mt2701[] = {
161 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 63, 64
164 static const u8 spare_size_mt2712[] = {
165 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67,
169 static const u8 spare_size_mt7622[] = {
173 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
175 return container_of(nand, struct mtk_nfc_nand_chip, nand);
178 static inline u8 *data_ptr(struct nand_chip *chip, const u8 *p, int i)
180 return (u8 *)p + i * chip->ecc.size;
183 static inline u8 *oob_ptr(struct nand_chip *chip, int i)
185 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
188 /* map the sector's FDM data to free oob:
189 * the beginning of the oob area stores the FDM data of bad mark sectors
192 if (i < mtk_nand->bad_mark.sec)
193 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size;
194 else if (i == mtk_nand->bad_mark.sec)
197 poi = chip->oob_poi + i * mtk_nand->fdm.reg_size;
202 static inline int mtk_data_len(struct nand_chip *chip)
204 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
206 return chip->ecc.size + mtk_nand->spare_per_sector;
209 static inline u8 *mtk_data_ptr(struct nand_chip *chip, int i)
211 struct mtk_nfc *nfc = nand_get_controller_data(chip);
213 return nfc->buffer + i * mtk_data_len(chip);
216 static inline u8 *mtk_oob_ptr(struct nand_chip *chip, int i)
218 struct mtk_nfc *nfc = nand_get_controller_data(chip);
220 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size;
223 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg)
225 writel(val, nfc->regs + reg);
228 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg)
230 writew(val, nfc->regs + reg);
233 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg)
235 writeb(val, nfc->regs + reg);
238 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg)
240 return readl_relaxed(nfc->regs + reg);
243 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg)
245 return readw_relaxed(nfc->regs + reg);
248 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
250 return readb_relaxed(nfc->regs + reg);
253 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
255 struct device *dev = nfc->dev;
259 /* reset all registers and force the NFI master to terminate */
260 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
262 /* wait for the master to finish the last transaction */
263 ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val,
264 !(val & MASTER_STA_MASK), 50,
267 dev_warn(dev, "master active in reset [0x%x] = 0x%x\n",
268 NFI_MASTER_STA, val);
270 /* ensure any status register affected by the NFI master is reset */
271 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
272 nfi_writew(nfc, STAR_DE, NFI_STRDATA);
275 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command)
277 struct device *dev = nfc->dev;
281 nfi_writel(nfc, command, NFI_CMD);
283 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
284 !(val & STA_CMD), 10, MTK_TIMEOUT);
286 dev_warn(dev, "nfi core timed out entering command mode\n");
293 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr)
295 struct device *dev = nfc->dev;
299 nfi_writel(nfc, addr, NFI_COLADDR);
300 nfi_writel(nfc, 0, NFI_ROWADDR);
301 nfi_writew(nfc, 1, NFI_ADDRNOB);
303 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
304 !(val & STA_ADDR), 10, MTK_TIMEOUT);
306 dev_warn(dev, "nfi core timed out entering address mode\n");
313 static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
315 struct nand_chip *chip = mtd_to_nand(mtd);
316 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
317 struct mtk_nfc *nfc = nand_get_controller_data(chip);
323 spare = mtk_nand->spare_per_sector;
325 switch (mtd->writesize) {
327 fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512;
330 if (chip->ecc.size == 512)
331 fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512;
333 fmt = PAGEFMT_512_2K;
336 if (chip->ecc.size == 512)
337 fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512;
342 if (chip->ecc.size == 512)
343 fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512;
348 fmt = PAGEFMT_8K_16K;
351 dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize);
356 * the hardware will double the value for this eccsize, so we need to
359 if (chip->ecc.size == 1024)
362 for (i = 0; i < nfc->caps->num_spare_size; i++) {
363 if (nfc->caps->spare_size[i] == spare)
367 if (i == nfc->caps->num_spare_size) {
368 dev_err(nfc->dev, "invalid spare size %d\n", spare);
372 fmt |= i << nfc->caps->pageformat_spare_shift;
374 fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT;
375 fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT;
376 nfi_writel(nfc, fmt, NFI_PAGEFMT);
378 nfc->ecc_cfg.strength = chip->ecc.strength;
379 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size;
384 static void mtk_nfc_select_chip(struct nand_chip *nand, int chip)
386 struct mtk_nfc *nfc = nand_get_controller_data(nand);
387 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand);
392 mtk_nfc_hw_runtime_config(nand_to_mtd(nand));
394 nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL);
397 static int mtk_nfc_dev_ready(struct nand_chip *nand)
399 struct mtk_nfc *nfc = nand_get_controller_data(nand);
401 if (nfi_readl(nfc, NFI_STA) & STA_BUSY)
407 static void mtk_nfc_cmd_ctrl(struct nand_chip *chip, int dat,
410 struct mtk_nfc *nfc = nand_get_controller_data(chip);
412 if (ctrl & NAND_ALE) {
413 mtk_nfc_send_address(nfc, dat);
414 } else if (ctrl & NAND_CLE) {
415 mtk_nfc_hw_reset(nfc);
417 nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
418 mtk_nfc_send_command(nfc, dat);
422 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
427 rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val,
428 val & PIO_DI_RDY, 10, MTK_TIMEOUT);
430 dev_err(nfc->dev, "data not ready\n");
433 static inline u8 mtk_nfc_read_byte(struct nand_chip *chip)
435 struct mtk_nfc *nfc = nand_get_controller_data(chip);
438 /* after each byte read, the NFI_STA reg is reset by the hardware */
439 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
440 if (reg != NFI_FSM_CUSTDATA) {
441 reg = nfi_readw(nfc, NFI_CNFG);
442 reg |= CNFG_BYTE_RW | CNFG_READ_EN;
443 nfi_writew(nfc, reg, NFI_CNFG);
446 * set to max sector to allow the HW to continue reading over
449 reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
450 nfi_writel(nfc, reg, NFI_CON);
452 /* trigger to fetch data */
453 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
456 mtk_nfc_wait_ioready(nfc);
458 return nfi_readb(nfc, NFI_DATAR);
461 static void mtk_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len)
465 for (i = 0; i < len; i++)
466 buf[i] = mtk_nfc_read_byte(chip);
469 static void mtk_nfc_write_byte(struct nand_chip *chip, u8 byte)
471 struct mtk_nfc *nfc = nand_get_controller_data(chip);
474 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
476 if (reg != NFI_FSM_CUSTDATA) {
477 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
478 nfi_writew(nfc, reg, NFI_CNFG);
480 reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
481 nfi_writel(nfc, reg, NFI_CON);
483 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
486 mtk_nfc_wait_ioready(nfc);
487 nfi_writeb(nfc, byte, NFI_DATAW);
490 static void mtk_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
494 for (i = 0; i < len; i++)
495 mtk_nfc_write_byte(chip, buf[i]);
498 static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
499 const struct nand_data_interface *conf)
501 struct mtk_nfc *nfc = nand_get_controller_data(chip);
502 const struct nand_sdr_timings *timings;
503 u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;
505 timings = nand_get_sdr_timings(conf);
509 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
512 rate = clk_get_rate(nfc->clk.nfi_clk);
513 /* There is a frequency divider in some IPs */
514 rate /= nfc->caps->nfi_clk_div;
516 /* turn clock rate into KHZ */
519 tpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000;
520 tpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000);
523 tprecs = max(timings->tCLS_min, timings->tALS_min) / 1000;
524 tprecs = DIV_ROUND_UP(tprecs * rate, 1000000);
527 /* sdr interface has no tCR which means CE# low to RE# low */
530 tw2r = timings->tWHR_min / 1000;
531 tw2r = DIV_ROUND_UP(tw2r * rate, 1000000);
532 tw2r = DIV_ROUND_UP(tw2r - 1, 2);
535 twh = max(timings->tREH_min, timings->tWH_min) / 1000;
536 twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
539 twst = timings->tWP_min / 1000;
540 twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
543 trlt = max(timings->tREA_max, timings->tRP_min) / 1000;
544 trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
548 * ACCON: access timing control register
549 * -------------------------------------
550 * 31:28: tpoecs, minimum required time for CS post pulling down after
551 * accessing the device
552 * 27:22: tprecs, minimum required time for CS pre pulling down before
553 * accessing the device
554 * 21:16: tc2r, minimum required time from NCEB low to NREB low
555 * 15:12: tw2r, minimum required time from NWEB high to NREB low.
556 * 11:08: twh, write enable hold time
557 * 07:04: twst, write wait states
558 * 03:00: trlt, read wait states
560 trlt = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt);
561 nfi_writel(nfc, trlt, NFI_ACCCON);
566 static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data)
568 struct mtk_nfc *nfc = nand_get_controller_data(chip);
569 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
570 int size = chip->ecc.size + mtk_nand->fdm.reg_size;
572 nfc->ecc_cfg.mode = ECC_DMA_MODE;
573 nfc->ecc_cfg.op = ECC_ENCODE;
575 return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size);
578 static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, u8 *b, int c)
583 static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, u8 *buf, int raw)
585 struct nand_chip *chip = mtd_to_nand(mtd);
586 struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip);
587 u32 bad_pos = nand->bad_mark.pos;
590 bad_pos += nand->bad_mark.sec * mtk_data_len(chip);
592 bad_pos += nand->bad_mark.sec * chip->ecc.size;
594 swap(chip->oob_poi[0], buf[bad_pos]);
597 static int mtk_nfc_format_subpage(struct mtd_info *mtd, u32 offset,
598 u32 len, const u8 *buf)
600 struct nand_chip *chip = mtd_to_nand(mtd);
601 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
602 struct mtk_nfc *nfc = nand_get_controller_data(chip);
603 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
607 start = offset / chip->ecc.size;
608 end = DIV_ROUND_UP(offset + len, chip->ecc.size);
610 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
611 for (i = 0; i < chip->ecc.steps; i++) {
612 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
615 if (start > i || i >= end)
618 if (i == mtk_nand->bad_mark.sec)
619 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
621 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
623 /* program the CRC back to the OOB */
624 ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i));
632 static void mtk_nfc_format_page(struct mtd_info *mtd, const u8 *buf)
634 struct nand_chip *chip = mtd_to_nand(mtd);
635 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
636 struct mtk_nfc *nfc = nand_get_controller_data(chip);
637 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
640 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
641 for (i = 0; i < chip->ecc.steps; i++) {
643 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
646 if (i == mtk_nand->bad_mark.sec)
647 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
649 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
653 static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start,
656 struct mtk_nfc *nfc = nand_get_controller_data(chip);
657 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
658 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
663 for (i = 0; i < sectors; i++) {
664 oobptr = oob_ptr(chip, start + i);
665 vall = nfi_readl(nfc, NFI_FDML(i));
666 valm = nfi_readl(nfc, NFI_FDMM(i));
668 for (j = 0; j < fdm->reg_size; j++)
669 oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
673 static inline void mtk_nfc_write_fdm(struct nand_chip *chip)
675 struct mtk_nfc *nfc = nand_get_controller_data(chip);
676 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
677 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
682 for (i = 0; i < chip->ecc.steps; i++) {
683 oobptr = oob_ptr(chip, i);
686 for (j = 0; j < 8; j++) {
688 vall |= (j < fdm->reg_size ? oobptr[j] : 0xff)
691 valm |= (j < fdm->reg_size ? oobptr[j] : 0xff)
694 nfi_writel(nfc, vall, NFI_FDML(i));
695 nfi_writel(nfc, valm, NFI_FDMM(i));
699 static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip,
700 const u8 *buf, int page, int len)
702 struct mtk_nfc *nfc = nand_get_controller_data(chip);
703 struct device *dev = nfc->dev;
708 addr = dma_map_single(dev, (void *)buf, len, DMA_TO_DEVICE);
709 ret = dma_mapping_error(nfc->dev, addr);
711 dev_err(nfc->dev, "dma mapping error\n");
715 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN;
716 nfi_writew(nfc, reg, NFI_CNFG);
718 nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);
719 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
720 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
722 init_completion(&nfc->done);
724 reg = nfi_readl(nfc, NFI_CON) | CON_BWR;
725 nfi_writel(nfc, reg, NFI_CON);
726 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
728 ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
730 dev_err(dev, "program ahb done timeout\n");
731 nfi_writew(nfc, 0, NFI_INTR_EN);
736 ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg,
737 ADDRCNTR_SEC(reg) >= chip->ecc.steps,
740 dev_err(dev, "hwecc write timeout\n");
744 dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE);
745 nfi_writel(nfc, 0, NFI_CON);
750 static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
751 const u8 *buf, int page, int raw)
753 struct mtk_nfc *nfc = nand_get_controller_data(chip);
754 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
760 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
763 /* OOB => FDM: from register, ECC: from HW */
764 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN;
765 nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG);
767 nfc->ecc_cfg.op = ECC_ENCODE;
768 nfc->ecc_cfg.mode = ECC_NFI_MODE;
769 ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
771 /* clear NFI config */
772 reg = nfi_readw(nfc, NFI_CNFG);
773 reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
774 nfi_writew(nfc, reg, NFI_CNFG);
779 memcpy(nfc->buffer, buf, mtd->writesize);
780 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw);
781 bufpoi = nfc->buffer;
783 /* write OOB into the FDM registers (OOB area in MTK NAND) */
784 mtk_nfc_write_fdm(chip);
789 len = mtd->writesize + (raw ? mtd->oobsize : 0);
790 ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len);
793 mtk_ecc_disable(nfc->ecc);
798 return nand_prog_page_end_op(chip);
801 static int mtk_nfc_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
802 int oob_on, int page)
804 return mtk_nfc_write_page(nand_to_mtd(chip), chip, buf, page, 0);
807 static int mtk_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf,
810 struct mtd_info *mtd = nand_to_mtd(chip);
811 struct mtk_nfc *nfc = nand_get_controller_data(chip);
813 mtk_nfc_format_page(mtd, buf);
814 return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1);
817 static int mtk_nfc_write_subpage_hwecc(struct nand_chip *chip, u32 offset,
818 u32 data_len, const u8 *buf,
819 int oob_on, int page)
821 struct mtd_info *mtd = nand_to_mtd(chip);
822 struct mtk_nfc *nfc = nand_get_controller_data(chip);
825 ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf);
829 /* use the data in the private buffer (now with FDM and CRC) */
830 return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1);
833 static int mtk_nfc_write_oob_std(struct nand_chip *chip, int page)
835 return mtk_nfc_write_page_raw(chip, NULL, 1, page);
838 static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors)
840 struct nand_chip *chip = mtd_to_nand(mtd);
841 struct mtk_nfc *nfc = nand_get_controller_data(chip);
842 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
843 struct mtk_ecc_stats stats;
846 rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
848 memset(buf, 0xff, sectors * chip->ecc.size);
849 for (i = 0; i < sectors; i++)
850 memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size);
854 mtk_ecc_get_stats(nfc->ecc, &stats, sectors);
855 mtd->ecc_stats.corrected += stats.corrected;
856 mtd->ecc_stats.failed += stats.failed;
858 return stats.bitflips;
861 static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
862 u32 data_offs, u32 readlen,
863 u8 *bufpoi, int page, int raw)
865 struct mtk_nfc *nfc = nand_get_controller_data(chip);
866 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
867 u32 spare = mtk_nand->spare_per_sector;
868 u32 column, sectors, start, end, reg;
875 start = data_offs / chip->ecc.size;
876 end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
878 sectors = end - start;
879 column = start * (chip->ecc.size + spare);
881 len = sectors * chip->ecc.size + (raw ? sectors * spare : 0);
882 buf = bufpoi + start * chip->ecc.size;
884 nand_read_page_op(chip, page, column, NULL, 0);
886 addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE);
887 rc = dma_mapping_error(nfc->dev, addr);
889 dev_err(nfc->dev, "dma mapping error\n");
894 reg = nfi_readw(nfc, NFI_CNFG);
895 reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB;
897 reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
898 nfi_writew(nfc, reg, NFI_CNFG);
900 nfc->ecc_cfg.mode = ECC_NFI_MODE;
901 nfc->ecc_cfg.sectors = sectors;
902 nfc->ecc_cfg.op = ECC_DECODE;
903 rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
905 dev_err(nfc->dev, "ecc enable\n");
907 reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN |
908 CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
909 nfi_writew(nfc, reg, NFI_CNFG);
910 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
915 nfi_writew(nfc, reg, NFI_CNFG);
918 nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON);
919 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
920 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
922 init_completion(&nfc->done);
923 reg = nfi_readl(nfc, NFI_CON) | CON_BRD;
924 nfi_writel(nfc, reg, NFI_CON);
925 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
927 rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
929 dev_warn(nfc->dev, "read ahb/dma done timeout\n");
931 rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg,
932 ADDRCNTR_SEC(reg) >= sectors, 10,
935 dev_err(nfc->dev, "subpage done timeout\n");
940 rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
941 bitflips = rc < 0 ? -ETIMEDOUT :
942 mtk_nfc_update_ecc_stats(mtd, buf, sectors);
943 mtk_nfc_read_fdm(chip, start, sectors);
947 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
952 mtk_ecc_disable(nfc->ecc);
954 if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec)
955 mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw);
957 nfi_writel(nfc, 0, NFI_CON);
962 static int mtk_nfc_read_subpage_hwecc(struct nand_chip *chip, u32 off,
963 u32 len, u8 *p, int pg)
965 return mtk_nfc_read_subpage(nand_to_mtd(chip), chip, off, len, p, pg,
969 static int mtk_nfc_read_page_hwecc(struct nand_chip *chip, u8 *p, int oob_on,
972 struct mtd_info *mtd = nand_to_mtd(chip);
974 return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0);
977 static int mtk_nfc_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_on,
980 struct mtd_info *mtd = nand_to_mtd(chip);
981 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
982 struct mtk_nfc *nfc = nand_get_controller_data(chip);
983 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
986 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
987 ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer,
992 for (i = 0; i < chip->ecc.steps; i++) {
993 memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
995 if (i == mtk_nand->bad_mark.sec)
996 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
999 memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
1006 static int mtk_nfc_read_oob_std(struct nand_chip *chip, int page)
1008 return mtk_nfc_read_page_raw(chip, NULL, 1, page);
1011 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc)
1014 * CNRNB: nand ready/busy register
1015 * -------------------------------
1016 * 7:4: timeout register for polling the NAND busy/ready signal
1017 * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles.
1019 nfi_writew(nfc, 0xf1, NFI_CNRNB);
1020 nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
1022 mtk_nfc_hw_reset(nfc);
1024 nfi_readl(nfc, NFI_INTR_STA);
1025 nfi_writel(nfc, 0, NFI_INTR_EN);
1028 static irqreturn_t mtk_nfc_irq(int irq, void *id)
1030 struct mtk_nfc *nfc = id;
1033 sta = nfi_readw(nfc, NFI_INTR_STA);
1034 ien = nfi_readw(nfc, NFI_INTR_EN);
1039 nfi_writew(nfc, ~sta & ien, NFI_INTR_EN);
1040 complete(&nfc->done);
1045 static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk)
1049 ret = clk_prepare_enable(clk->nfi_clk);
1051 dev_err(dev, "failed to enable nfi clk\n");
1055 ret = clk_prepare_enable(clk->pad_clk);
1057 dev_err(dev, "failed to enable pad clk\n");
1058 clk_disable_unprepare(clk->nfi_clk);
1065 static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk)
1067 clk_disable_unprepare(clk->nfi_clk);
1068 clk_disable_unprepare(clk->pad_clk);
1071 static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1072 struct mtd_oob_region *oob_region)
1074 struct nand_chip *chip = mtd_to_nand(mtd);
1075 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1076 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1079 eccsteps = mtd->writesize / chip->ecc.size;
1081 if (section >= eccsteps)
1084 oob_region->length = fdm->reg_size - fdm->ecc_size;
1085 oob_region->offset = section * fdm->reg_size + fdm->ecc_size;
1090 static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1091 struct mtd_oob_region *oob_region)
1093 struct nand_chip *chip = mtd_to_nand(mtd);
1094 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1100 eccsteps = mtd->writesize / chip->ecc.size;
1101 oob_region->offset = mtk_nand->fdm.reg_size * eccsteps;
1102 oob_region->length = mtd->oobsize - oob_region->offset;
1107 static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = {
1108 .free = mtk_nfc_ooblayout_free,
1109 .ecc = mtk_nfc_ooblayout_ecc,
1112 static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
1114 struct nand_chip *nand = mtd_to_nand(mtd);
1115 struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
1116 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1119 ecc_bytes = DIV_ROUND_UP(nand->ecc.strength *
1120 mtk_ecc_get_parity_bits(nfc->ecc), 8);
1122 fdm->reg_size = chip->spare_per_sector - ecc_bytes;
1123 if (fdm->reg_size > NFI_FDM_MAX_SIZE)
1124 fdm->reg_size = NFI_FDM_MAX_SIZE;
1126 /* bad block mark storage */
1130 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
1131 struct mtd_info *mtd)
1133 struct nand_chip *nand = mtd_to_nand(mtd);
1135 if (mtd->writesize == 512) {
1136 bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap;
1138 bm_ctl->bm_swap = mtk_nfc_bad_mark_swap;
1139 bm_ctl->sec = mtd->writesize / mtk_data_len(nand);
1140 bm_ctl->pos = mtd->writesize % mtk_data_len(nand);
1144 static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd)
1146 struct nand_chip *nand = mtd_to_nand(mtd);
1147 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1148 const u8 *spare = nfc->caps->spare_size;
1149 u32 eccsteps, i, closest_spare = 0;
1151 eccsteps = mtd->writesize / nand->ecc.size;
1152 *sps = mtd->oobsize / eccsteps;
1154 if (nand->ecc.size == 1024)
1157 if (*sps < MTK_NFC_MIN_SPARE)
1160 for (i = 0; i < nfc->caps->num_spare_size; i++) {
1161 if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) {
1163 if (*sps == spare[i])
1168 *sps = spare[closest_spare];
1170 if (nand->ecc.size == 1024)
1176 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
1178 struct nand_chip *nand = mtd_to_nand(mtd);
1179 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1183 /* support only ecc hw mode */
1184 if (nand->ecc.mode != NAND_ECC_HW) {
1185 dev_err(dev, "ecc.mode not supported\n");
1189 /* if optional dt settings not present */
1190 if (!nand->ecc.size || !nand->ecc.strength) {
1191 /* use datasheet requirements */
1192 nand->ecc.strength = nand->base.eccreq.strength;
1193 nand->ecc.size = nand->base.eccreq.step_size;
1196 * align eccstrength and eccsize
1197 * this controller only supports 512 and 1024 sizes
1199 if (nand->ecc.size < 1024) {
1200 if (mtd->writesize > 512 &&
1201 nfc->caps->max_sector_size > 512) {
1202 nand->ecc.size = 1024;
1203 nand->ecc.strength <<= 1;
1205 nand->ecc.size = 512;
1208 nand->ecc.size = 1024;
1211 ret = mtk_nfc_set_spare_per_sector(&spare, mtd);
1215 /* calculate oob bytes except ecc parity data */
1216 free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
1218 free = spare - free;
1221 * enhance ecc strength if oob left is bigger than max FDM size
1222 * or reduce ecc strength if oob size is not enough for ecc
1225 if (free > NFI_FDM_MAX_SIZE) {
1226 spare -= NFI_FDM_MAX_SIZE;
1227 nand->ecc.strength = (spare << 3) /
1228 mtk_ecc_get_parity_bits(nfc->ecc);
1229 } else if (free < 0) {
1230 spare -= NFI_FDM_MIN_SIZE;
1231 nand->ecc.strength = (spare << 3) /
1232 mtk_ecc_get_parity_bits(nfc->ecc);
1236 mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength);
1238 dev_info(dev, "eccsize %d eccstrength %d\n",
1239 nand->ecc.size, nand->ecc.strength);
1244 static int mtk_nfc_attach_chip(struct nand_chip *chip)
1246 struct mtd_info *mtd = nand_to_mtd(chip);
1247 struct device *dev = mtd->dev.parent;
1248 struct mtk_nfc *nfc = nand_get_controller_data(chip);
1249 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1253 if (chip->options & NAND_BUSWIDTH_16) {
1254 dev_err(dev, "16bits buswidth not supported");
1258 /* store bbt magic in page, cause OOB is not protected */
1259 if (chip->bbt_options & NAND_BBT_USE_FLASH)
1260 chip->bbt_options |= NAND_BBT_NO_OOB;
1262 ret = mtk_nfc_ecc_init(dev, mtd);
1266 ret = mtk_nfc_set_spare_per_sector(&mtk_nand->spare_per_sector, mtd);
1270 mtk_nfc_set_fdm(&mtk_nand->fdm, mtd);
1271 mtk_nfc_set_bad_mark_ctl(&mtk_nand->bad_mark, mtd);
1273 len = mtd->writesize + mtd->oobsize;
1274 nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1281 static const struct nand_controller_ops mtk_nfc_controller_ops = {
1282 .attach_chip = mtk_nfc_attach_chip,
1283 .setup_data_interface = mtk_nfc_setup_data_interface,
1286 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
1287 struct device_node *np)
1289 struct mtk_nfc_nand_chip *chip;
1290 struct nand_chip *nand;
1291 struct mtd_info *mtd;
1297 if (!of_get_property(np, "reg", &nsels))
1300 nsels /= sizeof(u32);
1301 if (!nsels || nsels > MTK_NAND_MAX_NSELS) {
1302 dev_err(dev, "invalid reg property size %d\n", nsels);
1306 chip = devm_kzalloc(dev, sizeof(*chip) + nsels * sizeof(u8),
1311 chip->nsels = nsels;
1312 for (i = 0; i < nsels; i++) {
1313 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1315 dev_err(dev, "reg property failure : %d\n", ret);
1318 chip->sels[i] = tmp;
1322 nand->controller = &nfc->controller;
1324 nand_set_flash_node(nand, np);
1325 nand_set_controller_data(nand, nfc);
1327 nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ;
1328 nand->legacy.dev_ready = mtk_nfc_dev_ready;
1329 nand->legacy.select_chip = mtk_nfc_select_chip;
1330 nand->legacy.write_byte = mtk_nfc_write_byte;
1331 nand->legacy.write_buf = mtk_nfc_write_buf;
1332 nand->legacy.read_byte = mtk_nfc_read_byte;
1333 nand->legacy.read_buf = mtk_nfc_read_buf;
1334 nand->legacy.cmd_ctrl = mtk_nfc_cmd_ctrl;
1336 /* set default mode in case dt entry is missing */
1337 nand->ecc.mode = NAND_ECC_HW;
1339 nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc;
1340 nand->ecc.write_page_raw = mtk_nfc_write_page_raw;
1341 nand->ecc.write_page = mtk_nfc_write_page_hwecc;
1342 nand->ecc.write_oob_raw = mtk_nfc_write_oob_std;
1343 nand->ecc.write_oob = mtk_nfc_write_oob_std;
1345 nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc;
1346 nand->ecc.read_page_raw = mtk_nfc_read_page_raw;
1347 nand->ecc.read_page = mtk_nfc_read_page_hwecc;
1348 nand->ecc.read_oob_raw = mtk_nfc_read_oob_std;
1349 nand->ecc.read_oob = mtk_nfc_read_oob_std;
1351 mtd = nand_to_mtd(nand);
1352 mtd->owner = THIS_MODULE;
1353 mtd->dev.parent = dev;
1354 mtd->name = MTK_NAME;
1355 mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops);
1357 mtk_nfc_hw_init(nfc);
1359 ret = nand_scan(nand, nsels);
1363 ret = mtd_device_register(mtd, NULL, 0);
1365 dev_err(dev, "mtd parse partition error\n");
1370 list_add_tail(&chip->node, &nfc->chips);
1375 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
1377 struct device_node *np = dev->of_node;
1378 struct device_node *nand_np;
1381 for_each_child_of_node(np, nand_np) {
1382 ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np);
1384 of_node_put(nand_np);
1392 static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
1393 .spare_size = spare_size_mt2701,
1394 .num_spare_size = 16,
1395 .pageformat_spare_shift = 4,
1398 .max_sector_size = 1024,
1401 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
1402 .spare_size = spare_size_mt2712,
1403 .num_spare_size = 19,
1404 .pageformat_spare_shift = 16,
1407 .max_sector_size = 1024,
1410 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
1411 .spare_size = spare_size_mt7622,
1412 .num_spare_size = 4,
1413 .pageformat_spare_shift = 4,
1416 .max_sector_size = 512,
1419 static const struct of_device_id mtk_nfc_id_table[] = {
1421 .compatible = "mediatek,mt2701-nfc",
1422 .data = &mtk_nfc_caps_mt2701,
1424 .compatible = "mediatek,mt2712-nfc",
1425 .data = &mtk_nfc_caps_mt2712,
1427 .compatible = "mediatek,mt7622-nfc",
1428 .data = &mtk_nfc_caps_mt7622,
1432 MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
1434 static int mtk_nfc_probe(struct platform_device *pdev)
1436 struct device *dev = &pdev->dev;
1437 struct device_node *np = dev->of_node;
1438 struct mtk_nfc *nfc;
1439 struct resource *res;
1442 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1446 nand_controller_init(&nfc->controller);
1447 INIT_LIST_HEAD(&nfc->chips);
1448 nfc->controller.ops = &mtk_nfc_controller_ops;
1450 /* probe defer if not ready */
1451 nfc->ecc = of_mtk_ecc_get(np);
1452 if (IS_ERR(nfc->ecc))
1453 return PTR_ERR(nfc->ecc);
1457 nfc->caps = of_device_get_match_data(dev);
1460 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1461 nfc->regs = devm_ioremap_resource(dev, res);
1462 if (IS_ERR(nfc->regs)) {
1463 ret = PTR_ERR(nfc->regs);
1467 nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1468 if (IS_ERR(nfc->clk.nfi_clk)) {
1469 dev_err(dev, "no clk\n");
1470 ret = PTR_ERR(nfc->clk.nfi_clk);
1474 nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk");
1475 if (IS_ERR(nfc->clk.pad_clk)) {
1476 dev_err(dev, "no pad clk\n");
1477 ret = PTR_ERR(nfc->clk.pad_clk);
1481 ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1485 irq = platform_get_irq(pdev, 0);
1487 dev_err(dev, "no nfi irq resource\n");
1492 ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc);
1494 dev_err(dev, "failed to request nfi irq\n");
1498 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1500 dev_err(dev, "failed to set dma mask\n");
1504 platform_set_drvdata(pdev, nfc);
1506 ret = mtk_nfc_nand_chips_init(dev, nfc);
1508 dev_err(dev, "failed to init nand chips\n");
1515 mtk_nfc_disable_clk(&nfc->clk);
1518 mtk_ecc_release(nfc->ecc);
1523 static int mtk_nfc_remove(struct platform_device *pdev)
1525 struct mtk_nfc *nfc = platform_get_drvdata(pdev);
1526 struct mtk_nfc_nand_chip *chip;
1528 while (!list_empty(&nfc->chips)) {
1529 chip = list_first_entry(&nfc->chips, struct mtk_nfc_nand_chip,
1531 nand_release(&chip->nand);
1532 list_del(&chip->node);
1535 mtk_ecc_release(nfc->ecc);
1536 mtk_nfc_disable_clk(&nfc->clk);
1541 #ifdef CONFIG_PM_SLEEP
1542 static int mtk_nfc_suspend(struct device *dev)
1544 struct mtk_nfc *nfc = dev_get_drvdata(dev);
1546 mtk_nfc_disable_clk(&nfc->clk);
1551 static int mtk_nfc_resume(struct device *dev)
1553 struct mtk_nfc *nfc = dev_get_drvdata(dev);
1554 struct mtk_nfc_nand_chip *chip;
1555 struct nand_chip *nand;
1561 ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1565 /* reset NAND chip if VCC was powered off */
1566 list_for_each_entry(chip, &nfc->chips, node) {
1568 for (i = 0; i < chip->nsels; i++)
1569 nand_reset(nand, i);
1575 static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume);
1578 static struct platform_driver mtk_nfc_driver = {
1579 .probe = mtk_nfc_probe,
1580 .remove = mtk_nfc_remove,
1583 .of_match_table = mtk_nfc_id_table,
1584 #ifdef CONFIG_PM_SLEEP
1585 .pm = &mtk_nfc_pm_ops,
1590 module_platform_driver(mtk_nfc_driver);
1592 MODULE_LICENSE("GPL");
1593 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
1594 MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");