drivers/mtd/nand/raw/fsl_ifc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Integrated Flash Controller NAND Machine Driver
   3  *
   4  * Copyright (c) 2012 Freescale Semiconductor, Inc
   5  *
   6  * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <malloc.h>
  12 #include <nand.h>
  13
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/rawnand.h>
  16 #include <linux/mtd/nand_ecc.h>
  17
  18 #include <asm/io.h>
  19 #include <linux/errno.h>
  20 #include <fsl_ifc.h>
  21
  22 #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  23 #define CONFIG_SYS_FSL_IFC_BANK_COUNT   4
  24 #endif
  25
  26 #define MAX_BANKS       CONFIG_SYS_FSL_IFC_BANK_COUNT
  27 #define ERR_BYTE        0xFF /* Value returned for read bytes
  28                                 when read failed */
  29
  30 struct fsl_ifc_ctrl;
  31
  32 /* mtd information per set */
  33 struct fsl_ifc_mtd {
  34         struct nand_chip chip;
  35         struct fsl_ifc_ctrl *ctrl;
  36
  37         struct device *dev;
  38         int bank;               /* Chip select bank number                */
  39         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  40         u8 __iomem *vbase;      /* Chip select base virtual address       */
  41 };
  42
  43 /* overview of the fsl ifc controller */
  44 struct fsl_ifc_ctrl {
  45         struct nand_hw_control controller;
  46         struct fsl_ifc_mtd *chips[MAX_BANKS];
  47
  48         /* device info */
  49         struct fsl_ifc regs;
  50         void __iomem *addr;      /* Address of assigned IFC buffer        */
  51         unsigned int page;       /* Last page written to / read from      */
  52         unsigned int read_bytes; /* Number of bytes read during command   */
  53         unsigned int column;     /* Saved column from SEQIN               */
  54         unsigned int index;      /* Pointer to next byte to 'read'        */
  55         unsigned int status;     /* status read from NEESR after last op  */
  56         unsigned int oob;        /* Non zero if operating on OOB data     */
  57         unsigned int eccread;    /* Non zero for a full-page ECC read     */
  58 };
  59
  60 static struct fsl_ifc_ctrl *ifc_ctrl;
  61
  62 /* 512-byte page with 4-bit ECC, 8-bit */
  63 static struct nand_ecclayout oob_512_8bit_ecc4 = {
  64         .eccbytes = 8,
  65         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  66         .oobfree = { {0, 5}, {6, 2} },
  67 };
  68
  69 /* 512-byte page with 4-bit ECC, 16-bit */
  70 static struct nand_ecclayout oob_512_16bit_ecc4 = {
  71         .eccbytes = 8,
  72         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  73         .oobfree = { {2, 6}, },
  74 };
  75
  76 /* 2048-byte page size with 4-bit ECC */
  77 static struct nand_ecclayout oob_2048_ecc4 = {
  78         .eccbytes = 32,
  79         .eccpos = {
  80                 8, 9, 10, 11, 12, 13, 14, 15,
  81                 16, 17, 18, 19, 20, 21, 22, 23,
  82                 24, 25, 26, 27, 28, 29, 30, 31,
  83                 32, 33, 34, 35, 36, 37, 38, 39,
  84         },
  85         .oobfree = { {2, 6}, {40, 24} },
  86 };
  87
  88 /* 4096-byte page size with 4-bit ECC */
  89 static struct nand_ecclayout oob_4096_ecc4 = {
  90         .eccbytes = 64,
  91         .eccpos = {
  92                 8, 9, 10, 11, 12, 13, 14, 15,
  93                 16, 17, 18, 19, 20, 21, 22, 23,
  94                 24, 25, 26, 27, 28, 29, 30, 31,
  95                 32, 33, 34, 35, 36, 37, 38, 39,
  96                 40, 41, 42, 43, 44, 45, 46, 47,
  97                 48, 49, 50, 51, 52, 53, 54, 55,
  98                 56, 57, 58, 59, 60, 61, 62, 63,
  99                 64, 65, 66, 67, 68, 69, 70, 71,
 100         },
 101         .oobfree = { {2, 6}, {72, 56} },
 102 };
 103
 104 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
 105 static struct nand_ecclayout oob_4096_ecc8 = {
 106         .eccbytes = 128,
 107         .eccpos = {
 108                 8, 9, 10, 11, 12, 13, 14, 15,
 109                 16, 17, 18, 19, 20, 21, 22, 23,
 110                 24, 25, 26, 27, 28, 29, 30, 31,
 111                 32, 33, 34, 35, 36, 37, 38, 39,
 112                 40, 41, 42, 43, 44, 45, 46, 47,
 113                 48, 49, 50, 51, 52, 53, 54, 55,
 114                 56, 57, 58, 59, 60, 61, 62, 63,
 115                 64, 65, 66, 67, 68, 69, 70, 71,
 116                 72, 73, 74, 75, 76, 77, 78, 79,
 117                 80, 81, 82, 83, 84, 85, 86, 87,
 118                 88, 89, 90, 91, 92, 93, 94, 95,
 119                 96, 97, 98, 99, 100, 101, 102, 103,
 120                 104, 105, 106, 107, 108, 109, 110, 111,
 121                 112, 113, 114, 115, 116, 117, 118, 119,
 122                 120, 121, 122, 123, 124, 125, 126, 127,
 123                 128, 129, 130, 131, 132, 133, 134, 135,
 124         },
 125         .oobfree = { {2, 6}, {136, 82} },
 126 };
 127
 128 /* 8192-byte page size with 4-bit ECC */
 129 static struct nand_ecclayout oob_8192_ecc4 = {
 130         .eccbytes = 128,
 131         .eccpos = {
 132                 8, 9, 10, 11, 12, 13, 14, 15,
 133                 16, 17, 18, 19, 20, 21, 22, 23,
 134                 24, 25, 26, 27, 28, 29, 30, 31,
 135                 32, 33, 34, 35, 36, 37, 38, 39,
 136                 40, 41, 42, 43, 44, 45, 46, 47,
 137                 48, 49, 50, 51, 52, 53, 54, 55,
 138                 56, 57, 58, 59, 60, 61, 62, 63,
 139                 64, 65, 66, 67, 68, 69, 70, 71,
 140                 72, 73, 74, 75, 76, 77, 78, 79,
 141                 80, 81, 82, 83, 84, 85, 86, 87,
 142                 88, 89, 90, 91, 92, 93, 94, 95,
 143                 96, 97, 98, 99, 100, 101, 102, 103,
 144                 104, 105, 106, 107, 108, 109, 110, 111,
 145                 112, 113, 114, 115, 116, 117, 118, 119,
 146                 120, 121, 122, 123, 124, 125, 126, 127,
 147                 128, 129, 130, 131, 132, 133, 134, 135,
 148         },
 149         .oobfree = { {2, 6}, {136, 208} },
 150 };
 151
 152 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
 153 static struct nand_ecclayout oob_8192_ecc8 = {
 154         .eccbytes = 256,
 155         .eccpos = {
 156                 8, 9, 10, 11, 12, 13, 14, 15,
 157                 16, 17, 18, 19, 20, 21, 22, 23,
 158                 24, 25, 26, 27, 28, 29, 30, 31,
 159                 32, 33, 34, 35, 36, 37, 38, 39,
 160                 40, 41, 42, 43, 44, 45, 46, 47,
 161                 48, 49, 50, 51, 52, 53, 54, 55,
 162                 56, 57, 58, 59, 60, 61, 62, 63,
 163                 64, 65, 66, 67, 68, 69, 70, 71,
 164                 72, 73, 74, 75, 76, 77, 78, 79,
 165                 80, 81, 82, 83, 84, 85, 86, 87,
 166                 88, 89, 90, 91, 92, 93, 94, 95,
 167                 96, 97, 98, 99, 100, 101, 102, 103,
 168                 104, 105, 106, 107, 108, 109, 110, 111,
 169                 112, 113, 114, 115, 116, 117, 118, 119,
 170                 120, 121, 122, 123, 124, 125, 126, 127,
 171                 128, 129, 130, 131, 132, 133, 134, 135,
 172                 136, 137, 138, 139, 140, 141, 142, 143,
 173                 144, 145, 146, 147, 148, 149, 150, 151,
 174                 152, 153, 154, 155, 156, 157, 158, 159,
 175                 160, 161, 162, 163, 164, 165, 166, 167,
 176                 168, 169, 170, 171, 172, 173, 174, 175,
 177                 176, 177, 178, 179, 180, 181, 182, 183,
 178                 184, 185, 186, 187, 188, 189, 190, 191,
 179                 192, 193, 194, 195, 196, 197, 198, 199,
 180                 200, 201, 202, 203, 204, 205, 206, 207,
 181                 208, 209, 210, 211, 212, 213, 214, 215,
 182                 216, 217, 218, 219, 220, 221, 222, 223,
 183                 224, 225, 226, 227, 228, 229, 230, 231,
 184                 232, 233, 234, 235, 236, 237, 238, 239,
 185                 240, 241, 242, 243, 244, 245, 246, 247,
 186                 248, 249, 250, 251, 252, 253, 254, 255,
 187                 256, 257, 258, 259, 260, 261, 262, 263,
 188         },
 189         .oobfree = { {2, 6}, {264, 80} },
 190 };
 191
 192 /*
 193  * Generic flash bbt descriptors
 194  */
 195 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 196 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 197
 198 static struct nand_bbt_descr bbt_main_descr = {
 199         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 200                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 201         .offs = 2, /* 0 on 8-bit small page */
 202         .len = 4,
 203         .veroffs = 6,
 204         .maxblocks = 4,
 205         .pattern = bbt_pattern,
 206 };
 207
 208 static struct nand_bbt_descr bbt_mirror_descr = {
 209         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 210                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 211         .offs = 2, /* 0 on 8-bit small page */
 212         .len = 4,
 213         .veroffs = 6,
 214         .maxblocks = 4,
 215         .pattern = mirror_pattern,
 216 };
 217
 218 /*
 219  * Set up the IFC hardware block and page address fields, and the ifc nand
 220  * structure addr field to point to the correct IFC buffer in memory
 221  */
 222 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 223 {
 224         struct nand_chip *chip = mtd_to_nand(mtd);
 225         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 226         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 227         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 228         int buf_num;
 229
 230         ctrl->page = page_addr;
 231
 232         /* Program ROW0/COL0 */
 233         ifc_out32(&ifc->ifc_nand.row0, page_addr);
 234         ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
 235
 236         buf_num = page_addr & priv->bufnum_mask;
 237
 238         ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 239         ctrl->index = column;
 240
 241         /* for OOB data point to the second half of the buffer */
 242         if (oob)
 243                 ctrl->index += mtd->writesize;
 244 }
 245
 246 /* returns nonzero if entire page is blank */
 247 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 248                           u32 eccstat, unsigned int bufnum)
 249 {
 250         return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
 251 }
 252
 253 /*
 254  * execute IFC NAND command and wait for it to complete
 255  */
 256 static int fsl_ifc_run_command(struct mtd_info *mtd)
 257 {
 258         struct nand_chip *chip = mtd_to_nand(mtd);
 259         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 260         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 261         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 262         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 263         u32 time_start;
 264         u32 eccstat;
 265         int i;
 266
 267         /* set the chip select for NAND Transaction */
 268         ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 269
 270         /* start read/write seq */
 271         ifc_out32(&ifc->ifc_nand.nandseq_strt,
 272                   IFC_NAND_SEQ_STRT_FIR_STRT);
 273
 274         /* wait for NAND Machine complete flag or timeout */
 275         time_start = get_timer(0);
 276
 277         while (get_timer(time_start) < timeo) {
 278                 ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 279
 280                 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 281                         break;
 282         }
 283
 284         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
 285
 286         if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
 287                 printf("%s: Flash Time Out Error\n", __func__);
 288         if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
 289                 printf("%s: Write Protect Error\n", __func__);
 290
 291         if (ctrl->eccread) {
 292                 int errors;
 293                 int bufnum = ctrl->page & priv->bufnum_mask;
 294                 int sector_start = bufnum * chip->ecc.steps;
 295                 int sector_end = sector_start + chip->ecc.steps - 1;
 296                 u32 *eccstat_regs;
 297
 298                 eccstat_regs = ifc->ifc_nand.nand_eccstat;
 299                 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
 300
 301                 for (i = sector_start; i <= sector_end; i++) {
 302                         if ((i != sector_start) && !(i % 4))
 303                                 eccstat = ifc_in32(&eccstat_regs[i / 4]);
 304
 305                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 306
 307                         if (errors == 15) {
 308                                 /*
 309                                  * Uncorrectable error.
 310                                  * We'll check for blank pages later.
 311                                  *
 312                                  * We disable ECCER reporting due to erratum
 313                                  * IFC-A002770 -- so report it now if we
 314                                  * see an uncorrectable error in ECCSTAT.
 315                                  */
 316                                 ctrl->status |= IFC_NAND_EVTER_STAT_ECCER;
 317                                 continue;
 318                         }
 319
 320                         mtd->ecc_stats.corrected += errors;
 321                 }
 322
 323                 ctrl->eccread = 0;
 324         }
 325
 326         /* returns 0 on success otherwise non-zero) */
 327         return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
 328 }
 329
 330 static void fsl_ifc_do_read(struct nand_chip *chip,
 331                             int oob,
 332                             struct mtd_info *mtd)
 333 {
 334         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 335         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 336         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 337
 338         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 339         if (mtd->writesize > 512) {
 340                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 341                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 342                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 343                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 344                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 345                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
 346                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 347
 348                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 349                           (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 350                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 351         } else {
 352                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 353                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 354                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 355                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 356                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
 357
 358                 if (oob)
 359                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 360                                   NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
 361                 else
 362                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 363                                   NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 364         }
 365 }
 366
 367 /* cmdfunc send commands to the IFC NAND Machine */
 368 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 369                              int column, int page_addr)
 370 {
 371         struct nand_chip *chip = mtd_to_nand(mtd);
 372         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 373         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 374         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 375
 376         /* clear the read buffer */
 377         ctrl->read_bytes = 0;
 378         if (command != NAND_CMD_PAGEPROG)
 379                 ctrl->index = 0;
 380
 381         switch (command) {
 382         /* READ0 read the entire buffer to use hardware ECC. */
 383         case NAND_CMD_READ0: {
 384                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 385                 set_addr(mtd, 0, page_addr, 0);
 386
 387                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 388                 ctrl->index += column;
 389
 390                 if (chip->ecc.mode == NAND_ECC_HW)
 391                         ctrl->eccread = 1;
 392
 393                 fsl_ifc_do_read(chip, 0, mtd);
 394                 fsl_ifc_run_command(mtd);
 395                 return;
 396         }
 397
 398         /* READOOB reads only the OOB because no ECC is performed. */
 399         case NAND_CMD_READOOB:
 400                 ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
 401                 set_addr(mtd, column, page_addr, 1);
 402
 403                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 404
 405                 fsl_ifc_do_read(chip, 1, mtd);
 406                 fsl_ifc_run_command(mtd);
 407
 408                 return;
 409
 410         /* READID must read all possible bytes while CEB is active */
 411         case NAND_CMD_READID:
 412         case NAND_CMD_PARAM: {
 413                 int timing = IFC_FIR_OP_RB;
 414                 if (command == NAND_CMD_PARAM)
 415                         timing = IFC_FIR_OP_RBCD;
 416
 417                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 418                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 419                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 420                           (timing << IFC_NAND_FIR0_OP2_SHIFT));
 421                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 422                           command << IFC_NAND_FCR0_CMD0_SHIFT);
 423                 ifc_out32(&ifc->ifc_nand.row3, column);
 424
 425                 /*
 426                  * although currently it's 8 bytes for READID, we always read
 427                  * the maximum 256 bytes(for PARAM)
 428                  */
 429                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
 430                 ctrl->read_bytes = 256;
 431
 432                 set_addr(mtd, 0, 0, 0);
 433                 fsl_ifc_run_command(mtd);
 434                 return;
 435         }
 436
 437         /* ERASE1 stores the block and page address */
 438         case NAND_CMD_ERASE1:
 439                 set_addr(mtd, 0, page_addr, 0);
 440                 return;
 441
 442         /* ERASE2 uses the block and page address from ERASE1 */
 443         case NAND_CMD_ERASE2:
 444                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 445                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 446                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 447                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
 448
 449                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 450                           (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 451                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
 452
 453                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 454                 ctrl->read_bytes = 0;
 455                 fsl_ifc_run_command(mtd);
 456                 return;
 457
 458         /* SEQIN sets up the addr buffer and all registers except the length */
 459         case NAND_CMD_SEQIN: {
 460                 u32 nand_fcr0;
 461                 ctrl->column = column;
 462                 ctrl->oob = 0;
 463
 464                 if (mtd->writesize > 512) {
 465                         nand_fcr0 =
 466                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 467                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 468                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 469
 470                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 471                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 472                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 473                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 474                                   (IFC_FIR_OP_WBCD  <<
 475                                                 IFC_NAND_FIR0_OP3_SHIFT) |
 476                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
 477                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 478                                   (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 479                                   (IFC_FIR_OP_RDSTAT <<
 480                                         IFC_NAND_FIR1_OP6_SHIFT) |
 481                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
 482                 } else {
 483                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 484                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 485                                     (NAND_CMD_SEQIN <<
 486                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 487                                     (NAND_CMD_STATUS <<
 488                                         IFC_NAND_FCR0_CMD3_SHIFT));
 489
 490                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 491                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 492                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 493                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 494                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 495                                   (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
 496                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 497                                   (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 498                                   (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 499                                   (IFC_FIR_OP_RDSTAT <<
 500                                         IFC_NAND_FIR1_OP7_SHIFT) |
 501                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
 502
 503                         if (column >= mtd->writesize)
 504                                 nand_fcr0 |=
 505                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 506                         else
 507                                 nand_fcr0 |=
 508                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 509                 }
 510
 511                 if (column >= mtd->writesize) {
 512                         /* OOB area --> READOOB */
 513                         column -= mtd->writesize;
 514                         ctrl->oob = 1;
 515                 }
 516                 ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
 517                 set_addr(mtd, column, page_addr, ctrl->oob);
 518                 return;
 519         }
 520
 521         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 522         case NAND_CMD_PAGEPROG:
 523                 if (ctrl->oob)
 524                         ifc_out32(&ifc->ifc_nand.nand_fbcr,
 525                                   ctrl->index - ctrl->column);
 526                 else
 527                         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 528
 529                 fsl_ifc_run_command(mtd);
 530                 return;
 531
 532         case NAND_CMD_STATUS:
 533                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 534                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 535                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
 536                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 537                           NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
 538                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 539                 set_addr(mtd, 0, 0, 0);
 540                 ctrl->read_bytes = 1;
 541
 542                 fsl_ifc_run_command(mtd);
 543
 544                 /*
 545                  * The chip always seems to report that it is
 546                  * write-protected, even when it is not.
 547                  */
 548                 if (chip->options & NAND_BUSWIDTH_16)
 549                         ifc_out16(ctrl->addr,
 550                                   ifc_in16(ctrl->addr) | NAND_STATUS_WP);
 551                 else
 552                         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 553                 return;
 554
 555         case NAND_CMD_RESET:
 556                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 557                           IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
 558                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 559                           NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
 560                 fsl_ifc_run_command(mtd);
 561                 return;
 562
 563         default:
 564                 printf("%s: error, unsupported command 0x%x.\n",
 565                         __func__, command);
 566         }
 567 }
 568
 569 /*
 570  * Write buf to the IFC NAND Controller Data Buffer
 571  */
 572 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 573 {
 574         struct nand_chip *chip = mtd_to_nand(mtd);
 575         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 576         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 577         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 578
 579         if (len <= 0) {
 580                 printf("%s of %d bytes", __func__, len);
 581                 ctrl->status = 0;
 582                 return;
 583         }
 584
 585         if ((unsigned int)len > bufsize - ctrl->index) {
 586                 printf("%s beyond end of buffer "
 587                        "(%d requested, %u available)\n",
 588                         __func__, len, bufsize - ctrl->index);
 589                 len = bufsize - ctrl->index;
 590         }
 591
 592         memcpy_toio(ctrl->addr + ctrl->index, buf, len);
 593         ctrl->index += len;
 594 }
 595
 596 /*
 597  * read a byte from either the IFC hardware buffer if it has any data left
 598  * otherwise issue a command to read a single byte.
 599  */
 600 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
 601 {
 602         struct nand_chip *chip = mtd_to_nand(mtd);
 603         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 604         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 605         unsigned int offset;
 606
 607         /*
 608          * If there are still bytes in the IFC buffer, then use the
 609          * next byte.
 610          */
 611         if (ctrl->index < ctrl->read_bytes) {
 612                 offset = ctrl->index++;
 613                 return in_8(ctrl->addr + offset);
 614         }
 615
 616         printf("%s beyond end of buffer\n", __func__);
 617         return ERR_BYTE;
 618 }
 619
 620 /*
 621  * Read two bytes from the IFC hardware buffer
 622  * read function for 16-bit buswith
 623  */
 624 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 625 {
 626         struct nand_chip *chip = mtd_to_nand(mtd);
 627         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 628         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 629         uint16_t data;
 630
 631         /*
 632          * If there are still bytes in the IFC buffer, then use the
 633          * next byte.
 634          */
 635         if (ctrl->index < ctrl->read_bytes) {
 636                 data = ifc_in16(ctrl->addr + ctrl->index);
 637                 ctrl->index += 2;
 638                 return (uint8_t)data;
 639         }
 640
 641         printf("%s beyond end of buffer\n", __func__);
 642         return ERR_BYTE;
 643 }
 644
 645 /*
 646  * Read from the IFC Controller Data Buffer
 647  */
 648 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 649 {
 650         struct nand_chip *chip = mtd_to_nand(mtd);
 651         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 652         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 653         int avail;
 654
 655         if (len < 0)
 656                 return;
 657
 658         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 659         memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
 660         ctrl->index += avail;
 661
 662         if (len > avail)
 663                 printf("%s beyond end of buffer "
 664                        "(%d requested, %d available)\n",
 665                        __func__, len, avail);
 666 }
 667
 668 /* This function is called after Program and Erase Operations to
 669  * check for success or failure.
 670  */
 671 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 672 {
 673         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 674         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 675         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 676         u32 nand_fsr;
 677         int status;
 678
 679         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 680                 return NAND_STATUS_FAIL;
 681
 682         /* Use READ_STATUS command, but wait for the device to be ready */
 683         ifc_out32(&ifc->ifc_nand.nand_fir0,
 684                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 685                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
 686         ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
 687                   IFC_NAND_FCR0_CMD0_SHIFT);
 688         ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 689         set_addr(mtd, 0, 0, 0);
 690         ctrl->read_bytes = 1;
 691
 692         fsl_ifc_run_command(mtd);
 693
 694         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 695                 return NAND_STATUS_FAIL;
 696
 697         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 698         status = nand_fsr >> 24;
 699
 700         /* Chip sometimes reporting write protect even when it's not */
 701         return status | NAND_STATUS_WP;
 702 }
 703
 704 /*
 705  * The controller does not check for bitflips in erased pages,
 706  * therefore software must check instead.
 707  */
 708 static int
 709 check_erased_page(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd)
 710 {
 711         u8 *ecc = chip->oob_poi;
 712         const int ecc_size = chip->ecc.bytes;
 713         const int pkt_size = chip->ecc.size;
 714         int i, res, bitflips;
 715
 716         /* IFC starts ecc bytes at offset 8 in the spare area. */
 717         ecc += 8;
 718         bitflips = 0;
 719         for (i = 0; i < chip->ecc.steps; i++) {
 720                 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
 721                                                   NULL, 0, chip->ecc.strength);
 722
 723                 if (res < 0) {
 724                         printf("fsl-ifc: NAND Flash ECC Uncorrectable Error\n");
 725                         mtd->ecc_stats.failed++;
 726                 } else if (res > 0) {
 727                         mtd->ecc_stats.corrected += res;
 728                 }
 729                 bitflips = max(res, bitflips);
 730                 buf += pkt_size;
 731                 ecc += ecc_size;
 732         }
 733
 734         return bitflips;
 735 }
 736
 737 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 738                              uint8_t *buf, int oob_required, int page)
 739 {
 740         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 741         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 742
 743         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 744         fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 745
 746         if (ctrl->status & IFC_NAND_EVTER_STAT_ECCER)
 747                 return check_erased_page(chip, buf, mtd);
 748
 749         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 750                 mtd->ecc_stats.failed++;
 751
 752         return 0;
 753 }
 754
 755 /* ECC will be calculated automatically, and errors will be detected in
 756  * waitfunc.
 757  */
 758 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 759                                const uint8_t *buf, int oob_required, int page)
 760 {
 761         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 762         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 763
 764         return 0;
 765 }
 766
 767 static void fsl_ifc_ctrl_init(void)
 768 {
 769         uint32_t ver = 0;
 770         ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
 771         if (!ifc_ctrl)
 772                 return;
 773
 774         ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
 775
 776         ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
 777         if (ver >= FSL_IFC_V2_0_0)
 778                 ifc_ctrl->regs.rregs =
 779                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
 780         else
 781                 ifc_ctrl->regs.rregs =
 782                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
 783
 784         /* clear event registers */
 785         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
 786         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
 787
 788         /* Enable error and event for any detected errors */
 789         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
 790                   IFC_NAND_EVTER_EN_OPC_EN |
 791                   IFC_NAND_EVTER_EN_PGRDCMPL_EN |
 792                   IFC_NAND_EVTER_EN_FTOER_EN |
 793                   IFC_NAND_EVTER_EN_WPER_EN);
 794
 795         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
 796 }
 797
 798 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 799 {
 800 }
 801
 802 static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv, uint32_t ver)
 803 {
 804         struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
 805         uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
 806         uint32_t ncfgr = 0;
 807         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 808         u32 time_start;
 809
 810         if (ver > FSL_IFC_V1_1_0) {
 811                 ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
 812                 ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
 813
 814                 /* wait for  SRAM_INIT bit to be clear or timeout */
 815                 time_start = get_timer(0);
 816                 while (get_timer(time_start) < timeo) {
 817                         ifc_ctrl->status =
 818                                 ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 819
 820                         if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
 821                                 return 0;
 822                 }
 823                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 824                 return 1;
 825         }
 826
 827         cs = priv->bank;
 828
 829         /* Save CSOR and CSOR_ext */
 830         csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
 831         csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
 832
 833         /* chage PageSize 8K and SpareSize 1K*/
 834         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 835         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
 836         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
 837
 838         /* READID */
 839         ifc_out32(&ifc->ifc_nand.nand_fir0,
 840                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 841                   (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 842                   (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
 843         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 844                   NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
 845         ifc_out32(&ifc->ifc_nand.row3, 0x0);
 846
 847         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
 848
 849         /* Program ROW0/COL0 */
 850         ifc_out32(&ifc->ifc_nand.row0, 0x0);
 851         ifc_out32(&ifc->ifc_nand.col0, 0x0);
 852
 853         /* set the chip select for NAND Transaction */
 854         ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 855
 856         /* start read seq */
 857         ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
 858
 859         time_start = get_timer(0);
 860
 861         while (get_timer(time_start) < timeo) {
 862                 ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 863
 864                 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 865                         break;
 866         }
 867
 868         if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
 869                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 870                 return 1;
 871         }
 872
 873         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 874
 875         /* Restore CSOR and CSOR_ext */
 876         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
 877         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
 878
 879         return 0;
 880 }
 881
 882 static int fsl_ifc_chip_init(int devnum, u8 *addr)
 883 {
 884         struct mtd_info *mtd;
 885         struct nand_chip *nand;
 886         struct fsl_ifc_mtd *priv;
 887         struct nand_ecclayout *layout;
 888         struct fsl_ifc_fcm *gregs = NULL;
 889         uint32_t cspr = 0, csor = 0, ver = 0;
 890         int ret = 0;
 891
 892         if (!ifc_ctrl) {
 893                 fsl_ifc_ctrl_init();
 894                 if (!ifc_ctrl)
 895                         return -1;
 896         }
 897
 898         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 899         if (!priv)
 900                 return -ENOMEM;
 901
 902         priv->ctrl = ifc_ctrl;
 903         priv->vbase = addr;
 904         gregs = ifc_ctrl->regs.gregs;
 905
 906         /* Find which chip select it is connected to.
 907          */
 908         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 909                 phys_addr_t phys_addr = virt_to_phys(addr);
 910
 911                 cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
 912                 csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
 913
 914                 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 915                     (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
 916                         break;
 917         }
 918
 919         if (priv->bank >= MAX_BANKS) {
 920                 printf("%s: address did not match any "
 921                        "chip selects\n", __func__);
 922                 kfree(priv);
 923                 return -ENODEV;
 924         }
 925
 926         nand = &priv->chip;
 927         mtd = nand_to_mtd(nand);
 928
 929         ifc_ctrl->chips[priv->bank] = priv;
 930
 931         /* fill in nand_chip structure */
 932         /* set up function call table */
 933
 934         nand->write_buf = fsl_ifc_write_buf;
 935         nand->read_buf = fsl_ifc_read_buf;
 936         nand->select_chip = fsl_ifc_select_chip;
 937         nand->cmdfunc = fsl_ifc_cmdfunc;
 938         nand->waitfunc = fsl_ifc_wait;
 939
 940         /* set up nand options */
 941         nand->bbt_td = &bbt_main_descr;
 942         nand->bbt_md = &bbt_mirror_descr;
 943
 944         /* set up nand options */
 945         nand->options = NAND_NO_SUBPAGE_WRITE;
 946         nand->bbt_options = NAND_BBT_USE_FLASH;
 947
 948         if (cspr & CSPR_PORT_SIZE_16) {
 949                 nand->read_byte = fsl_ifc_read_byte16;
 950                 nand->options |= NAND_BUSWIDTH_16;
 951         } else {
 952                 nand->read_byte = fsl_ifc_read_byte;
 953         }
 954
 955         nand->controller = &ifc_ctrl->controller;
 956         nand_set_controller_data(nand, priv);
 957
 958         nand->ecc.read_page = fsl_ifc_read_page;
 959         nand->ecc.write_page = fsl_ifc_write_page;
 960
 961         /* Hardware generates ECC per 512 Bytes */
 962         nand->ecc.size = 512;
 963         nand->ecc.bytes = 8;
 964
 965         switch (csor & CSOR_NAND_PGS_MASK) {
 966         case CSOR_NAND_PGS_512:
 967                 if (nand->options & NAND_BUSWIDTH_16) {
 968                         layout = &oob_512_16bit_ecc4;
 969                 } else {
 970                         layout = &oob_512_8bit_ecc4;
 971
 972                         /* Avoid conflict with bad block marker */
 973                         bbt_main_descr.offs = 0;
 974                         bbt_mirror_descr.offs = 0;
 975                 }
 976
 977                 nand->ecc.strength = 4;
 978                 priv->bufnum_mask = 15;
 979                 break;
 980
 981         case CSOR_NAND_PGS_2K:
 982                 layout = &oob_2048_ecc4;
 983                 nand->ecc.strength = 4;
 984                 priv->bufnum_mask = 3;
 985                 break;
 986
 987         case CSOR_NAND_PGS_4K:
 988                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 989                     CSOR_NAND_ECC_MODE_4) {
 990                         layout = &oob_4096_ecc4;
 991                         nand->ecc.strength = 4;
 992                 } else {
 993                         layout = &oob_4096_ecc8;
 994                         nand->ecc.strength = 8;
 995                         nand->ecc.bytes = 16;
 996                 }
 997
 998                 priv->bufnum_mask = 1;
 999                 break;
1000
1001         case CSOR_NAND_PGS_8K:
1002                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1003                     CSOR_NAND_ECC_MODE_4) {
1004                         layout = &oob_8192_ecc4;
1005                         nand->ecc.strength = 4;
1006                 } else {
1007                         layout = &oob_8192_ecc8;
1008                         nand->ecc.strength = 8;
1009                         nand->ecc.bytes = 16;
1010                 }
1011
1012                 priv->bufnum_mask = 0;
1013                 break;
1014
1015
1016         default:
1017                 printf("ifc nand: bad csor %#x: bad page size\n", csor);
1018                 return -ENODEV;
1019         }
1020
1021         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
1022         if (csor & CSOR_NAND_ECC_DEC_EN) {
1023                 nand->ecc.mode = NAND_ECC_HW;
1024                 nand->ecc.layout = layout;
1025         } else {
1026                 nand->ecc.mode = NAND_ECC_SOFT;
1027         }
1028
1029         ver = ifc_in32(&gregs->ifc_rev);
1030         if (ver >= FSL_IFC_V1_1_0)
1031                 ret = fsl_ifc_sram_init(priv, ver);
1032         if (ret)
1033                 return ret;
1034
1035         if (ver >= FSL_IFC_V2_0_0)
1036                 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
1037
1038         ret = nand_scan_ident(mtd, 1, NULL);
1039         if (ret)
1040                 return ret;
1041
1042         ret = nand_scan_tail(mtd);
1043         if (ret)
1044                 return ret;
1045
1046         ret = nand_register(devnum, mtd);
1047         if (ret)
1048                 return ret;
1049         return 0;
1050 }
1051
1052 #ifndef CONFIG_SYS_NAND_BASE_LIST
1053 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1054 #endif
1055
1056 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
1057         CONFIG_SYS_NAND_BASE_LIST;
1058
1059 void board_nand_init(void)
1060 {
1061         int i;
1062
1063         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1064                 fsl_ifc_chip_init(i, (u8 *)base_address[i]);
1065 }