drivers/mtd/nand/raw/fsl_ifc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Integrated Flash Controller NAND Machine Driver
   3  *
   4  * Copyright (c) 2012 Freescale Semiconductor, Inc
   5  *
   6  * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <nand.h>
  12
  13 #include <linux/mtd/mtd.h>
  14 #include <linux/mtd/rawnand.h>
  15 #include <linux/mtd/nand_ecc.h>
  16
  17 #include <asm/io.h>
  18 #include <linux/errno.h>
  19 #include <fsl_ifc.h>
  20
  21 #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  22 #define CONFIG_SYS_FSL_IFC_BANK_COUNT   4
  23 #endif
  24
  25 #define MAX_BANKS       CONFIG_SYS_FSL_IFC_BANK_COUNT
  26 #define ERR_BYTE        0xFF /* Value returned for read bytes
  27                                 when read failed */
  28
  29 struct fsl_ifc_ctrl;
  30
  31 /* mtd information per set */
  32 struct fsl_ifc_mtd {
  33         struct nand_chip chip;
  34         struct fsl_ifc_ctrl *ctrl;
  35
  36         struct device *dev;
  37         int bank;               /* Chip select bank number                */
  38         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  39         u8 __iomem *vbase;      /* Chip select base virtual address       */
  40 };
  41
  42 /* overview of the fsl ifc controller */
  43 struct fsl_ifc_ctrl {
  44         struct nand_hw_control controller;
  45         struct fsl_ifc_mtd *chips[MAX_BANKS];
  46
  47         /* device info */
  48         struct fsl_ifc regs;
  49         void __iomem *addr;      /* Address of assigned IFC buffer        */
  50         unsigned int page;       /* Last page written to / read from      */
  51         unsigned int read_bytes; /* Number of bytes read during command   */
  52         unsigned int column;     /* Saved column from SEQIN               */
  53         unsigned int index;      /* Pointer to next byte to 'read'        */
  54         unsigned int status;     /* status read from NEESR after last op  */
  55         unsigned int oob;        /* Non zero if operating on OOB data     */
  56         unsigned int eccread;    /* Non zero for a full-page ECC read     */
  57 };
  58
  59 static struct fsl_ifc_ctrl *ifc_ctrl;
  60
  61 /* 512-byte page with 4-bit ECC, 8-bit */
  62 static struct nand_ecclayout oob_512_8bit_ecc4 = {
  63         .eccbytes = 8,
  64         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  65         .oobfree = { {0, 5}, {6, 2} },
  66 };
  67
  68 /* 512-byte page with 4-bit ECC, 16-bit */
  69 static struct nand_ecclayout oob_512_16bit_ecc4 = {
  70         .eccbytes = 8,
  71         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  72         .oobfree = { {2, 6}, },
  73 };
  74
  75 /* 2048-byte page size with 4-bit ECC */
  76 static struct nand_ecclayout oob_2048_ecc4 = {
  77         .eccbytes = 32,
  78         .eccpos = {
  79                 8, 9, 10, 11, 12, 13, 14, 15,
  80                 16, 17, 18, 19, 20, 21, 22, 23,
  81                 24, 25, 26, 27, 28, 29, 30, 31,
  82                 32, 33, 34, 35, 36, 37, 38, 39,
  83         },
  84         .oobfree = { {2, 6}, {40, 24} },
  85 };
  86
  87 /* 4096-byte page size with 4-bit ECC */
  88 static struct nand_ecclayout oob_4096_ecc4 = {
  89         .eccbytes = 64,
  90         .eccpos = {
  91                 8, 9, 10, 11, 12, 13, 14, 15,
  92                 16, 17, 18, 19, 20, 21, 22, 23,
  93                 24, 25, 26, 27, 28, 29, 30, 31,
  94                 32, 33, 34, 35, 36, 37, 38, 39,
  95                 40, 41, 42, 43, 44, 45, 46, 47,
  96                 48, 49, 50, 51, 52, 53, 54, 55,
  97                 56, 57, 58, 59, 60, 61, 62, 63,
  98                 64, 65, 66, 67, 68, 69, 70, 71,
  99         },
 100         .oobfree = { {2, 6}, {72, 56} },
 101 };
 102
 103 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
 104 static struct nand_ecclayout oob_4096_ecc8 = {
 105         .eccbytes = 128,
 106         .eccpos = {
 107                 8, 9, 10, 11, 12, 13, 14, 15,
 108                 16, 17, 18, 19, 20, 21, 22, 23,
 109                 24, 25, 26, 27, 28, 29, 30, 31,
 110                 32, 33, 34, 35, 36, 37, 38, 39,
 111                 40, 41, 42, 43, 44, 45, 46, 47,
 112                 48, 49, 50, 51, 52, 53, 54, 55,
 113                 56, 57, 58, 59, 60, 61, 62, 63,
 114                 64, 65, 66, 67, 68, 69, 70, 71,
 115                 72, 73, 74, 75, 76, 77, 78, 79,
 116                 80, 81, 82, 83, 84, 85, 86, 87,
 117                 88, 89, 90, 91, 92, 93, 94, 95,
 118                 96, 97, 98, 99, 100, 101, 102, 103,
 119                 104, 105, 106, 107, 108, 109, 110, 111,
 120                 112, 113, 114, 115, 116, 117, 118, 119,
 121                 120, 121, 122, 123, 124, 125, 126, 127,
 122                 128, 129, 130, 131, 132, 133, 134, 135,
 123         },
 124         .oobfree = { {2, 6}, {136, 82} },
 125 };
 126
 127 /* 8192-byte page size with 4-bit ECC */
 128 static struct nand_ecclayout oob_8192_ecc4 = {
 129         .eccbytes = 128,
 130         .eccpos = {
 131                 8, 9, 10, 11, 12, 13, 14, 15,
 132                 16, 17, 18, 19, 20, 21, 22, 23,
 133                 24, 25, 26, 27, 28, 29, 30, 31,
 134                 32, 33, 34, 35, 36, 37, 38, 39,
 135                 40, 41, 42, 43, 44, 45, 46, 47,
 136                 48, 49, 50, 51, 52, 53, 54, 55,
 137                 56, 57, 58, 59, 60, 61, 62, 63,
 138                 64, 65, 66, 67, 68, 69, 70, 71,
 139                 72, 73, 74, 75, 76, 77, 78, 79,
 140                 80, 81, 82, 83, 84, 85, 86, 87,
 141                 88, 89, 90, 91, 92, 93, 94, 95,
 142                 96, 97, 98, 99, 100, 101, 102, 103,
 143                 104, 105, 106, 107, 108, 109, 110, 111,
 144                 112, 113, 114, 115, 116, 117, 118, 119,
 145                 120, 121, 122, 123, 124, 125, 126, 127,
 146                 128, 129, 130, 131, 132, 133, 134, 135,
 147         },
 148         .oobfree = { {2, 6}, {136, 208} },
 149 };
 150
 151 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
 152 static struct nand_ecclayout oob_8192_ecc8 = {
 153         .eccbytes = 256,
 154         .eccpos = {
 155                 8, 9, 10, 11, 12, 13, 14, 15,
 156                 16, 17, 18, 19, 20, 21, 22, 23,
 157                 24, 25, 26, 27, 28, 29, 30, 31,
 158                 32, 33, 34, 35, 36, 37, 38, 39,
 159                 40, 41, 42, 43, 44, 45, 46, 47,
 160                 48, 49, 50, 51, 52, 53, 54, 55,
 161                 56, 57, 58, 59, 60, 61, 62, 63,
 162                 64, 65, 66, 67, 68, 69, 70, 71,
 163                 72, 73, 74, 75, 76, 77, 78, 79,
 164                 80, 81, 82, 83, 84, 85, 86, 87,
 165                 88, 89, 90, 91, 92, 93, 94, 95,
 166                 96, 97, 98, 99, 100, 101, 102, 103,
 167                 104, 105, 106, 107, 108, 109, 110, 111,
 168                 112, 113, 114, 115, 116, 117, 118, 119,
 169                 120, 121, 122, 123, 124, 125, 126, 127,
 170                 128, 129, 130, 131, 132, 133, 134, 135,
 171                 136, 137, 138, 139, 140, 141, 142, 143,
 172                 144, 145, 146, 147, 148, 149, 150, 151,
 173                 152, 153, 154, 155, 156, 157, 158, 159,
 174                 160, 161, 162, 163, 164, 165, 166, 167,
 175                 168, 169, 170, 171, 172, 173, 174, 175,
 176                 176, 177, 178, 179, 180, 181, 182, 183,
 177                 184, 185, 186, 187, 188, 189, 190, 191,
 178                 192, 193, 194, 195, 196, 197, 198, 199,
 179                 200, 201, 202, 203, 204, 205, 206, 207,
 180                 208, 209, 210, 211, 212, 213, 214, 215,
 181                 216, 217, 218, 219, 220, 221, 222, 223,
 182                 224, 225, 226, 227, 228, 229, 230, 231,
 183                 232, 233, 234, 235, 236, 237, 238, 239,
 184                 240, 241, 242, 243, 244, 245, 246, 247,
 185                 248, 249, 250, 251, 252, 253, 254, 255,
 186                 256, 257, 258, 259, 260, 261, 262, 263,
 187         },
 188         .oobfree = { {2, 6}, {264, 80} },
 189 };
 190
 191 /*
 192  * Generic flash bbt descriptors
 193  */
 194 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 195 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 196
 197 static struct nand_bbt_descr bbt_main_descr = {
 198         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 199                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 200         .offs = 2, /* 0 on 8-bit small page */
 201         .len = 4,
 202         .veroffs = 6,
 203         .maxblocks = 4,
 204         .pattern = bbt_pattern,
 205 };
 206
 207 static struct nand_bbt_descr bbt_mirror_descr = {
 208         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 209                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 210         .offs = 2, /* 0 on 8-bit small page */
 211         .len = 4,
 212         .veroffs = 6,
 213         .maxblocks = 4,
 214         .pattern = mirror_pattern,
 215 };
 216
 217 /*
 218  * Set up the IFC hardware block and page address fields, and the ifc nand
 219  * structure addr field to point to the correct IFC buffer in memory
 220  */
 221 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 222 {
 223         struct nand_chip *chip = mtd_to_nand(mtd);
 224         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 225         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 226         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 227         int buf_num;
 228
 229         ctrl->page = page_addr;
 230
 231         /* Program ROW0/COL0 */
 232         ifc_out32(&ifc->ifc_nand.row0, page_addr);
 233         ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
 234
 235         buf_num = page_addr & priv->bufnum_mask;
 236
 237         ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 238         ctrl->index = column;
 239
 240         /* for OOB data point to the second half of the buffer */
 241         if (oob)
 242                 ctrl->index += mtd->writesize;
 243 }
 244
 245 /* returns nonzero if entire page is blank */
 246 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 247                           u32 eccstat, unsigned int bufnum)
 248 {
 249         return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
 250 }
 251
 252 /*
 253  * execute IFC NAND command and wait for it to complete
 254  */
 255 static int fsl_ifc_run_command(struct mtd_info *mtd)
 256 {
 257         struct nand_chip *chip = mtd_to_nand(mtd);
 258         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 259         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 260         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 261         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 262         u32 time_start;
 263         u32 eccstat;
 264         int i;
 265
 266         /* set the chip select for NAND Transaction */
 267         ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 268
 269         /* start read/write seq */
 270         ifc_out32(&ifc->ifc_nand.nandseq_strt,
 271                   IFC_NAND_SEQ_STRT_FIR_STRT);
 272
 273         /* wait for NAND Machine complete flag or timeout */
 274         time_start = get_timer(0);
 275
 276         while (get_timer(time_start) < timeo) {
 277                 ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 278
 279                 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 280                         break;
 281         }
 282
 283         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
 284
 285         if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
 286                 printf("%s: Flash Time Out Error\n", __func__);
 287         if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
 288                 printf("%s: Write Protect Error\n", __func__);
 289
 290         if (ctrl->eccread) {
 291                 int errors;
 292                 int bufnum = ctrl->page & priv->bufnum_mask;
 293                 int sector_start = bufnum * chip->ecc.steps;
 294                 int sector_end = sector_start + chip->ecc.steps - 1;
 295                 u32 *eccstat_regs;
 296
 297                 eccstat_regs = ifc->ifc_nand.nand_eccstat;
 298                 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
 299
 300                 for (i = sector_start; i <= sector_end; i++) {
 301                         if ((i != sector_start) && !(i % 4))
 302                                 eccstat = ifc_in32(&eccstat_regs[i / 4]);
 303
 304                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 305
 306                         if (errors == 15) {
 307                                 /*
 308                                  * Uncorrectable error.
 309                                  * We'll check for blank pages later.
 310                                  *
 311                                  * We disable ECCER reporting due to erratum
 312                                  * IFC-A002770 -- so report it now if we
 313                                  * see an uncorrectable error in ECCSTAT.
 314                                  */
 315                                 ctrl->status |= IFC_NAND_EVTER_STAT_ECCER;
 316                                 continue;
 317                         }
 318
 319                         mtd->ecc_stats.corrected += errors;
 320                 }
 321
 322                 ctrl->eccread = 0;
 323         }
 324
 325         /* returns 0 on success otherwise non-zero) */
 326         return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
 327 }
 328
 329 static void fsl_ifc_do_read(struct nand_chip *chip,
 330                             int oob,
 331                             struct mtd_info *mtd)
 332 {
 333         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 334         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 335         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 336
 337         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 338         if (mtd->writesize > 512) {
 339                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 340                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 341                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 342                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 343                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 344                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
 345                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 346
 347                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 348                           (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 349                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 350         } else {
 351                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 352                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 353                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 354                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 355                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
 356
 357                 if (oob)
 358                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 359                                   NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
 360                 else
 361                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 362                                   NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 363         }
 364 }
 365
 366 /* cmdfunc send commands to the IFC NAND Machine */
 367 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 368                              int column, int page_addr)
 369 {
 370         struct nand_chip *chip = mtd_to_nand(mtd);
 371         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 372         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 373         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 374
 375         /* clear the read buffer */
 376         ctrl->read_bytes = 0;
 377         if (command != NAND_CMD_PAGEPROG)
 378                 ctrl->index = 0;
 379
 380         switch (command) {
 381         /* READ0 read the entire buffer to use hardware ECC. */
 382         case NAND_CMD_READ0: {
 383                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 384                 set_addr(mtd, 0, page_addr, 0);
 385
 386                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 387                 ctrl->index += column;
 388
 389                 if (chip->ecc.mode == NAND_ECC_HW)
 390                         ctrl->eccread = 1;
 391
 392                 fsl_ifc_do_read(chip, 0, mtd);
 393                 fsl_ifc_run_command(mtd);
 394                 return;
 395         }
 396
 397         /* READOOB reads only the OOB because no ECC is performed. */
 398         case NAND_CMD_READOOB:
 399                 ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
 400                 set_addr(mtd, column, page_addr, 1);
 401
 402                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 403
 404                 fsl_ifc_do_read(chip, 1, mtd);
 405                 fsl_ifc_run_command(mtd);
 406
 407                 return;
 408
 409         /* READID must read all possible bytes while CEB is active */
 410         case NAND_CMD_READID:
 411         case NAND_CMD_PARAM: {
 412                 int timing = IFC_FIR_OP_RB;
 413                 if (command == NAND_CMD_PARAM)
 414                         timing = IFC_FIR_OP_RBCD;
 415
 416                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 417                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 418                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 419                           (timing << IFC_NAND_FIR0_OP2_SHIFT));
 420                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 421                           command << IFC_NAND_FCR0_CMD0_SHIFT);
 422                 ifc_out32(&ifc->ifc_nand.row3, column);
 423
 424                 /*
 425                  * although currently it's 8 bytes for READID, we always read
 426                  * the maximum 256 bytes(for PARAM)
 427                  */
 428                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
 429                 ctrl->read_bytes = 256;
 430
 431                 set_addr(mtd, 0, 0, 0);
 432                 fsl_ifc_run_command(mtd);
 433                 return;
 434         }
 435
 436         /* ERASE1 stores the block and page address */
 437         case NAND_CMD_ERASE1:
 438                 set_addr(mtd, 0, page_addr, 0);
 439                 return;
 440
 441         /* ERASE2 uses the block and page address from ERASE1 */
 442         case NAND_CMD_ERASE2:
 443                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 444                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 445                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 446                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
 447
 448                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 449                           (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 450                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
 451
 452                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 453                 ctrl->read_bytes = 0;
 454                 fsl_ifc_run_command(mtd);
 455                 return;
 456
 457         /* SEQIN sets up the addr buffer and all registers except the length */
 458         case NAND_CMD_SEQIN: {
 459                 u32 nand_fcr0;
 460                 ctrl->column = column;
 461                 ctrl->oob = 0;
 462
 463                 if (mtd->writesize > 512) {
 464                         nand_fcr0 =
 465                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 466                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 467                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 468
 469                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 470                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 471                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 472                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 473                                   (IFC_FIR_OP_WBCD  <<
 474                                                 IFC_NAND_FIR0_OP3_SHIFT) |
 475                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
 476                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 477                                   (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 478                                   (IFC_FIR_OP_RDSTAT <<
 479                                         IFC_NAND_FIR1_OP6_SHIFT) |
 480                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
 481                 } else {
 482                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 483                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 484                                     (NAND_CMD_SEQIN <<
 485                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 486                                     (NAND_CMD_STATUS <<
 487                                         IFC_NAND_FCR0_CMD3_SHIFT));
 488
 489                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 490                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 491                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 492                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 493                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 494                                   (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
 495                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 496                                   (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 497                                   (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 498                                   (IFC_FIR_OP_RDSTAT <<
 499                                         IFC_NAND_FIR1_OP7_SHIFT) |
 500                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
 501
 502                         if (column >= mtd->writesize)
 503                                 nand_fcr0 |=
 504                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 505                         else
 506                                 nand_fcr0 |=
 507                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 508                 }
 509
 510                 if (column >= mtd->writesize) {
 511                         /* OOB area --> READOOB */
 512                         column -= mtd->writesize;
 513                         ctrl->oob = 1;
 514                 }
 515                 ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
 516                 set_addr(mtd, column, page_addr, ctrl->oob);
 517                 return;
 518         }
 519
 520         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 521         case NAND_CMD_PAGEPROG:
 522                 if (ctrl->oob)
 523                         ifc_out32(&ifc->ifc_nand.nand_fbcr,
 524                                   ctrl->index - ctrl->column);
 525                 else
 526                         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 527
 528                 fsl_ifc_run_command(mtd);
 529                 return;
 530
 531         case NAND_CMD_STATUS:
 532                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 533                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 534                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
 535                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 536                           NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
 537                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 538                 set_addr(mtd, 0, 0, 0);
 539                 ctrl->read_bytes = 1;
 540
 541                 fsl_ifc_run_command(mtd);
 542
 543                 /*
 544                  * The chip always seems to report that it is
 545                  * write-protected, even when it is not.
 546                  */
 547                 if (chip->options & NAND_BUSWIDTH_16)
 548                         ifc_out16(ctrl->addr,
 549                                   ifc_in16(ctrl->addr) | NAND_STATUS_WP);
 550                 else
 551                         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 552                 return;
 553
 554         case NAND_CMD_RESET:
 555                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 556                           IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
 557                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 558                           NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
 559                 fsl_ifc_run_command(mtd);
 560                 return;
 561
 562         default:
 563                 printf("%s: error, unsupported command 0x%x.\n",
 564                         __func__, command);
 565         }
 566 }
 567
 568 /*
 569  * Write buf to the IFC NAND Controller Data Buffer
 570  */
 571 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 572 {
 573         struct nand_chip *chip = mtd_to_nand(mtd);
 574         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 575         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 576         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 577
 578         if (len <= 0) {
 579                 printf("%s of %d bytes", __func__, len);
 580                 ctrl->status = 0;
 581                 return;
 582         }
 583
 584         if ((unsigned int)len > bufsize - ctrl->index) {
 585                 printf("%s beyond end of buffer "
 586                        "(%d requested, %u available)\n",
 587                         __func__, len, bufsize - ctrl->index);
 588                 len = bufsize - ctrl->index;
 589         }
 590
 591         memcpy_toio(ctrl->addr + ctrl->index, buf, len);
 592         ctrl->index += len;
 593 }
 594
 595 /*
 596  * read a byte from either the IFC hardware buffer if it has any data left
 597  * otherwise issue a command to read a single byte.
 598  */
 599 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
 600 {
 601         struct nand_chip *chip = mtd_to_nand(mtd);
 602         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 603         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 604         unsigned int offset;
 605
 606         /*
 607          * If there are still bytes in the IFC buffer, then use the
 608          * next byte.
 609          */
 610         if (ctrl->index < ctrl->read_bytes) {
 611                 offset = ctrl->index++;
 612                 return in_8(ctrl->addr + offset);
 613         }
 614
 615         printf("%s beyond end of buffer\n", __func__);
 616         return ERR_BYTE;
 617 }
 618
 619 /*
 620  * Read two bytes from the IFC hardware buffer
 621  * read function for 16-bit buswith
 622  */
 623 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 624 {
 625         struct nand_chip *chip = mtd_to_nand(mtd);
 626         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 627         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 628         uint16_t data;
 629
 630         /*
 631          * If there are still bytes in the IFC buffer, then use the
 632          * next byte.
 633          */
 634         if (ctrl->index < ctrl->read_bytes) {
 635                 data = ifc_in16(ctrl->addr + ctrl->index);
 636                 ctrl->index += 2;
 637                 return (uint8_t)data;
 638         }
 639
 640         printf("%s beyond end of buffer\n", __func__);
 641         return ERR_BYTE;
 642 }
 643
 644 /*
 645  * Read from the IFC Controller Data Buffer
 646  */
 647 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 648 {
 649         struct nand_chip *chip = mtd_to_nand(mtd);
 650         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 651         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 652         int avail;
 653
 654         if (len < 0)
 655                 return;
 656
 657         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 658         memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
 659         ctrl->index += avail;
 660
 661         if (len > avail)
 662                 printf("%s beyond end of buffer "
 663                        "(%d requested, %d available)\n",
 664                        __func__, len, avail);
 665 }
 666
 667 /* This function is called after Program and Erase Operations to
 668  * check for success or failure.
 669  */
 670 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 671 {
 672         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 673         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 674         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 675         u32 nand_fsr;
 676         int status;
 677
 678         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 679                 return NAND_STATUS_FAIL;
 680
 681         /* Use READ_STATUS command, but wait for the device to be ready */
 682         ifc_out32(&ifc->ifc_nand.nand_fir0,
 683                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 684                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
 685         ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
 686                   IFC_NAND_FCR0_CMD0_SHIFT);
 687         ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 688         set_addr(mtd, 0, 0, 0);
 689         ctrl->read_bytes = 1;
 690
 691         fsl_ifc_run_command(mtd);
 692
 693         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 694                 return NAND_STATUS_FAIL;
 695
 696         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 697         status = nand_fsr >> 24;
 698
 699         /* Chip sometimes reporting write protect even when it's not */
 700         return status | NAND_STATUS_WP;
 701 }
 702
 703 /*
 704  * The controller does not check for bitflips in erased pages,
 705  * therefore software must check instead.
 706  */
 707 static int
 708 check_erased_page(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd)
 709 {
 710         u8 *ecc = chip->oob_poi;
 711         const int ecc_size = chip->ecc.bytes;
 712         const int pkt_size = chip->ecc.size;
 713         int i, res, bitflips;
 714
 715         /* IFC starts ecc bytes at offset 8 in the spare area. */
 716         ecc += 8;
 717         bitflips = 0;
 718         for (i = 0; i < chip->ecc.steps; i++) {
 719                 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
 720                                                   NULL, 0, chip->ecc.strength);
 721
 722                 if (res < 0) {
 723                         printf("fsl-ifc: NAND Flash ECC Uncorrectable Error\n");
 724                         mtd->ecc_stats.failed++;
 725                 } else if (res > 0) {
 726                         mtd->ecc_stats.corrected += res;
 727                 }
 728                 bitflips = max(res, bitflips);
 729                 buf += pkt_size;
 730                 ecc += ecc_size;
 731         }
 732
 733         return bitflips;
 734 }
 735
 736 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 737                              uint8_t *buf, int oob_required, int page)
 738 {
 739         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 740         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 741
 742         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 743         fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 744
 745         if (ctrl->status & IFC_NAND_EVTER_STAT_ECCER)
 746                 return check_erased_page(chip, buf, mtd);
 747
 748         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 749                 mtd->ecc_stats.failed++;
 750
 751         return 0;
 752 }
 753
 754 /* ECC will be calculated automatically, and errors will be detected in
 755  * waitfunc.
 756  */
 757 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 758                                const uint8_t *buf, int oob_required, int page)
 759 {
 760         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 761         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 762
 763         return 0;
 764 }
 765
 766 static void fsl_ifc_ctrl_init(void)
 767 {
 768         uint32_t ver = 0;
 769         ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
 770         if (!ifc_ctrl)
 771                 return;
 772
 773         ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
 774
 775         ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
 776         if (ver >= FSL_IFC_V2_0_0)
 777                 ifc_ctrl->regs.rregs =
 778                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
 779         else
 780                 ifc_ctrl->regs.rregs =
 781                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
 782
 783         /* clear event registers */
 784         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
 785         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
 786
 787         /* Enable error and event for any detected errors */
 788         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
 789                   IFC_NAND_EVTER_EN_OPC_EN |
 790                   IFC_NAND_EVTER_EN_PGRDCMPL_EN |
 791                   IFC_NAND_EVTER_EN_FTOER_EN |
 792                   IFC_NAND_EVTER_EN_WPER_EN);
 793
 794         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
 795 }
 796
 797 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 798 {
 799 }
 800
 801 static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv, uint32_t ver)
 802 {
 803         struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
 804         uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
 805         uint32_t ncfgr = 0;
 806         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 807         u32 time_start;
 808
 809         if (ver > FSL_IFC_V1_1_0) {
 810                 ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
 811                 ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
 812
 813                 /* wait for  SRAM_INIT bit to be clear or timeout */
 814                 time_start = get_timer(0);
 815                 while (get_timer(time_start) < timeo) {
 816                         ifc_ctrl->status =
 817                                 ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 818
 819                         if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
 820                                 return 0;
 821                 }
 822                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 823                 return 1;
 824         }
 825
 826         cs = priv->bank;
 827
 828         /* Save CSOR and CSOR_ext */
 829         csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
 830         csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
 831
 832         /* chage PageSize 8K and SpareSize 1K*/
 833         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 834         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
 835         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
 836
 837         /* READID */
 838         ifc_out32(&ifc->ifc_nand.nand_fir0,
 839                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 840                   (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 841                   (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
 842         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 843                   NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
 844         ifc_out32(&ifc->ifc_nand.row3, 0x0);
 845
 846         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
 847
 848         /* Program ROW0/COL0 */
 849         ifc_out32(&ifc->ifc_nand.row0, 0x0);
 850         ifc_out32(&ifc->ifc_nand.col0, 0x0);
 851
 852         /* set the chip select for NAND Transaction */
 853         ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 854
 855         /* start read seq */
 856         ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
 857
 858         time_start = get_timer(0);
 859
 860         while (get_timer(time_start) < timeo) {
 861                 ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 862
 863                 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 864                         break;
 865         }
 866
 867         if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
 868                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 869                 return 1;
 870         }
 871
 872         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 873
 874         /* Restore CSOR and CSOR_ext */
 875         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
 876         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
 877
 878         return 0;
 879 }
 880
 881 static int fsl_ifc_chip_init(int devnum, u8 *addr)
 882 {
 883         struct mtd_info *mtd;
 884         struct nand_chip *nand;
 885         struct fsl_ifc_mtd *priv;
 886         struct nand_ecclayout *layout;
 887         struct fsl_ifc_fcm *gregs = NULL;
 888         uint32_t cspr = 0, csor = 0, ver = 0;
 889         int ret = 0;
 890
 891         if (!ifc_ctrl) {
 892                 fsl_ifc_ctrl_init();
 893                 if (!ifc_ctrl)
 894                         return -1;
 895         }
 896
 897         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 898         if (!priv)
 899                 return -ENOMEM;
 900
 901         priv->ctrl = ifc_ctrl;
 902         priv->vbase = addr;
 903         gregs = ifc_ctrl->regs.gregs;
 904
 905         /* Find which chip select it is connected to.
 906          */
 907         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 908                 phys_addr_t phys_addr = virt_to_phys(addr);
 909
 910                 cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
 911                 csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
 912
 913                 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 914                     (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
 915                         break;
 916         }
 917
 918         if (priv->bank >= MAX_BANKS) {
 919                 printf("%s: address did not match any "
 920                        "chip selects\n", __func__);
 921                 kfree(priv);
 922                 return -ENODEV;
 923         }
 924
 925         nand = &priv->chip;
 926         mtd = nand_to_mtd(nand);
 927
 928         ifc_ctrl->chips[priv->bank] = priv;
 929
 930         /* fill in nand_chip structure */
 931         /* set up function call table */
 932
 933         nand->write_buf = fsl_ifc_write_buf;
 934         nand->read_buf = fsl_ifc_read_buf;
 935         nand->select_chip = fsl_ifc_select_chip;
 936         nand->cmdfunc = fsl_ifc_cmdfunc;
 937         nand->waitfunc = fsl_ifc_wait;
 938
 939         /* set up nand options */
 940         nand->bbt_td = &bbt_main_descr;
 941         nand->bbt_md = &bbt_mirror_descr;
 942
 943         /* set up nand options */
 944         nand->options = NAND_NO_SUBPAGE_WRITE;
 945         nand->bbt_options = NAND_BBT_USE_FLASH;
 946
 947         if (cspr & CSPR_PORT_SIZE_16) {
 948                 nand->read_byte = fsl_ifc_read_byte16;
 949                 nand->options |= NAND_BUSWIDTH_16;
 950         } else {
 951                 nand->read_byte = fsl_ifc_read_byte;
 952         }
 953
 954         nand->controller = &ifc_ctrl->controller;
 955         nand_set_controller_data(nand, priv);
 956
 957         nand->ecc.read_page = fsl_ifc_read_page;
 958         nand->ecc.write_page = fsl_ifc_write_page;
 959
 960         /* Hardware generates ECC per 512 Bytes */
 961         nand->ecc.size = 512;
 962         nand->ecc.bytes = 8;
 963
 964         switch (csor & CSOR_NAND_PGS_MASK) {
 965         case CSOR_NAND_PGS_512:
 966                 if (nand->options & NAND_BUSWIDTH_16) {
 967                         layout = &oob_512_16bit_ecc4;
 968                 } else {
 969                         layout = &oob_512_8bit_ecc4;
 970
 971                         /* Avoid conflict with bad block marker */
 972                         bbt_main_descr.offs = 0;
 973                         bbt_mirror_descr.offs = 0;
 974                 }
 975
 976                 nand->ecc.strength = 4;
 977                 priv->bufnum_mask = 15;
 978                 break;
 979
 980         case CSOR_NAND_PGS_2K:
 981                 layout = &oob_2048_ecc4;
 982                 nand->ecc.strength = 4;
 983                 priv->bufnum_mask = 3;
 984                 break;
 985
 986         case CSOR_NAND_PGS_4K:
 987                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 988                     CSOR_NAND_ECC_MODE_4) {
 989                         layout = &oob_4096_ecc4;
 990                         nand->ecc.strength = 4;
 991                 } else {
 992                         layout = &oob_4096_ecc8;
 993                         nand->ecc.strength = 8;
 994                         nand->ecc.bytes = 16;
 995                 }
 996
 997                 priv->bufnum_mask = 1;
 998                 break;
 999
1000         case CSOR_NAND_PGS_8K:
1001                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1002                     CSOR_NAND_ECC_MODE_4) {
1003                         layout = &oob_8192_ecc4;
1004                         nand->ecc.strength = 4;
1005                 } else {
1006                         layout = &oob_8192_ecc8;
1007                         nand->ecc.strength = 8;
1008                         nand->ecc.bytes = 16;
1009                 }
1010
1011                 priv->bufnum_mask = 0;
1012                 break;
1013
1014
1015         default:
1016                 printf("ifc nand: bad csor %#x: bad page size\n", csor);
1017                 return -ENODEV;
1018         }
1019
1020         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
1021         if (csor & CSOR_NAND_ECC_DEC_EN) {
1022                 nand->ecc.mode = NAND_ECC_HW;
1023                 nand->ecc.layout = layout;
1024         } else {
1025                 nand->ecc.mode = NAND_ECC_SOFT;
1026         }
1027
1028         ver = ifc_in32(&gregs->ifc_rev);
1029         if (ver >= FSL_IFC_V1_1_0)
1030                 ret = fsl_ifc_sram_init(priv, ver);
1031         if (ret)
1032                 return ret;
1033
1034         if (ver >= FSL_IFC_V2_0_0)
1035                 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
1036
1037         ret = nand_scan_ident(mtd, 1, NULL);
1038         if (ret)
1039                 return ret;
1040
1041         ret = nand_scan_tail(mtd);
1042         if (ret)
1043                 return ret;
1044
1045         ret = nand_register(devnum, mtd);
1046         if (ret)
1047                 return ret;
1048         return 0;
1049 }
1050
1051 #ifndef CONFIG_SYS_NAND_BASE_LIST
1052 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1053 #endif
1054
1055 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
1056         CONFIG_SYS_NAND_BASE_LIST;
1057
1058 void board_nand_init(void)
1059 {
1060         int i;
1061
1062         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1063                 fsl_ifc_chip_init(i, (u8 *)base_address[i]);
1064 }