drivers/mtd/nand/raw/fsl_ifc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Integrated Flash Controller NAND Machine Driver
   3  *
   4  * Copyright (c) 2012 Freescale Semiconductor, Inc
   5  *
   6  * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <malloc.h>
  12 #include <nand.h>
  13 #include <dm/devres.h>
  14
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/rawnand.h>
  17 #include <linux/mtd/nand_ecc.h>
  18
  19 #include <asm/io.h>
  20 #include <linux/errno.h>
  21 #include <fsl_ifc.h>
  22
  23 #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  24 #define CONFIG_SYS_FSL_IFC_BANK_COUNT   4
  25 #endif
  26
  27 #define MAX_BANKS       CONFIG_SYS_FSL_IFC_BANK_COUNT
  28 #define ERR_BYTE        0xFF /* Value returned for read bytes
  29                                 when read failed */
  30
  31 struct fsl_ifc_ctrl;
  32
  33 /* mtd information per set */
  34 struct fsl_ifc_mtd {
  35         struct nand_chip chip;
  36         struct fsl_ifc_ctrl *ctrl;
  37
  38         struct device *dev;
  39         int bank;               /* Chip select bank number                */
  40         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  41         u8 __iomem *vbase;      /* Chip select base virtual address       */
  42 };
  43
  44 /* overview of the fsl ifc controller */
  45 struct fsl_ifc_ctrl {
  46         struct nand_hw_control controller;
  47         struct fsl_ifc_mtd *chips[MAX_BANKS];
  48
  49         /* device info */
  50         struct fsl_ifc regs;
  51         void __iomem *addr;      /* Address of assigned IFC buffer        */
  52         unsigned int page;       /* Last page written to / read from      */
  53         unsigned int read_bytes; /* Number of bytes read during command   */
  54         unsigned int column;     /* Saved column from SEQIN               */
  55         unsigned int index;      /* Pointer to next byte to 'read'        */
  56         unsigned int status;     /* status read from NEESR after last op  */
  57         unsigned int oob;        /* Non zero if operating on OOB data     */
  58         unsigned int eccread;    /* Non zero for a full-page ECC read     */
  59 };
  60
  61 static struct fsl_ifc_ctrl *ifc_ctrl;
  62
  63 /* 512-byte page with 4-bit ECC, 8-bit */
  64 static struct nand_ecclayout oob_512_8bit_ecc4 = {
  65         .eccbytes = 8,
  66         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  67         .oobfree = { {0, 5}, {6, 2} },
  68 };
  69
  70 /* 512-byte page with 4-bit ECC, 16-bit */
  71 static struct nand_ecclayout oob_512_16bit_ecc4 = {
  72         .eccbytes = 8,
  73         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  74         .oobfree = { {2, 6}, },
  75 };
  76
  77 /* 2048-byte page size with 4-bit ECC */
  78 static struct nand_ecclayout oob_2048_ecc4 = {
  79         .eccbytes = 32,
  80         .eccpos = {
  81                 8, 9, 10, 11, 12, 13, 14, 15,
  82                 16, 17, 18, 19, 20, 21, 22, 23,
  83                 24, 25, 26, 27, 28, 29, 30, 31,
  84                 32, 33, 34, 35, 36, 37, 38, 39,
  85         },
  86         .oobfree = { {2, 6}, {40, 24} },
  87 };
  88
  89 /* 4096-byte page size with 4-bit ECC */
  90 static struct nand_ecclayout oob_4096_ecc4 = {
  91         .eccbytes = 64,
  92         .eccpos = {
  93                 8, 9, 10, 11, 12, 13, 14, 15,
  94                 16, 17, 18, 19, 20, 21, 22, 23,
  95                 24, 25, 26, 27, 28, 29, 30, 31,
  96                 32, 33, 34, 35, 36, 37, 38, 39,
  97                 40, 41, 42, 43, 44, 45, 46, 47,
  98                 48, 49, 50, 51, 52, 53, 54, 55,
  99                 56, 57, 58, 59, 60, 61, 62, 63,
 100                 64, 65, 66, 67, 68, 69, 70, 71,
 101         },
 102         .oobfree = { {2, 6}, {72, 56} },
 103 };
 104
 105 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
 106 static struct nand_ecclayout oob_4096_ecc8 = {
 107         .eccbytes = 128,
 108         .eccpos = {
 109                 8, 9, 10, 11, 12, 13, 14, 15,
 110                 16, 17, 18, 19, 20, 21, 22, 23,
 111                 24, 25, 26, 27, 28, 29, 30, 31,
 112                 32, 33, 34, 35, 36, 37, 38, 39,
 113                 40, 41, 42, 43, 44, 45, 46, 47,
 114                 48, 49, 50, 51, 52, 53, 54, 55,
 115                 56, 57, 58, 59, 60, 61, 62, 63,
 116                 64, 65, 66, 67, 68, 69, 70, 71,
 117                 72, 73, 74, 75, 76, 77, 78, 79,
 118                 80, 81, 82, 83, 84, 85, 86, 87,
 119                 88, 89, 90, 91, 92, 93, 94, 95,
 120                 96, 97, 98, 99, 100, 101, 102, 103,
 121                 104, 105, 106, 107, 108, 109, 110, 111,
 122                 112, 113, 114, 115, 116, 117, 118, 119,
 123                 120, 121, 122, 123, 124, 125, 126, 127,
 124                 128, 129, 130, 131, 132, 133, 134, 135,
 125         },
 126         .oobfree = { {2, 6}, {136, 82} },
 127 };
 128
 129 /* 8192-byte page size with 4-bit ECC */
 130 static struct nand_ecclayout oob_8192_ecc4 = {
 131         .eccbytes = 128,
 132         .eccpos = {
 133                 8, 9, 10, 11, 12, 13, 14, 15,
 134                 16, 17, 18, 19, 20, 21, 22, 23,
 135                 24, 25, 26, 27, 28, 29, 30, 31,
 136                 32, 33, 34, 35, 36, 37, 38, 39,
 137                 40, 41, 42, 43, 44, 45, 46, 47,
 138                 48, 49, 50, 51, 52, 53, 54, 55,
 139                 56, 57, 58, 59, 60, 61, 62, 63,
 140                 64, 65, 66, 67, 68, 69, 70, 71,
 141                 72, 73, 74, 75, 76, 77, 78, 79,
 142                 80, 81, 82, 83, 84, 85, 86, 87,
 143                 88, 89, 90, 91, 92, 93, 94, 95,
 144                 96, 97, 98, 99, 100, 101, 102, 103,
 145                 104, 105, 106, 107, 108, 109, 110, 111,
 146                 112, 113, 114, 115, 116, 117, 118, 119,
 147                 120, 121, 122, 123, 124, 125, 126, 127,
 148                 128, 129, 130, 131, 132, 133, 134, 135,
 149         },
 150         .oobfree = { {2, 6}, {136, 208} },
 151 };
 152
 153 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
 154 static struct nand_ecclayout oob_8192_ecc8 = {
 155         .eccbytes = 256,
 156         .eccpos = {
 157                 8, 9, 10, 11, 12, 13, 14, 15,
 158                 16, 17, 18, 19, 20, 21, 22, 23,
 159                 24, 25, 26, 27, 28, 29, 30, 31,
 160                 32, 33, 34, 35, 36, 37, 38, 39,
 161                 40, 41, 42, 43, 44, 45, 46, 47,
 162                 48, 49, 50, 51, 52, 53, 54, 55,
 163                 56, 57, 58, 59, 60, 61, 62, 63,
 164                 64, 65, 66, 67, 68, 69, 70, 71,
 165                 72, 73, 74, 75, 76, 77, 78, 79,
 166                 80, 81, 82, 83, 84, 85, 86, 87,
 167                 88, 89, 90, 91, 92, 93, 94, 95,
 168                 96, 97, 98, 99, 100, 101, 102, 103,
 169                 104, 105, 106, 107, 108, 109, 110, 111,
 170                 112, 113, 114, 115, 116, 117, 118, 119,
 171                 120, 121, 122, 123, 124, 125, 126, 127,
 172                 128, 129, 130, 131, 132, 133, 134, 135,
 173                 136, 137, 138, 139, 140, 141, 142, 143,
 174                 144, 145, 146, 147, 148, 149, 150, 151,
 175                 152, 153, 154, 155, 156, 157, 158, 159,
 176                 160, 161, 162, 163, 164, 165, 166, 167,
 177                 168, 169, 170, 171, 172, 173, 174, 175,
 178                 176, 177, 178, 179, 180, 181, 182, 183,
 179                 184, 185, 186, 187, 188, 189, 190, 191,
 180                 192, 193, 194, 195, 196, 197, 198, 199,
 181                 200, 201, 202, 203, 204, 205, 206, 207,
 182                 208, 209, 210, 211, 212, 213, 214, 215,
 183                 216, 217, 218, 219, 220, 221, 222, 223,
 184                 224, 225, 226, 227, 228, 229, 230, 231,
 185                 232, 233, 234, 235, 236, 237, 238, 239,
 186                 240, 241, 242, 243, 244, 245, 246, 247,
 187                 248, 249, 250, 251, 252, 253, 254, 255,
 188                 256, 257, 258, 259, 260, 261, 262, 263,
 189         },
 190         .oobfree = { {2, 6}, {264, 80} },
 191 };
 192
 193 /*
 194  * Generic flash bbt descriptors
 195  */
 196 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 197 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 198
 199 static struct nand_bbt_descr bbt_main_descr = {
 200         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 201                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 202         .offs = 2, /* 0 on 8-bit small page */
 203         .len = 4,
 204         .veroffs = 6,
 205         .maxblocks = 4,
 206         .pattern = bbt_pattern,
 207 };
 208
 209 static struct nand_bbt_descr bbt_mirror_descr = {
 210         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 211                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 212         .offs = 2, /* 0 on 8-bit small page */
 213         .len = 4,
 214         .veroffs = 6,
 215         .maxblocks = 4,
 216         .pattern = mirror_pattern,
 217 };
 218
 219 /*
 220  * Set up the IFC hardware block and page address fields, and the ifc nand
 221  * structure addr field to point to the correct IFC buffer in memory
 222  */
 223 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 224 {
 225         struct nand_chip *chip = mtd_to_nand(mtd);
 226         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 227         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 228         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 229         int buf_num;
 230
 231         ctrl->page = page_addr;
 232
 233         /* Program ROW0/COL0 */
 234         ifc_out32(&ifc->ifc_nand.row0, page_addr);
 235         ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
 236
 237         buf_num = page_addr & priv->bufnum_mask;
 238
 239         ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 240         ctrl->index = column;
 241
 242         /* for OOB data point to the second half of the buffer */
 243         if (oob)
 244                 ctrl->index += mtd->writesize;
 245 }
 246
 247 /* returns nonzero if entire page is blank */
 248 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 249                           u32 eccstat, unsigned int bufnum)
 250 {
 251         return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
 252 }
 253
 254 /*
 255  * execute IFC NAND command and wait for it to complete
 256  */
 257 static int fsl_ifc_run_command(struct mtd_info *mtd)
 258 {
 259         struct nand_chip *chip = mtd_to_nand(mtd);
 260         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 261         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 262         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 263         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 264         u32 time_start;
 265         u32 eccstat;
 266         int i;
 267
 268         /* set the chip select for NAND Transaction */
 269         ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 270
 271         /* start read/write seq */
 272         ifc_out32(&ifc->ifc_nand.nandseq_strt,
 273                   IFC_NAND_SEQ_STRT_FIR_STRT);
 274
 275         /* wait for NAND Machine complete flag or timeout */
 276         time_start = get_timer(0);
 277
 278         while (get_timer(time_start) < timeo) {
 279                 ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 280
 281                 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 282                         break;
 283         }
 284
 285         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
 286
 287         if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
 288                 printf("%s: Flash Time Out Error\n", __func__);
 289         if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
 290                 printf("%s: Write Protect Error\n", __func__);
 291
 292         if (ctrl->eccread) {
 293                 int errors;
 294                 int bufnum = ctrl->page & priv->bufnum_mask;
 295                 int sector_start = bufnum * chip->ecc.steps;
 296                 int sector_end = sector_start + chip->ecc.steps - 1;
 297                 u32 *eccstat_regs;
 298
 299                 eccstat_regs = ifc->ifc_nand.nand_eccstat;
 300                 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
 301
 302                 for (i = sector_start; i <= sector_end; i++) {
 303                         if ((i != sector_start) && !(i % 4))
 304                                 eccstat = ifc_in32(&eccstat_regs[i / 4]);
 305
 306                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 307
 308                         if (errors == 15) {
 309                                 /*
 310                                  * Uncorrectable error.
 311                                  * We'll check for blank pages later.
 312                                  *
 313                                  * We disable ECCER reporting due to erratum
 314                                  * IFC-A002770 -- so report it now if we
 315                                  * see an uncorrectable error in ECCSTAT.
 316                                  */
 317                                 ctrl->status |= IFC_NAND_EVTER_STAT_ECCER;
 318                                 continue;
 319                         }
 320
 321                         mtd->ecc_stats.corrected += errors;
 322                 }
 323
 324                 ctrl->eccread = 0;
 325         }
 326
 327         /* returns 0 on success otherwise non-zero) */
 328         return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
 329 }
 330
 331 static void fsl_ifc_do_read(struct nand_chip *chip,
 332                             int oob,
 333                             struct mtd_info *mtd)
 334 {
 335         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 336         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 337         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 338
 339         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 340         if (mtd->writesize > 512) {
 341                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 342                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 343                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 344                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 345                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 346                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
 347                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 348
 349                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 350                           (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 351                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 352         } else {
 353                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 354                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 355                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 356                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 357                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
 358
 359                 if (oob)
 360                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 361                                   NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
 362                 else
 363                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 364                                   NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 365         }
 366 }
 367
 368 /* cmdfunc send commands to the IFC NAND Machine */
 369 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 370                              int column, int page_addr)
 371 {
 372         struct nand_chip *chip = mtd_to_nand(mtd);
 373         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 374         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 375         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 376
 377         /* clear the read buffer */
 378         ctrl->read_bytes = 0;
 379         if (command != NAND_CMD_PAGEPROG)
 380                 ctrl->index = 0;
 381
 382         switch (command) {
 383         /* READ0 read the entire buffer to use hardware ECC. */
 384         case NAND_CMD_READ0: {
 385                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 386                 set_addr(mtd, 0, page_addr, 0);
 387
 388                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 389                 ctrl->index += column;
 390
 391                 if (chip->ecc.mode == NAND_ECC_HW)
 392                         ctrl->eccread = 1;
 393
 394                 fsl_ifc_do_read(chip, 0, mtd);
 395                 fsl_ifc_run_command(mtd);
 396                 return;
 397         }
 398
 399         /* READOOB reads only the OOB because no ECC is performed. */
 400         case NAND_CMD_READOOB:
 401                 ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
 402                 set_addr(mtd, column, page_addr, 1);
 403
 404                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 405
 406                 fsl_ifc_do_read(chip, 1, mtd);
 407                 fsl_ifc_run_command(mtd);
 408
 409                 return;
 410
 411         /* READID must read all possible bytes while CEB is active */
 412         case NAND_CMD_READID:
 413         case NAND_CMD_PARAM: {
 414                 /*
 415                  * For READID, read 8 bytes that are currently used.
 416                  * For PARAM, read all 3 copies of 256-bytes pages.
 417                  */
 418                 int len = 8;
 419                 int timing = IFC_FIR_OP_RB;
 420                 if (command == NAND_CMD_PARAM) {
 421                         timing = IFC_FIR_OP_RBCD;
 422                         len = 256 * 3;
 423                 }
 424
 425                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 426                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 427                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 428                           (timing << IFC_NAND_FIR0_OP2_SHIFT));
 429                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 430                           command << IFC_NAND_FCR0_CMD0_SHIFT);
 431                 ifc_out32(&ifc->ifc_nand.row3, column);
 432
 433                 ifc_out32(&ifc->ifc_nand.nand_fbcr, len);
 434                 ctrl->read_bytes = len;
 435
 436                 set_addr(mtd, 0, 0, 0);
 437                 fsl_ifc_run_command(mtd);
 438                 return;
 439         }
 440
 441         /* ERASE1 stores the block and page address */
 442         case NAND_CMD_ERASE1:
 443                 set_addr(mtd, 0, page_addr, 0);
 444                 return;
 445
 446         /* ERASE2 uses the block and page address from ERASE1 */
 447         case NAND_CMD_ERASE2:
 448                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 449                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 450                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 451                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
 452
 453                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 454                           (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 455                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
 456
 457                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 458                 ctrl->read_bytes = 0;
 459                 fsl_ifc_run_command(mtd);
 460                 return;
 461
 462         /* SEQIN sets up the addr buffer and all registers except the length */
 463         case NAND_CMD_SEQIN: {
 464                 u32 nand_fcr0;
 465                 ctrl->column = column;
 466                 ctrl->oob = 0;
 467
 468                 if (mtd->writesize > 512) {
 469                         nand_fcr0 =
 470                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 471                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 472                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 473
 474                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 475                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 476                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 477                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 478                                   (IFC_FIR_OP_WBCD  <<
 479                                                 IFC_NAND_FIR0_OP3_SHIFT) |
 480                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
 481                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 482                                   (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 483                                   (IFC_FIR_OP_RDSTAT <<
 484                                         IFC_NAND_FIR1_OP6_SHIFT) |
 485                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
 486                 } else {
 487                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 488                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 489                                     (NAND_CMD_SEQIN <<
 490                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 491                                     (NAND_CMD_STATUS <<
 492                                         IFC_NAND_FCR0_CMD3_SHIFT));
 493
 494                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 495                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 496                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 497                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 498                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 499                                   (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
 500                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 501                                   (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 502                                   (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 503                                   (IFC_FIR_OP_RDSTAT <<
 504                                         IFC_NAND_FIR1_OP7_SHIFT) |
 505                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
 506
 507                         if (column >= mtd->writesize)
 508                                 nand_fcr0 |=
 509                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 510                         else
 511                                 nand_fcr0 |=
 512                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 513                 }
 514
 515                 if (column >= mtd->writesize) {
 516                         /* OOB area --> READOOB */
 517                         column -= mtd->writesize;
 518                         ctrl->oob = 1;
 519                 }
 520                 ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
 521                 set_addr(mtd, column, page_addr, ctrl->oob);
 522                 return;
 523         }
 524
 525         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 526         case NAND_CMD_PAGEPROG:
 527                 if (ctrl->oob)
 528                         ifc_out32(&ifc->ifc_nand.nand_fbcr,
 529                                   ctrl->index - ctrl->column);
 530                 else
 531                         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 532
 533                 fsl_ifc_run_command(mtd);
 534                 return;
 535
 536         case NAND_CMD_STATUS:
 537                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 538                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 539                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
 540                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 541                           NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
 542                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 543                 set_addr(mtd, 0, 0, 0);
 544                 ctrl->read_bytes = 1;
 545
 546                 fsl_ifc_run_command(mtd);
 547
 548                 /*
 549                  * The chip always seems to report that it is
 550                  * write-protected, even when it is not.
 551                  */
 552                 if (chip->options & NAND_BUSWIDTH_16)
 553                         ifc_out16(ctrl->addr,
 554                                   ifc_in16(ctrl->addr) | NAND_STATUS_WP);
 555                 else
 556                         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 557                 return;
 558
 559         case NAND_CMD_RESET:
 560                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 561                           IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
 562                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 563                           NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
 564                 fsl_ifc_run_command(mtd);
 565                 return;
 566
 567         default:
 568                 printf("%s: error, unsupported command 0x%x.\n",
 569                         __func__, command);
 570         }
 571 }
 572
 573 /*
 574  * Write buf to the IFC NAND Controller Data Buffer
 575  */
 576 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 577 {
 578         struct nand_chip *chip = mtd_to_nand(mtd);
 579         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 580         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 581         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 582
 583         if (len <= 0) {
 584                 printf("%s of %d bytes", __func__, len);
 585                 ctrl->status = 0;
 586                 return;
 587         }
 588
 589         if ((unsigned int)len > bufsize - ctrl->index) {
 590                 printf("%s beyond end of buffer "
 591                        "(%d requested, %u available)\n",
 592                         __func__, len, bufsize - ctrl->index);
 593                 len = bufsize - ctrl->index;
 594         }
 595
 596         memcpy_toio(ctrl->addr + ctrl->index, buf, len);
 597         ctrl->index += len;
 598 }
 599
 600 /*
 601  * read a byte from either the IFC hardware buffer if it has any data left
 602  * otherwise issue a command to read a single byte.
 603  */
 604 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
 605 {
 606         struct nand_chip *chip = mtd_to_nand(mtd);
 607         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 608         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 609         unsigned int offset;
 610
 611         /*
 612          * If there are still bytes in the IFC buffer, then use the
 613          * next byte.
 614          */
 615         if (ctrl->index < ctrl->read_bytes) {
 616                 offset = ctrl->index++;
 617                 return in_8(ctrl->addr + offset);
 618         }
 619
 620         printf("%s beyond end of buffer\n", __func__);
 621         return ERR_BYTE;
 622 }
 623
 624 /*
 625  * Read two bytes from the IFC hardware buffer
 626  * read function for 16-bit buswith
 627  */
 628 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 629 {
 630         struct nand_chip *chip = mtd_to_nand(mtd);
 631         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 632         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 633         uint16_t data;
 634
 635         /*
 636          * If there are still bytes in the IFC buffer, then use the
 637          * next byte.
 638          */
 639         if (ctrl->index < ctrl->read_bytes) {
 640                 data = ifc_in16(ctrl->addr + ctrl->index);
 641                 ctrl->index += 2;
 642                 return (uint8_t)data;
 643         }
 644
 645         printf("%s beyond end of buffer\n", __func__);
 646         return ERR_BYTE;
 647 }
 648
 649 /*
 650  * Read from the IFC Controller Data Buffer
 651  */
 652 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 653 {
 654         struct nand_chip *chip = mtd_to_nand(mtd);
 655         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 656         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 657         int avail;
 658
 659         if (len < 0)
 660                 return;
 661
 662         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 663         memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
 664         ctrl->index += avail;
 665
 666         if (len > avail)
 667                 printf("%s beyond end of buffer "
 668                        "(%d requested, %d available)\n",
 669                        __func__, len, avail);
 670 }
 671
 672 /* This function is called after Program and Erase Operations to
 673  * check for success or failure.
 674  */
 675 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 676 {
 677         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 678         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 679         struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 680         u32 nand_fsr;
 681         int status;
 682
 683         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 684                 return NAND_STATUS_FAIL;
 685
 686         /* Use READ_STATUS command, but wait for the device to be ready */
 687         ifc_out32(&ifc->ifc_nand.nand_fir0,
 688                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 689                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
 690         ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
 691                   IFC_NAND_FCR0_CMD0_SHIFT);
 692         ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 693         set_addr(mtd, 0, 0, 0);
 694         ctrl->read_bytes = 1;
 695
 696         fsl_ifc_run_command(mtd);
 697
 698         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 699                 return NAND_STATUS_FAIL;
 700
 701         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 702         status = nand_fsr >> 24;
 703
 704         /* Chip sometimes reporting write protect even when it's not */
 705         return status | NAND_STATUS_WP;
 706 }
 707
 708 /*
 709  * The controller does not check for bitflips in erased pages,
 710  * therefore software must check instead.
 711  */
 712 static int
 713 check_erased_page(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd)
 714 {
 715         u8 *ecc = chip->oob_poi;
 716         const int ecc_size = chip->ecc.bytes;
 717         const int pkt_size = chip->ecc.size;
 718         int i, res, bitflips;
 719
 720         /* IFC starts ecc bytes at offset 8 in the spare area. */
 721         ecc += 8;
 722         bitflips = 0;
 723         for (i = 0; i < chip->ecc.steps; i++) {
 724                 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
 725                                                   NULL, 0, chip->ecc.strength);
 726
 727                 if (res < 0) {
 728                         printf("fsl-ifc: NAND Flash ECC Uncorrectable Error\n");
 729                         mtd->ecc_stats.failed++;
 730                 } else if (res > 0) {
 731                         mtd->ecc_stats.corrected += res;
 732                 }
 733                 bitflips = max(res, bitflips);
 734                 buf += pkt_size;
 735                 ecc += ecc_size;
 736         }
 737
 738         return bitflips;
 739 }
 740
 741 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 742                              uint8_t *buf, int oob_required, int page)
 743 {
 744         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 745         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 746
 747         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 748         fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 749
 750         if (ctrl->status & IFC_NAND_EVTER_STAT_ECCER)
 751                 return check_erased_page(chip, buf, mtd);
 752
 753         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 754                 mtd->ecc_stats.failed++;
 755
 756         return 0;
 757 }
 758
 759 /* ECC will be calculated automatically, and errors will be detected in
 760  * waitfunc.
 761  */
 762 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 763                                const uint8_t *buf, int oob_required, int page)
 764 {
 765         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 766         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 767
 768         return 0;
 769 }
 770
 771 static void fsl_ifc_ctrl_init(void)
 772 {
 773         uint32_t ver = 0;
 774         ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
 775         if (!ifc_ctrl)
 776                 return;
 777
 778         ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
 779
 780         ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
 781         if (ver >= FSL_IFC_V2_0_0)
 782                 ifc_ctrl->regs.rregs =
 783                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
 784         else
 785                 ifc_ctrl->regs.rregs =
 786                         (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
 787
 788         /* clear event registers */
 789         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
 790         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
 791
 792         /* Enable error and event for any detected errors */
 793         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
 794                   IFC_NAND_EVTER_EN_OPC_EN |
 795                   IFC_NAND_EVTER_EN_PGRDCMPL_EN |
 796                   IFC_NAND_EVTER_EN_FTOER_EN |
 797                   IFC_NAND_EVTER_EN_WPER_EN);
 798
 799         ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
 800 }
 801
 802 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 803 {
 804 }
 805
 806 static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv, uint32_t ver)
 807 {
 808         struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
 809         uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
 810         uint32_t ncfgr = 0;
 811         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 812         u32 time_start;
 813
 814         if (ver > FSL_IFC_V1_1_0) {
 815                 ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
 816                 ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
 817
 818                 /* wait for  SRAM_INIT bit to be clear or timeout */
 819                 time_start = get_timer(0);
 820                 while (get_timer(time_start) < timeo) {
 821                         ifc_ctrl->status =
 822                                 ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 823
 824                         if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
 825                                 return 0;
 826                 }
 827                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 828                 return 1;
 829         }
 830
 831         cs = priv->bank;
 832
 833         /* Save CSOR and CSOR_ext */
 834         csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
 835         csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
 836
 837         /* chage PageSize 8K and SpareSize 1K*/
 838         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 839         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
 840         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
 841
 842         /* READID */
 843         ifc_out32(&ifc->ifc_nand.nand_fir0,
 844                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 845                   (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 846                   (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
 847         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 848                   NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
 849         ifc_out32(&ifc->ifc_nand.row3, 0x0);
 850
 851         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
 852
 853         /* Program ROW0/COL0 */
 854         ifc_out32(&ifc->ifc_nand.row0, 0x0);
 855         ifc_out32(&ifc->ifc_nand.col0, 0x0);
 856
 857         /* set the chip select for NAND Transaction */
 858         ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 859
 860         /* start read seq */
 861         ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
 862
 863         time_start = get_timer(0);
 864
 865         while (get_timer(time_start) < timeo) {
 866                 ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 867
 868                 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 869                         break;
 870         }
 871
 872         if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
 873                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 874                 return 1;
 875         }
 876
 877         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 878
 879         /* Restore CSOR and CSOR_ext */
 880         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
 881         ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
 882
 883         return 0;
 884 }
 885
 886 static int fsl_ifc_chip_init(int devnum, u8 *addr)
 887 {
 888         struct mtd_info *mtd;
 889         struct nand_chip *nand;
 890         struct fsl_ifc_mtd *priv;
 891         struct nand_ecclayout *layout;
 892         struct fsl_ifc_fcm *gregs = NULL;
 893         uint32_t cspr = 0, csor = 0, ver = 0;
 894         int ret = 0;
 895
 896         if (!ifc_ctrl) {
 897                 fsl_ifc_ctrl_init();
 898                 if (!ifc_ctrl)
 899                         return -1;
 900         }
 901
 902         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 903         if (!priv)
 904                 return -ENOMEM;
 905
 906         priv->ctrl = ifc_ctrl;
 907         priv->vbase = addr;
 908         gregs = ifc_ctrl->regs.gregs;
 909
 910         /* Find which chip select it is connected to.
 911          */
 912         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 913                 phys_addr_t phys_addr = virt_to_phys(addr);
 914
 915                 cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
 916                 csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
 917
 918                 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 919                     (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
 920                         break;
 921         }
 922
 923         if (priv->bank >= MAX_BANKS) {
 924                 printf("%s: address did not match any "
 925                        "chip selects\n", __func__);
 926                 kfree(priv);
 927                 return -ENODEV;
 928         }
 929
 930         nand = &priv->chip;
 931         mtd = nand_to_mtd(nand);
 932
 933         ifc_ctrl->chips[priv->bank] = priv;
 934
 935         /* fill in nand_chip structure */
 936         /* set up function call table */
 937
 938         nand->write_buf = fsl_ifc_write_buf;
 939         nand->read_buf = fsl_ifc_read_buf;
 940         nand->select_chip = fsl_ifc_select_chip;
 941         nand->cmdfunc = fsl_ifc_cmdfunc;
 942         nand->waitfunc = fsl_ifc_wait;
 943
 944         /* set up nand options */
 945         nand->bbt_td = &bbt_main_descr;
 946         nand->bbt_md = &bbt_mirror_descr;
 947
 948         /* set up nand options */
 949         nand->options = NAND_NO_SUBPAGE_WRITE;
 950         nand->bbt_options = NAND_BBT_USE_FLASH;
 951
 952         if (cspr & CSPR_PORT_SIZE_16) {
 953                 nand->read_byte = fsl_ifc_read_byte16;
 954                 nand->options |= NAND_BUSWIDTH_16;
 955         } else {
 956                 nand->read_byte = fsl_ifc_read_byte;
 957         }
 958
 959         nand->controller = &ifc_ctrl->controller;
 960         nand_set_controller_data(nand, priv);
 961
 962         nand->ecc.read_page = fsl_ifc_read_page;
 963         nand->ecc.write_page = fsl_ifc_write_page;
 964
 965         /* Hardware generates ECC per 512 Bytes */
 966         nand->ecc.size = 512;
 967         nand->ecc.bytes = 8;
 968
 969         switch (csor & CSOR_NAND_PGS_MASK) {
 970         case CSOR_NAND_PGS_512:
 971                 if (nand->options & NAND_BUSWIDTH_16) {
 972                         layout = &oob_512_16bit_ecc4;
 973                 } else {
 974                         layout = &oob_512_8bit_ecc4;
 975
 976                         /* Avoid conflict with bad block marker */
 977                         bbt_main_descr.offs = 0;
 978                         bbt_mirror_descr.offs = 0;
 979                 }
 980
 981                 nand->ecc.strength = 4;
 982                 priv->bufnum_mask = 15;
 983                 break;
 984
 985         case CSOR_NAND_PGS_2K:
 986                 layout = &oob_2048_ecc4;
 987                 nand->ecc.strength = 4;
 988                 priv->bufnum_mask = 3;
 989                 break;
 990
 991         case CSOR_NAND_PGS_4K:
 992                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 993                     CSOR_NAND_ECC_MODE_4) {
 994                         layout = &oob_4096_ecc4;
 995                         nand->ecc.strength = 4;
 996                 } else {
 997                         layout = &oob_4096_ecc8;
 998                         nand->ecc.strength = 8;
 999                         nand->ecc.bytes = 16;
1000                 }
1001
1002                 priv->bufnum_mask = 1;
1003                 break;
1004
1005         case CSOR_NAND_PGS_8K:
1006                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1007                     CSOR_NAND_ECC_MODE_4) {
1008                         layout = &oob_8192_ecc4;
1009                         nand->ecc.strength = 4;
1010                 } else {
1011                         layout = &oob_8192_ecc8;
1012                         nand->ecc.strength = 8;
1013                         nand->ecc.bytes = 16;
1014                 }
1015
1016                 priv->bufnum_mask = 0;
1017                 break;
1018
1019
1020         default:
1021                 printf("ifc nand: bad csor %#x: bad page size\n", csor);
1022                 return -ENODEV;
1023         }
1024
1025         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
1026         if (csor & CSOR_NAND_ECC_DEC_EN) {
1027                 nand->ecc.mode = NAND_ECC_HW;
1028                 nand->ecc.layout = layout;
1029         } else {
1030                 nand->ecc.mode = NAND_ECC_SOFT;
1031         }
1032
1033         ver = ifc_in32(&gregs->ifc_rev);
1034         if (ver >= FSL_IFC_V1_1_0)
1035                 ret = fsl_ifc_sram_init(priv, ver);
1036         if (ret)
1037                 return ret;
1038
1039         if (ver >= FSL_IFC_V2_0_0)
1040                 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
1041
1042         ret = nand_scan_ident(mtd, 1, NULL);
1043         if (ret)
1044                 return ret;
1045
1046         ret = nand_scan_tail(mtd);
1047         if (ret)
1048                 return ret;
1049
1050         ret = nand_register(devnum, mtd);
1051         if (ret)
1052                 return ret;
1053         return 0;
1054 }
1055
1056 #ifndef CONFIG_SYS_NAND_BASE_LIST
1057 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1058 #endif
1059
1060 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
1061         CONFIG_SYS_NAND_BASE_LIST;
1062
1063 void board_nand_init(void)
1064 {
1065         int i;
1066
1067         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1068                 fsl_ifc_chip_init(i, (u8 *)base_address[i]);
1069 }