drivers/mtd/nand/raw/fsl_elbc_spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
   4  *
   5  * (C) Copyright 2006-2008
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Copyright (c) 2008 Freescale Semiconductor, Inc.
   9  * Author: Scott Wood <scottwood@freescale.com>
  10  */
  11
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <asm/fsl_lbc.h>
  15 #include <nand.h>
  16
  17 #ifdef CONFIG_MPC83xx
  18 #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
  19 #endif
  20
  21 #define WINDOW_SIZE 8192
  22
  23 static void nand_wait(void)
  24 {
  25         fsl_lbc_t *regs = LBC_BASE_ADDR;
  26
  27         for (;;) {
  28                 uint32_t status = in_be32(&regs->ltesr);
  29
  30                 if (status == 1)
  31                         return;
  32
  33                 if (status & 1) {
  34                         puts("read failed (ltesr)\n");
  35                         for (;;);
  36                 }
  37         }
  38 }
  39
  40 #ifdef CONFIG_TPL_BUILD
  41 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
  42 #else
  43 static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
  44 #endif
  45 {
  46         fsl_lbc_t *regs = LBC_BASE_ADDR;
  47         uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
  48         const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
  49         const int block_shift = large ? 17 : 14;
  50         const int block_size = 1 << block_shift;
  51         const int page_size = large ? 2048 : 512;
  52         const int bad_marker = large ? page_size + 0 : page_size + 5;
  53         int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
  54         int pos = 0;
  55         char *dst = vdst;
  56
  57         if (offs & (block_size - 1)) {
  58                 puts("bad offset\n");
  59                 for (;;);
  60         }
  61
  62         if (large) {
  63                 fmr |= FMR_ECCM;
  64                 out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
  65                                      (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
  66                 out_be32(&regs->fir,
  67                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  68                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
  69                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
  70                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
  71                          (FIR_OP_RBW << FIR_OP4_SHIFT));
  72         } else {
  73                 out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
  74                 out_be32(&regs->fir,
  75                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  76                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
  77                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
  78                          (FIR_OP_RBW << FIR_OP3_SHIFT));
  79         }
  80
  81         out_be32(&regs->fbcr, 0);
  82         clrsetbits_be32(&regs->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
  83
  84         while (pos < uboot_size) {
  85                 int i = 0;
  86                 out_be32(&regs->fbar, offs >> block_shift);
  87
  88                 do {
  89                         int j;
  90                         unsigned int page_offs = (offs & (block_size - 1)) << 1;
  91
  92                         out_be32(&regs->ltesr, ~0);
  93                         out_be32(&regs->lteatr, 0);
  94                         out_be32(&regs->fpar, page_offs);
  95                         out_be32(&regs->fmr, fmr);
  96                         out_be32(&regs->lsor, 0);
  97                         nand_wait();
  98
  99                         page_offs %= WINDOW_SIZE;
 100
 101                         /*
 102                          * If either of the first two pages are marked bad,
 103                          * continue to the next block.
 104                          */
 105                         if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
 106                                 puts("skipping\n");
 107                                 offs = (offs + block_size) & ~(block_size - 1);
 108                                 pos &= ~(block_size - 1);
 109                                 break;
 110                         }
 111
 112                         for (j = 0; j < page_size; j++)
 113                                 dst[pos + j] = buf[page_offs + j];
 114
 115                         pos += page_size;
 116                         offs += page_size;
 117                 } while ((offs & (block_size - 1)) && (pos < uboot_size));
 118         }
 119
 120         return 0;
 121 }
 122
 123 /*
 124  * Defines a static function nand_load_image() here, because non-static makes
 125  * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
 126  */
 127 #ifndef CONFIG_TPL_BUILD
 128 #define nand_spl_load_image(offs, uboot_size, vdst) \
 129         nand_load_image(offs, uboot_size, vdst)
 130 #endif
 131
 132 /*
 133  * The main entry for NAND booting. It's necessary that SDRAM is already
 134  * configured and available since this code loads the main U-Boot image
 135  * from NAND into SDRAM and starts it from there.
 136  */
 137 void nand_boot(void)
 138 {
 139         __attribute__((noreturn)) void (*uboot)(void);
 140         /*
 141          * Load U-Boot image from NAND into RAM
 142          */
 143         nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
 144                             CONFIG_SYS_NAND_U_BOOT_SIZE,
 145                             (void *)CONFIG_SYS_NAND_U_BOOT_DST);
 146
 147 #ifdef CONFIG_NAND_ENV_DST
 148         nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 149                             (void *)CONFIG_NAND_ENV_DST);
 150
 151 #ifdef CONFIG_ENV_OFFSET_REDUND
 152         nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 153                             (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 154 #endif
 155 #endif
 156
 157 #ifdef CONFIG_SPL_FLUSH_IMAGE
 158         /*
 159          * Clean d-cache and invalidate i-cache, to
 160          * make sure that no stale data is executed.
 161          */
 162         flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
 163 #endif
 164
 165         puts("transfering control\n");
 166         /*
 167          * Jump to U-Boot image
 168          */
 169         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 170         (*uboot)();
 171 }