1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
10 #include <linux/ioport.h>
11 #include <linux/printk.h>
15 struct denali_dt_data {
16 unsigned int revision;
18 const struct nand_ecc_caps *ecc_caps;
21 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
23 static const struct denali_dt_data denali_socfpga_data = {
24 .caps = DENALI_CAP_HW_ECC_FIXUP,
25 .ecc_caps = &denali_socfpga_ecc_caps,
28 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
30 static const struct denali_dt_data denali_uniphier_v5a_data = {
31 .caps = DENALI_CAP_HW_ECC_FIXUP |
33 .ecc_caps = &denali_uniphier_v5a_ecc_caps,
36 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
38 static const struct denali_dt_data denali_uniphier_v5b_data = {
40 .caps = DENALI_CAP_HW_ECC_FIXUP |
42 .ecc_caps = &denali_uniphier_v5b_ecc_caps,
45 static const struct udevice_id denali_nand_dt_ids[] = {
47 .compatible = "altr,socfpga-denali-nand",
48 .data = (unsigned long)&denali_socfpga_data,
51 .compatible = "socionext,uniphier-denali-nand-v5a",
52 .data = (unsigned long)&denali_uniphier_v5a_data,
55 .compatible = "socionext,uniphier-denali-nand-v5b",
56 .data = (unsigned long)&denali_uniphier_v5b_data,
61 static int denali_dt_probe(struct udevice *dev)
63 struct denali_nand_info *denali = dev_get_priv(dev);
64 const struct denali_dt_data *data;
65 struct clk clk, clk_x, clk_ecc;
69 data = (void *)dev_get_driver_data(dev);
71 denali->revision = data->revision;
72 denali->caps = data->caps;
73 denali->ecc_caps = data->ecc_caps;
78 ret = dev_read_resource_byname(dev, "denali_reg", &res);
82 denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
84 ret = dev_read_resource_byname(dev, "nand_data", &res);
88 denali->host = devm_ioremap(dev, res.start, resource_size(&res));
90 ret = clk_get_by_name(dev, "nand", &clk);
92 ret = clk_get_by_index(dev, 0, &clk);
96 ret = clk_get_by_name(dev, "nand_x", &clk_x);
100 ret = clk_get_by_name(dev, "ecc", &clk_ecc);
104 ret = clk_enable(&clk);
109 ret = clk_enable(&clk_x);
115 ret = clk_enable(&clk_ecc);
121 denali->clk_rate = clk_get_rate(&clk);
122 denali->clk_x_rate = clk_get_rate(&clk_x);
125 * Hardcode the clock rates for the backward compatibility.
126 * This works for both SOCFPGA and UniPhier.
129 "necessary clock is missing. default clock rates are used.\n");
130 denali->clk_rate = 50000000;
131 denali->clk_x_rate = 200000000;
134 ret = reset_get_bulk(dev, &denali->resets);
136 dev_warn(dev, "Can't get reset: %d\n", ret);
138 reset_deassert_bulk(&denali->resets);
140 return denali_init(denali);
143 static int denali_dt_remove(struct udevice *dev)
145 struct denali_nand_info *denali = dev_get_priv(dev);
147 return reset_release_bulk(&denali->resets);
150 U_BOOT_DRIVER(denali_nand_dt) = {
151 .name = "denali-nand-dt",
153 .of_match = denali_nand_dt_ids,
154 .probe = denali_dt_probe,
155 .priv_auto_alloc_size = sizeof(struct denali_nand_info),
156 .remove = denali_dt_remove,
157 .flags = DM_FLAG_OS_PREPARE,
160 void board_nand_init(void)
165 ret = uclass_get_device_by_driver(UCLASS_MISC,
166 DM_GET_DRIVER(denali_nand_dt),
168 if (ret && ret != -ENODEV)
169 pr_err("Failed to initialize Denali NAND controller. (error %d)\n",