drivers/mtd/nand/raw/brcmnand/brcmnand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright © 2010-2015 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <common.h>
  16 #include <asm/io.h>
  17 #include <memalign.h>
  18 #include <nand.h>
  19 #include <clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/completion.h>
  22 #include <linux/errno.h>
  23 #include <linux/log2.h>
  24 #include <asm/processor.h>
  25 #include <dm.h>
  26
  27 #include "brcmnand.h"
  28 #include "brcmnand_compat.h"
  29
  30 /*
  31  * This flag controls if WP stays on between erase/write commands to mitigate
  32  * flash corruption due to power glitches. Values:
  33  * 0: NAND_WP is not used or not available
  34  * 1: NAND_WP is set by default, cleared for erase/write operations
  35  * 2: NAND_WP is always cleared
  36  */
  37 static int wp_on = 1;
  38 module_param(wp_on, int, 0444);
  39
  40 /***********************************************************************
  41  * Definitions
  42  ***********************************************************************/
  43
  44 #define DRV_NAME                        "brcmnand"
  45
  46 #define CMD_NULL                        0x00
  47 #define CMD_PAGE_READ                   0x01
  48 #define CMD_SPARE_AREA_READ             0x02
  49 #define CMD_STATUS_READ                 0x03
  50 #define CMD_PROGRAM_PAGE                0x04
  51 #define CMD_PROGRAM_SPARE_AREA          0x05
  52 #define CMD_COPY_BACK                   0x06
  53 #define CMD_DEVICE_ID_READ              0x07
  54 #define CMD_BLOCK_ERASE                 0x08
  55 #define CMD_FLASH_RESET                 0x09
  56 #define CMD_BLOCKS_LOCK                 0x0a
  57 #define CMD_BLOCKS_LOCK_DOWN            0x0b
  58 #define CMD_BLOCKS_UNLOCK               0x0c
  59 #define CMD_READ_BLOCKS_LOCK_STATUS     0x0d
  60 #define CMD_PARAMETER_READ              0x0e
  61 #define CMD_PARAMETER_CHANGE_COL        0x0f
  62 #define CMD_LOW_LEVEL_OP                0x10
  63
  64 struct brcm_nand_dma_desc {
  65         u32 next_desc;
  66         u32 next_desc_ext;
  67         u32 cmd_irq;
  68         u32 dram_addr;
  69         u32 dram_addr_ext;
  70         u32 tfr_len;
  71         u32 total_len;
  72         u32 flash_addr;
  73         u32 flash_addr_ext;
  74         u32 cs;
  75         u32 pad2[5];
  76         u32 status_valid;
  77 } __packed;
  78
  79 /* Bitfields for brcm_nand_dma_desc::status_valid */
  80 #define FLASH_DMA_ECC_ERROR     (1 << 8)
  81 #define FLASH_DMA_CORR_ERROR    (1 << 9)
  82
  83 /* 512B flash cache in the NAND controller HW */
  84 #define FC_SHIFT                9U
  85 #define FC_BYTES                512U
  86 #define FC_WORDS                (FC_BYTES >> 2)
  87
  88 #define BRCMNAND_MIN_PAGESIZE   512
  89 #define BRCMNAND_MIN_BLOCKSIZE  (8 * 1024)
  90 #define BRCMNAND_MIN_DEVSIZE    (4ULL * 1024 * 1024)
  91
  92 #define NAND_CTRL_RDY                   (INTFC_CTLR_READY | INTFC_FLASH_READY)
  93 #define NAND_POLL_STATUS_TIMEOUT_MS     100
  94
  95 /* Controller feature flags */
  96 enum {
  97         BRCMNAND_HAS_1K_SECTORS                 = BIT(0),
  98         BRCMNAND_HAS_PREFETCH                   = BIT(1),
  99         BRCMNAND_HAS_CACHE_MODE                 = BIT(2),
 100         BRCMNAND_HAS_WP                         = BIT(3),
 101 };
 102
 103 struct brcmnand_controller {
 104 #ifndef __UBOOT__
 105         struct device           *dev;
 106 #else
 107         struct udevice          *dev;
 108 #endif /* __UBOOT__ */
 109         struct nand_hw_control  controller;
 110         void __iomem            *nand_base;
 111         void __iomem            *nand_fc; /* flash cache */
 112         void __iomem            *flash_dma_base;
 113         unsigned int            irq;
 114         unsigned int            dma_irq;
 115         int                     nand_version;
 116
 117         /* Some SoCs provide custom interrupt status register(s) */
 118         struct brcmnand_soc     *soc;
 119
 120         /* Some SoCs have a gateable clock for the controller */
 121         struct clk              *clk;
 122
 123         int                     cmd_pending;
 124         bool                    dma_pending;
 125         struct completion       done;
 126         struct completion       dma_done;
 127
 128         /* List of NAND hosts (one for each chip-select) */
 129         struct list_head host_list;
 130
 131         struct brcm_nand_dma_desc *dma_desc;
 132         dma_addr_t              dma_pa;
 133
 134         /* in-memory cache of the FLASH_CACHE, used only for some commands */
 135         u8                      flash_cache[FC_BYTES];
 136
 137         /* Controller revision details */
 138         const u16               *reg_offsets;
 139         unsigned int            reg_spacing; /* between CS1, CS2, ... regs */
 140         const u8                *cs_offsets; /* within each chip-select */
 141         const u8                *cs0_offsets; /* within CS0, if different */
 142         unsigned int            max_block_size;
 143         const unsigned int      *block_sizes;
 144         unsigned int            max_page_size;
 145         const unsigned int      *page_sizes;
 146         unsigned int            max_oob;
 147         u32                     features;
 148
 149         /* for low-power standby/resume only */
 150         u32                     nand_cs_nand_select;
 151         u32                     nand_cs_nand_xor;
 152         u32                     corr_stat_threshold;
 153         u32                     flash_dma_mode;
 154 };
 155
 156 struct brcmnand_cfg {
 157         u64                     device_size;
 158         unsigned int            block_size;
 159         unsigned int            page_size;
 160         unsigned int            spare_area_size;
 161         unsigned int            device_width;
 162         unsigned int            col_adr_bytes;
 163         unsigned int            blk_adr_bytes;
 164         unsigned int            ful_adr_bytes;
 165         unsigned int            sector_size_1k;
 166         unsigned int            ecc_level;
 167         /* use for low-power standby/resume only */
 168         u32                     acc_control;
 169         u32                     config;
 170         u32                     config_ext;
 171         u32                     timing_1;
 172         u32                     timing_2;
 173 };
 174
 175 struct brcmnand_host {
 176         struct list_head        node;
 177
 178         struct nand_chip        chip;
 179 #ifndef __UBOOT__
 180         struct platform_device  *pdev;
 181 #else
 182         struct udevice  *pdev;
 183 #endif /* __UBOOT__ */
 184         int                     cs;
 185
 186         unsigned int            last_cmd;
 187         unsigned int            last_byte;
 188         u64                     last_addr;
 189         struct brcmnand_cfg     hwcfg;
 190         struct brcmnand_controller *ctrl;
 191 };
 192
 193 enum brcmnand_reg {
 194         BRCMNAND_CMD_START = 0,
 195         BRCMNAND_CMD_EXT_ADDRESS,
 196         BRCMNAND_CMD_ADDRESS,
 197         BRCMNAND_INTFC_STATUS,
 198         BRCMNAND_CS_SELECT,
 199         BRCMNAND_CS_XOR,
 200         BRCMNAND_LL_OP,
 201         BRCMNAND_CS0_BASE,
 202         BRCMNAND_CS1_BASE,              /* CS1 regs, if non-contiguous */
 203         BRCMNAND_CORR_THRESHOLD,
 204         BRCMNAND_CORR_THRESHOLD_EXT,
 205         BRCMNAND_UNCORR_COUNT,
 206         BRCMNAND_CORR_COUNT,
 207         BRCMNAND_CORR_EXT_ADDR,
 208         BRCMNAND_CORR_ADDR,
 209         BRCMNAND_UNCORR_EXT_ADDR,
 210         BRCMNAND_UNCORR_ADDR,
 211         BRCMNAND_SEMAPHORE,
 212         BRCMNAND_ID,
 213         BRCMNAND_ID_EXT,
 214         BRCMNAND_LL_RDATA,
 215         BRCMNAND_OOB_READ_BASE,
 216         BRCMNAND_OOB_READ_10_BASE,      /* offset 0x10, if non-contiguous */
 217         BRCMNAND_OOB_WRITE_BASE,
 218         BRCMNAND_OOB_WRITE_10_BASE,     /* offset 0x10, if non-contiguous */
 219         BRCMNAND_FC_BASE,
 220 };
 221
 222 /* BRCMNAND v4.0 */
 223 static const u16 brcmnand_regs_v40[] = {
 224         [BRCMNAND_CMD_START]            =  0x04,
 225         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 226         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 227         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 228         [BRCMNAND_CS_SELECT]            =  0x14,
 229         [BRCMNAND_CS_XOR]               =  0x18,
 230         [BRCMNAND_LL_OP]                = 0x178,
 231         [BRCMNAND_CS0_BASE]             =  0x40,
 232         [BRCMNAND_CS1_BASE]             =  0xd0,
 233         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 234         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 235         [BRCMNAND_UNCORR_COUNT]         =     0,
 236         [BRCMNAND_CORR_COUNT]           =     0,
 237         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 238         [BRCMNAND_CORR_ADDR]            =  0x74,
 239         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 240         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 241         [BRCMNAND_SEMAPHORE]            =  0x58,
 242         [BRCMNAND_ID]                   =  0x60,
 243         [BRCMNAND_ID_EXT]               =  0x64,
 244         [BRCMNAND_LL_RDATA]             = 0x17c,
 245         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 246         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 247         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 248         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 249         [BRCMNAND_FC_BASE]              = 0x200,
 250 };
 251
 252 /* BRCMNAND v5.0 */
 253 static const u16 brcmnand_regs_v50[] = {
 254         [BRCMNAND_CMD_START]            =  0x04,
 255         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 256         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 257         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 258         [BRCMNAND_CS_SELECT]            =  0x14,
 259         [BRCMNAND_CS_XOR]               =  0x18,
 260         [BRCMNAND_LL_OP]                = 0x178,
 261         [BRCMNAND_CS0_BASE]             =  0x40,
 262         [BRCMNAND_CS1_BASE]             =  0xd0,
 263         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 264         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 265         [BRCMNAND_UNCORR_COUNT]         =     0,
 266         [BRCMNAND_CORR_COUNT]           =     0,
 267         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 268         [BRCMNAND_CORR_ADDR]            =  0x74,
 269         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 270         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 271         [BRCMNAND_SEMAPHORE]            =  0x58,
 272         [BRCMNAND_ID]                   =  0x60,
 273         [BRCMNAND_ID_EXT]               =  0x64,
 274         [BRCMNAND_LL_RDATA]             = 0x17c,
 275         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 276         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 277         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 278         [BRCMNAND_OOB_WRITE_10_BASE]    = 0x140,
 279         [BRCMNAND_FC_BASE]              = 0x200,
 280 };
 281
 282 /* BRCMNAND v6.0 - v7.1 */
 283 static const u16 brcmnand_regs_v60[] = {
 284         [BRCMNAND_CMD_START]            =  0x04,
 285         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 286         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 287         [BRCMNAND_INTFC_STATUS]         =  0x14,
 288         [BRCMNAND_CS_SELECT]            =  0x18,
 289         [BRCMNAND_CS_XOR]               =  0x1c,
 290         [BRCMNAND_LL_OP]                =  0x20,
 291         [BRCMNAND_CS0_BASE]             =  0x50,
 292         [BRCMNAND_CS1_BASE]             =     0,
 293         [BRCMNAND_CORR_THRESHOLD]       =  0xc0,
 294         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xc4,
 295         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 296         [BRCMNAND_CORR_COUNT]           = 0x100,
 297         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 298         [BRCMNAND_CORR_ADDR]            = 0x110,
 299         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 300         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 301         [BRCMNAND_SEMAPHORE]            = 0x150,
 302         [BRCMNAND_ID]                   = 0x194,
 303         [BRCMNAND_ID_EXT]               = 0x198,
 304         [BRCMNAND_LL_RDATA]             = 0x19c,
 305         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 306         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 307         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 308         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 309         [BRCMNAND_FC_BASE]              = 0x400,
 310 };
 311
 312 /* BRCMNAND v7.1 */
 313 static const u16 brcmnand_regs_v71[] = {
 314         [BRCMNAND_CMD_START]            =  0x04,
 315         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 316         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 317         [BRCMNAND_INTFC_STATUS]         =  0x14,
 318         [BRCMNAND_CS_SELECT]            =  0x18,
 319         [BRCMNAND_CS_XOR]               =  0x1c,
 320         [BRCMNAND_LL_OP]                =  0x20,
 321         [BRCMNAND_CS0_BASE]             =  0x50,
 322         [BRCMNAND_CS1_BASE]             =     0,
 323         [BRCMNAND_CORR_THRESHOLD]       =  0xdc,
 324         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xe0,
 325         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 326         [BRCMNAND_CORR_COUNT]           = 0x100,
 327         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 328         [BRCMNAND_CORR_ADDR]            = 0x110,
 329         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 330         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 331         [BRCMNAND_SEMAPHORE]            = 0x150,
 332         [BRCMNAND_ID]                   = 0x194,
 333         [BRCMNAND_ID_EXT]               = 0x198,
 334         [BRCMNAND_LL_RDATA]             = 0x19c,
 335         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 336         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 337         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 338         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 339         [BRCMNAND_FC_BASE]              = 0x400,
 340 };
 341
 342 /* BRCMNAND v7.2 */
 343 static const u16 brcmnand_regs_v72[] = {
 344         [BRCMNAND_CMD_START]            =  0x04,
 345         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 346         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 347         [BRCMNAND_INTFC_STATUS]         =  0x14,
 348         [BRCMNAND_CS_SELECT]            =  0x18,
 349         [BRCMNAND_CS_XOR]               =  0x1c,
 350         [BRCMNAND_LL_OP]                =  0x20,
 351         [BRCMNAND_CS0_BASE]             =  0x50,
 352         [BRCMNAND_CS1_BASE]             =     0,
 353         [BRCMNAND_CORR_THRESHOLD]       =  0xdc,
 354         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xe0,
 355         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 356         [BRCMNAND_CORR_COUNT]           = 0x100,
 357         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 358         [BRCMNAND_CORR_ADDR]            = 0x110,
 359         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 360         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 361         [BRCMNAND_SEMAPHORE]            = 0x150,
 362         [BRCMNAND_ID]                   = 0x194,
 363         [BRCMNAND_ID_EXT]               = 0x198,
 364         [BRCMNAND_LL_RDATA]             = 0x19c,
 365         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 366         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 367         [BRCMNAND_OOB_WRITE_BASE]       = 0x400,
 368         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 369         [BRCMNAND_FC_BASE]              = 0x600,
 370 };
 371
 372 enum brcmnand_cs_reg {
 373         BRCMNAND_CS_CFG_EXT = 0,
 374         BRCMNAND_CS_CFG,
 375         BRCMNAND_CS_ACC_CONTROL,
 376         BRCMNAND_CS_TIMING1,
 377         BRCMNAND_CS_TIMING2,
 378 };
 379
 380 /* Per chip-select offsets for v7.1 */
 381 static const u8 brcmnand_cs_offsets_v71[] = {
 382         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 383         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 384         [BRCMNAND_CS_CFG]               = 0x08,
 385         [BRCMNAND_CS_TIMING1]           = 0x0c,
 386         [BRCMNAND_CS_TIMING2]           = 0x10,
 387 };
 388
 389 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
 390 static const u8 brcmnand_cs_offsets[] = {
 391         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 392         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 393         [BRCMNAND_CS_CFG]               = 0x04,
 394         [BRCMNAND_CS_TIMING1]           = 0x08,
 395         [BRCMNAND_CS_TIMING2]           = 0x0c,
 396 };
 397
 398 /* Per chip-select offset for <= v5.0 on CS0 only */
 399 static const u8 brcmnand_cs_offsets_cs0[] = {
 400         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 401         [BRCMNAND_CS_CFG_EXT]           = 0x08,
 402         [BRCMNAND_CS_CFG]               = 0x08,
 403         [BRCMNAND_CS_TIMING1]           = 0x10,
 404         [BRCMNAND_CS_TIMING2]           = 0x14,
 405 };
 406
 407 /*
 408  * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
 409  * one config register, but once the bitfields overflowed, newer controllers
 410  * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
 411  */
 412 enum {
 413         CFG_BLK_ADR_BYTES_SHIFT         = 8,
 414         CFG_COL_ADR_BYTES_SHIFT         = 12,
 415         CFG_FUL_ADR_BYTES_SHIFT         = 16,
 416         CFG_BUS_WIDTH_SHIFT             = 23,
 417         CFG_BUS_WIDTH                   = BIT(CFG_BUS_WIDTH_SHIFT),
 418         CFG_DEVICE_SIZE_SHIFT           = 24,
 419
 420         /* Only for pre-v7.1 (with no CFG_EXT register) */
 421         CFG_PAGE_SIZE_SHIFT             = 20,
 422         CFG_BLK_SIZE_SHIFT              = 28,
 423
 424         /* Only for v7.1+ (with CFG_EXT register) */
 425         CFG_EXT_PAGE_SIZE_SHIFT         = 0,
 426         CFG_EXT_BLK_SIZE_SHIFT          = 4,
 427 };
 428
 429 /* BRCMNAND_INTFC_STATUS */
 430 enum {
 431         INTFC_FLASH_STATUS              = GENMASK(7, 0),
 432
 433         INTFC_ERASED                    = BIT(27),
 434         INTFC_OOB_VALID                 = BIT(28),
 435         INTFC_CACHE_VALID               = BIT(29),
 436         INTFC_FLASH_READY               = BIT(30),
 437         INTFC_CTLR_READY                = BIT(31),
 438 };
 439
 440 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
 441 {
 442         return brcmnand_readl(ctrl->nand_base + offs);
 443 }
 444
 445 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
 446                                  u32 val)
 447 {
 448         brcmnand_writel(val, ctrl->nand_base + offs);
 449 }
 450
 451 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
 452 {
 453         static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
 454         static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
 455         static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
 456
 457         ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
 458
 459         /* Only support v4.0+? */
 460         if (ctrl->nand_version < 0x0400) {
 461                 dev_err(ctrl->dev, "version %#x not supported\n",
 462                         ctrl->nand_version);
 463                 return -ENODEV;
 464         }
 465
 466         /* Register offsets */
 467         if (ctrl->nand_version >= 0x0702)
 468                 ctrl->reg_offsets = brcmnand_regs_v72;
 469         else if (ctrl->nand_version >= 0x0701)
 470                 ctrl->reg_offsets = brcmnand_regs_v71;
 471         else if (ctrl->nand_version >= 0x0600)
 472                 ctrl->reg_offsets = brcmnand_regs_v60;
 473         else if (ctrl->nand_version >= 0x0500)
 474                 ctrl->reg_offsets = brcmnand_regs_v50;
 475         else if (ctrl->nand_version >= 0x0400)
 476                 ctrl->reg_offsets = brcmnand_regs_v40;
 477
 478         /* Chip-select stride */
 479         if (ctrl->nand_version >= 0x0701)
 480                 ctrl->reg_spacing = 0x14;
 481         else
 482                 ctrl->reg_spacing = 0x10;
 483
 484         /* Per chip-select registers */
 485         if (ctrl->nand_version >= 0x0701) {
 486                 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
 487         } else {
 488                 ctrl->cs_offsets = brcmnand_cs_offsets;
 489
 490                 /* v5.0 and earlier has a different CS0 offset layout */
 491                 if (ctrl->nand_version <= 0x0500)
 492                         ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
 493         }
 494
 495         /* Page / block sizes */
 496         if (ctrl->nand_version >= 0x0701) {
 497                 /* >= v7.1 use nice power-of-2 values! */
 498                 ctrl->max_page_size = 16 * 1024;
 499                 ctrl->max_block_size = 2 * 1024 * 1024;
 500         } else {
 501                 ctrl->page_sizes = page_sizes;
 502                 if (ctrl->nand_version >= 0x0600)
 503                         ctrl->block_sizes = block_sizes_v6;
 504                 else
 505                         ctrl->block_sizes = block_sizes_v4;
 506
 507                 if (ctrl->nand_version < 0x0400) {
 508                         ctrl->max_page_size = 4096;
 509                         ctrl->max_block_size = 512 * 1024;
 510                 }
 511         }
 512
 513         /* Maximum spare area sector size (per 512B) */
 514         if (ctrl->nand_version >= 0x0702)
 515                 ctrl->max_oob = 128;
 516         else if (ctrl->nand_version >= 0x0600)
 517                 ctrl->max_oob = 64;
 518         else if (ctrl->nand_version >= 0x0500)
 519                 ctrl->max_oob = 32;
 520         else
 521                 ctrl->max_oob = 16;
 522
 523         /* v6.0 and newer (except v6.1) have prefetch support */
 524         if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
 525                 ctrl->features |= BRCMNAND_HAS_PREFETCH;
 526
 527         /*
 528          * v6.x has cache mode, but it's implemented differently. Ignore it for
 529          * now.
 530          */
 531         if (ctrl->nand_version >= 0x0700)
 532                 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
 533
 534         if (ctrl->nand_version >= 0x0500)
 535                 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
 536
 537         if (ctrl->nand_version >= 0x0700)
 538                 ctrl->features |= BRCMNAND_HAS_WP;
 539 #ifndef __UBOOT__
 540         else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
 541 #else
 542         else if (dev_read_bool(ctrl->dev, "brcm,nand-has-wp"))
 543 #endif /* __UBOOT__ */
 544                 ctrl->features |= BRCMNAND_HAS_WP;
 545
 546         return 0;
 547 }
 548
 549 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
 550                 enum brcmnand_reg reg)
 551 {
 552         u16 offs = ctrl->reg_offsets[reg];
 553
 554         if (offs)
 555                 return nand_readreg(ctrl, offs);
 556         else
 557                 return 0;
 558 }
 559
 560 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
 561                                       enum brcmnand_reg reg, u32 val)
 562 {
 563         u16 offs = ctrl->reg_offsets[reg];
 564
 565         if (offs)
 566                 nand_writereg(ctrl, offs, val);
 567 }
 568
 569 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
 570                                     enum brcmnand_reg reg, u32 mask, unsigned
 571                                     int shift, u32 val)
 572 {
 573         u32 tmp = brcmnand_read_reg(ctrl, reg);
 574
 575         tmp &= ~mask;
 576         tmp |= val << shift;
 577         brcmnand_write_reg(ctrl, reg, tmp);
 578 }
 579
 580 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
 581 {
 582         return __raw_readl(ctrl->nand_fc + word * 4);
 583 }
 584
 585 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
 586                                      int word, u32 val)
 587 {
 588         __raw_writel(val, ctrl->nand_fc + word * 4);
 589 }
 590
 591 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
 592                                      enum brcmnand_cs_reg reg)
 593 {
 594         u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
 595         u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
 596         u8 cs_offs;
 597
 598         if (cs == 0 && ctrl->cs0_offsets)
 599                 cs_offs = ctrl->cs0_offsets[reg];
 600         else
 601                 cs_offs = ctrl->cs_offsets[reg];
 602
 603         if (cs && offs_cs1)
 604                 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
 605
 606         return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
 607 }
 608
 609 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
 610 {
 611         if (ctrl->nand_version < 0x0600)
 612                 return 1;
 613         return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
 614 }
 615
 616 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
 617 {
 618         struct brcmnand_controller *ctrl = host->ctrl;
 619         unsigned int shift = 0, bits;
 620         enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
 621         int cs = host->cs;
 622
 623         if (ctrl->nand_version >= 0x0702)
 624                 bits = 7;
 625         else if (ctrl->nand_version >= 0x0600)
 626                 bits = 6;
 627         else if (ctrl->nand_version >= 0x0500)
 628                 bits = 5;
 629         else
 630                 bits = 4;
 631
 632         if (ctrl->nand_version >= 0x0702) {
 633                 if (cs >= 4)
 634                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 635                 shift = (cs % 4) * bits;
 636         } else if (ctrl->nand_version >= 0x0600) {
 637                 if (cs >= 5)
 638                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 639                 shift = (cs % 5) * bits;
 640         }
 641         brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
 642 }
 643
 644 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
 645 {
 646         if (ctrl->nand_version < 0x0602)
 647                 return 24;
 648         return 0;
 649 }
 650
 651 /***********************************************************************
 652  * NAND ACC CONTROL bitfield
 653  *
 654  * Some bits have remained constant throughout hardware revision, while
 655  * others have shifted around.
 656  ***********************************************************************/
 657
 658 /* Constant for all versions (where supported) */
 659 enum {
 660         /* See BRCMNAND_HAS_CACHE_MODE */
 661         ACC_CONTROL_CACHE_MODE                          = BIT(22),
 662
 663         /* See BRCMNAND_HAS_PREFETCH */
 664         ACC_CONTROL_PREFETCH                            = BIT(23),
 665
 666         ACC_CONTROL_PAGE_HIT                            = BIT(24),
 667         ACC_CONTROL_WR_PREEMPT                          = BIT(25),
 668         ACC_CONTROL_PARTIAL_PAGE                        = BIT(26),
 669         ACC_CONTROL_RD_ERASED                           = BIT(27),
 670         ACC_CONTROL_FAST_PGM_RDIN                       = BIT(28),
 671         ACC_CONTROL_WR_ECC                              = BIT(30),
 672         ACC_CONTROL_RD_ECC                              = BIT(31),
 673 };
 674
 675 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
 676 {
 677         if (ctrl->nand_version >= 0x0702)
 678                 return GENMASK(7, 0);
 679         else if (ctrl->nand_version >= 0x0600)
 680                 return GENMASK(6, 0);
 681         else
 682                 return GENMASK(5, 0);
 683 }
 684
 685 #define NAND_ACC_CONTROL_ECC_SHIFT      16
 686 #define NAND_ACC_CONTROL_ECC_EXT_SHIFT  13
 687
 688 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
 689 {
 690         u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
 691
 692         mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
 693
 694         /* v7.2 includes additional ECC levels */
 695         if (ctrl->nand_version >= 0x0702)
 696                 mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
 697
 698         return mask;
 699 }
 700
 701 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
 702 {
 703         struct brcmnand_controller *ctrl = host->ctrl;
 704         u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
 705         u32 acc_control = nand_readreg(ctrl, offs);
 706         u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
 707
 708         if (en) {
 709                 acc_control |= ecc_flags; /* enable RD/WR ECC */
 710                 acc_control |= host->hwcfg.ecc_level
 711                                << NAND_ACC_CONTROL_ECC_SHIFT;
 712         } else {
 713                 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
 714                 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
 715         }
 716
 717         nand_writereg(ctrl, offs, acc_control);
 718 }
 719
 720 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
 721 {
 722         if (ctrl->nand_version >= 0x0702)
 723                 return 9;
 724         else if (ctrl->nand_version >= 0x0600)
 725                 return 7;
 726         else if (ctrl->nand_version >= 0x0500)
 727                 return 6;
 728         else
 729                 return -1;
 730 }
 731
 732 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
 733 {
 734         struct brcmnand_controller *ctrl = host->ctrl;
 735         int shift = brcmnand_sector_1k_shift(ctrl);
 736         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 737                                                   BRCMNAND_CS_ACC_CONTROL);
 738
 739         if (shift < 0)
 740                 return 0;
 741
 742         return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
 743 }
 744
 745 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
 746 {
 747         struct brcmnand_controller *ctrl = host->ctrl;
 748         int shift = brcmnand_sector_1k_shift(ctrl);
 749         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 750                                                   BRCMNAND_CS_ACC_CONTROL);
 751         u32 tmp;
 752
 753         if (shift < 0)
 754                 return;
 755
 756         tmp = nand_readreg(ctrl, acc_control_offs);
 757         tmp &= ~(1 << shift);
 758         tmp |= (!!val) << shift;
 759         nand_writereg(ctrl, acc_control_offs, tmp);
 760 }
 761
 762 /***********************************************************************
 763  * CS_NAND_SELECT
 764  ***********************************************************************/
 765
 766 enum {
 767         CS_SELECT_NAND_WP                       = BIT(29),
 768         CS_SELECT_AUTO_DEVICE_ID_CFG            = BIT(30),
 769 };
 770
 771 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
 772                                     u32 mask, u32 expected_val,
 773                                     unsigned long timeout_ms)
 774 {
 775 #ifndef __UBOOT__
 776         unsigned long limit;
 777         u32 val;
 778
 779         if (!timeout_ms)
 780                 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
 781
 782         limit = jiffies + msecs_to_jiffies(timeout_ms);
 783         do {
 784                 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
 785                 if ((val & mask) == expected_val)
 786                         return 0;
 787
 788                 cpu_relax();
 789         } while (time_after(limit, jiffies));
 790 #else
 791         unsigned long base, limit;
 792         u32 val;
 793
 794         if (!timeout_ms)
 795                 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
 796
 797         base = get_timer(0);
 798         limit = CONFIG_SYS_HZ * timeout_ms / 1000;
 799         do {
 800                 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
 801                 if ((val & mask) == expected_val)
 802                         return 0;
 803
 804                 cpu_relax();
 805         } while (get_timer(base) < limit);
 806 #endif /* __UBOOT__ */
 807
 808         dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
 809                  expected_val, val & mask);
 810
 811         return -ETIMEDOUT;
 812 }
 813
 814 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
 815 {
 816         u32 val = en ? CS_SELECT_NAND_WP : 0;
 817
 818         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
 819 }
 820
 821 /***********************************************************************
 822  * Flash DMA
 823  ***********************************************************************/
 824
 825 enum flash_dma_reg {
 826         FLASH_DMA_REVISION              = 0x00,
 827         FLASH_DMA_FIRST_DESC            = 0x04,
 828         FLASH_DMA_FIRST_DESC_EXT        = 0x08,
 829         FLASH_DMA_CTRL                  = 0x0c,
 830         FLASH_DMA_MODE                  = 0x10,
 831         FLASH_DMA_STATUS                = 0x14,
 832         FLASH_DMA_INTERRUPT_DESC        = 0x18,
 833         FLASH_DMA_INTERRUPT_DESC_EXT    = 0x1c,
 834         FLASH_DMA_ERROR_STATUS          = 0x20,
 835         FLASH_DMA_CURRENT_DESC          = 0x24,
 836         FLASH_DMA_CURRENT_DESC_EXT      = 0x28,
 837 };
 838
 839 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
 840 {
 841         return ctrl->flash_dma_base;
 842 }
 843
 844 static inline bool flash_dma_buf_ok(const void *buf)
 845 {
 846 #ifndef __UBOOT__
 847         return buf && !is_vmalloc_addr(buf) &&
 848                 likely(IS_ALIGNED((uintptr_t)buf, 4));
 849 #else
 850         return buf && likely(IS_ALIGNED((uintptr_t)buf, 4));
 851 #endif /* __UBOOT__ */
 852 }
 853
 854 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
 855                                     u32 val)
 856 {
 857         brcmnand_writel(val, ctrl->flash_dma_base + offs);
 858 }
 859
 860 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
 861 {
 862         return brcmnand_readl(ctrl->flash_dma_base + offs);
 863 }
 864
 865 /* Low-level operation types: command, address, write, or read */
 866 enum brcmnand_llop_type {
 867         LL_OP_CMD,
 868         LL_OP_ADDR,
 869         LL_OP_WR,
 870         LL_OP_RD,
 871 };
 872
 873 /***********************************************************************
 874  * Internal support functions
 875  ***********************************************************************/
 876
 877 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
 878                                   struct brcmnand_cfg *cfg)
 879 {
 880         if (ctrl->nand_version <= 0x0701)
 881                 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
 882                         cfg->ecc_level == 15;
 883         else
 884                 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
 885                         cfg->ecc_level == 15) ||
 886                         (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
 887 }
 888
 889 /*
 890  * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
 891  * the layout/configuration.
 892  * Returns -ERRCODE on failure.
 893  */
 894 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
 895                                           struct mtd_oob_region *oobregion)
 896 {
 897         struct nand_chip *chip = mtd_to_nand(mtd);
 898         struct brcmnand_host *host = nand_get_controller_data(chip);
 899         struct brcmnand_cfg *cfg = &host->hwcfg;
 900         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 901         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 902
 903         if (section >= sectors)
 904                 return -ERANGE;
 905
 906         oobregion->offset = (section * sas) + 6;
 907         oobregion->length = 3;
 908
 909         return 0;
 910 }
 911
 912 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
 913                                            struct mtd_oob_region *oobregion)
 914 {
 915         struct nand_chip *chip = mtd_to_nand(mtd);
 916         struct brcmnand_host *host = nand_get_controller_data(chip);
 917         struct brcmnand_cfg *cfg = &host->hwcfg;
 918         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 919         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 920
 921         if (section >= sectors * 2)
 922                 return -ERANGE;
 923
 924         oobregion->offset = (section / 2) * sas;
 925
 926         if (section & 1) {
 927                 oobregion->offset += 9;
 928                 oobregion->length = 7;
 929         } else {
 930                 oobregion->length = 6;
 931
 932                 /* First sector of each page may have BBI */
 933                 if (!section) {
 934                         /*
 935                          * Small-page NAND use byte 6 for BBI while large-page
 936                          * NAND use byte 0.
 937                          */
 938                         if (cfg->page_size > 512)
 939                                 oobregion->offset++;
 940                         oobregion->length--;
 941                 }
 942         }
 943
 944         return 0;
 945 }
 946
 947 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
 948         .ecc = brcmnand_hamming_ooblayout_ecc,
 949         .free = brcmnand_hamming_ooblayout_free,
 950 };
 951
 952 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
 953                                       struct mtd_oob_region *oobregion)
 954 {
 955         struct nand_chip *chip = mtd_to_nand(mtd);
 956         struct brcmnand_host *host = nand_get_controller_data(chip);
 957         struct brcmnand_cfg *cfg = &host->hwcfg;
 958         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 959         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 960
 961         if (section >= sectors)
 962                 return -ERANGE;
 963
 964         oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes;
 965         oobregion->length = chip->ecc.bytes;
 966
 967         return 0;
 968 }
 969
 970 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
 971                                           struct mtd_oob_region *oobregion)
 972 {
 973         struct nand_chip *chip = mtd_to_nand(mtd);
 974         struct brcmnand_host *host = nand_get_controller_data(chip);
 975         struct brcmnand_cfg *cfg = &host->hwcfg;
 976         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 977         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 978
 979         if (section >= sectors)
 980                 return -ERANGE;
 981
 982         if (sas <= chip->ecc.bytes)
 983                 return 0;
 984
 985         oobregion->offset = section * sas;
 986         oobregion->length = sas - chip->ecc.bytes;
 987
 988         if (!section) {
 989                 oobregion->offset++;
 990                 oobregion->length--;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
 997                                           struct mtd_oob_region *oobregion)
 998 {
 999         struct nand_chip *chip = mtd_to_nand(mtd);
1000         struct brcmnand_host *host = nand_get_controller_data(chip);
1001         struct brcmnand_cfg *cfg = &host->hwcfg;
1002         int sas = cfg->spare_area_size << cfg->sector_size_1k;
1003
1004         if (section > 1 || sas - chip->ecc.bytes < 6 ||
1005             (section && sas - chip->ecc.bytes == 6))
1006                 return -ERANGE;
1007
1008         if (!section) {
1009                 oobregion->offset = 0;
1010                 oobregion->length = 5;
1011         } else {
1012                 oobregion->offset = 6;
1013                 oobregion->length = sas - chip->ecc.bytes - 6;
1014         }
1015
1016         return 0;
1017 }
1018
1019 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
1020         .ecc = brcmnand_bch_ooblayout_ecc,
1021         .free = brcmnand_bch_ooblayout_free_lp,
1022 };
1023
1024 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
1025         .ecc = brcmnand_bch_ooblayout_ecc,
1026         .free = brcmnand_bch_ooblayout_free_sp,
1027 };
1028
1029 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
1030 {
1031         struct brcmnand_cfg *p = &host->hwcfg;
1032         struct mtd_info *mtd = nand_to_mtd(&host->chip);
1033         struct nand_ecc_ctrl *ecc = &host->chip.ecc;
1034         unsigned int ecc_level = p->ecc_level;
1035         int sas = p->spare_area_size << p->sector_size_1k;
1036         int sectors = p->page_size / (512 << p->sector_size_1k);
1037
1038         if (p->sector_size_1k)
1039                 ecc_level <<= 1;
1040
1041         if (is_hamming_ecc(host->ctrl, p)) {
1042                 ecc->bytes = 3 * sectors;
1043                 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
1044                 return 0;
1045         }
1046
1047         /*
1048          * CONTROLLER_VERSION:
1049          *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1050          *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1051          * But we will just be conservative.
1052          */
1053         ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1054         if (p->page_size == 512)
1055                 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
1056         else
1057                 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
1058
1059         if (ecc->bytes >= sas) {
1060                 dev_err(&host->pdev->dev,
1061                         "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1062                         ecc->bytes, sas);
1063                 return -EINVAL;
1064         }
1065
1066         return 0;
1067 }
1068
1069 static void brcmnand_wp(struct mtd_info *mtd, int wp)
1070 {
1071         struct nand_chip *chip = mtd_to_nand(mtd);
1072         struct brcmnand_host *host = nand_get_controller_data(chip);
1073         struct brcmnand_controller *ctrl = host->ctrl;
1074
1075         if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1076                 static int old_wp = -1;
1077                 int ret;
1078
1079                 if (old_wp != wp) {
1080                         dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
1081                         old_wp = wp;
1082                 }
1083
1084                 /*
1085                  * make sure ctrl/flash ready before and after
1086                  * changing state of #WP pin
1087                  */
1088                 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY |
1089                                                NAND_STATUS_READY,
1090                                                NAND_CTRL_RDY |
1091                                                NAND_STATUS_READY, 0);
1092                 if (ret)
1093                         return;
1094
1095                 brcmnand_set_wp(ctrl, wp);
1096                 nand_status_op(chip, NULL);
1097                 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
1098                 ret = bcmnand_ctrl_poll_status(ctrl,
1099                                                NAND_CTRL_RDY |
1100                                                NAND_STATUS_READY |
1101                                                NAND_STATUS_WP,
1102                                                NAND_CTRL_RDY |
1103                                                NAND_STATUS_READY |
1104                                                (wp ? 0 : NAND_STATUS_WP), 0);
1105 #ifndef __UBOOT__
1106                 if (ret)
1107                         dev_err_ratelimited(&host->pdev->dev,
1108                                             "nand #WP expected %s\n",
1109                                             wp ? "on" : "off");
1110 #else
1111                 if (ret)
1112                         dev_err(&host->pdev->dev,
1113                                             "nand #WP expected %s\n",
1114                                             wp ? "on" : "off");
1115 #endif /* __UBOOT__ */
1116         }
1117 }
1118
1119 /* Helper functions for reading and writing OOB registers */
1120 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1121 {
1122         u16 offset0, offset10, reg_offs;
1123
1124         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1125         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1126
1127         if (offs >= ctrl->max_oob)
1128                 return 0x77;
1129
1130         if (offs >= 16 && offset10)
1131                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1132         else
1133                 reg_offs = offset0 + (offs & ~0x03);
1134
1135         return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1136 }
1137
1138 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1139                                  u32 data)
1140 {
1141         u16 offset0, offset10, reg_offs;
1142
1143         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1144         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1145
1146         if (offs >= ctrl->max_oob)
1147                 return;
1148
1149         if (offs >= 16 && offset10)
1150                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1151         else
1152                 reg_offs = offset0 + (offs & ~0x03);
1153
1154         nand_writereg(ctrl, reg_offs, data);
1155 }
1156
1157 /*
1158  * read_oob_from_regs - read data from OOB registers
1159  * @ctrl: NAND controller
1160  * @i: sub-page sector index
1161  * @oob: buffer to read to
1162  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1163  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1164  */
1165 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1166                               int sas, int sector_1k)
1167 {
1168         int tbytes = sas << sector_1k;
1169         int j;
1170
1171         /* Adjust OOB values for 1K sector size */
1172         if (sector_1k && (i & 0x01))
1173                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1174         tbytes = min_t(int, tbytes, ctrl->max_oob);
1175
1176         for (j = 0; j < tbytes; j++)
1177                 oob[j] = oob_reg_read(ctrl, j);
1178         return tbytes;
1179 }
1180
1181 /*
1182  * write_oob_to_regs - write data to OOB registers
1183  * @i: sub-page sector index
1184  * @oob: buffer to write from
1185  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1186  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1187  */
1188 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1189                              const u8 *oob, int sas, int sector_1k)
1190 {
1191         int tbytes = sas << sector_1k;
1192         int j;
1193
1194         /* Adjust OOB values for 1K sector size */
1195         if (sector_1k && (i & 0x01))
1196                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1197         tbytes = min_t(int, tbytes, ctrl->max_oob);
1198
1199         for (j = 0; j < tbytes; j += 4)
1200                 oob_reg_write(ctrl, j,
1201                                 (oob[j + 0] << 24) |
1202                                 (oob[j + 1] << 16) |
1203                                 (oob[j + 2] <<  8) |
1204                                 (oob[j + 3] <<  0));
1205         return tbytes;
1206 }
1207
1208 #ifndef __UBOOT__
1209 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1210 {
1211         struct brcmnand_controller *ctrl = data;
1212
1213         /* Discard all NAND_CTLRDY interrupts during DMA */
1214         if (ctrl->dma_pending)
1215                 return IRQ_HANDLED;
1216
1217         complete(&ctrl->done);
1218         return IRQ_HANDLED;
1219 }
1220
1221 /* Handle SoC-specific interrupt hardware */
1222 static irqreturn_t brcmnand_irq(int irq, void *data)
1223 {
1224         struct brcmnand_controller *ctrl = data;
1225
1226         if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1227                 return brcmnand_ctlrdy_irq(irq, data);
1228
1229         return IRQ_NONE;
1230 }
1231
1232 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1233 {
1234         struct brcmnand_controller *ctrl = data;
1235
1236         complete(&ctrl->dma_done);
1237
1238         return IRQ_HANDLED;
1239 }
1240 #endif /* __UBOOT__ */
1241
1242 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1243 {
1244         struct brcmnand_controller *ctrl = host->ctrl;
1245         int ret;
1246
1247         dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1248                 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1249         BUG_ON(ctrl->cmd_pending != 0);
1250         ctrl->cmd_pending = cmd;
1251
1252         ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
1253         WARN_ON(ret);
1254
1255         mb(); /* flush previous writes */
1256         brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1257                            cmd << brcmnand_cmd_shift(ctrl));
1258 }
1259
1260 /***********************************************************************
1261  * NAND MTD API: read/program/erase
1262  ***********************************************************************/
1263
1264 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1265         unsigned int ctrl)
1266 {
1267         /* intentionally left blank */
1268 }
1269
1270 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1271 {
1272         struct nand_chip *chip = mtd_to_nand(mtd);
1273         struct brcmnand_host *host = nand_get_controller_data(chip);
1274         struct brcmnand_controller *ctrl = host->ctrl;
1275
1276 #ifndef __UBOOT__
1277         unsigned long timeo = msecs_to_jiffies(100);
1278
1279         dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1280         if (ctrl->cmd_pending &&
1281                         wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1282                 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1283                                         >> brcmnand_cmd_shift(ctrl);
1284
1285                 dev_err_ratelimited(ctrl->dev,
1286                         "timeout waiting for command %#02x\n", cmd);
1287                 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1288                         brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1289         }
1290 #else
1291         unsigned long timeo = 100; /* 100 msec */
1292         int ret;
1293
1294         dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1295
1296         ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, timeo);
1297         WARN_ON(ret);
1298 #endif /* __UBOOT__ */
1299
1300         ctrl->cmd_pending = 0;
1301         return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1302                                  INTFC_FLASH_STATUS;
1303 }
1304
1305 enum {
1306         LLOP_RE                         = BIT(16),
1307         LLOP_WE                         = BIT(17),
1308         LLOP_ALE                        = BIT(18),
1309         LLOP_CLE                        = BIT(19),
1310         LLOP_RETURN_IDLE                = BIT(31),
1311
1312         LLOP_DATA_MASK                  = GENMASK(15, 0),
1313 };
1314
1315 static int brcmnand_low_level_op(struct brcmnand_host *host,
1316                                  enum brcmnand_llop_type type, u32 data,
1317                                  bool last_op)
1318 {
1319         struct mtd_info *mtd = nand_to_mtd(&host->chip);
1320         struct nand_chip *chip = &host->chip;
1321         struct brcmnand_controller *ctrl = host->ctrl;
1322         u32 tmp;
1323
1324         tmp = data & LLOP_DATA_MASK;
1325         switch (type) {
1326         case LL_OP_CMD:
1327                 tmp |= LLOP_WE | LLOP_CLE;
1328                 break;
1329         case LL_OP_ADDR:
1330                 /* WE | ALE */
1331                 tmp |= LLOP_WE | LLOP_ALE;
1332                 break;
1333         case LL_OP_WR:
1334                 /* WE */
1335                 tmp |= LLOP_WE;
1336                 break;
1337         case LL_OP_RD:
1338                 /* RE */
1339                 tmp |= LLOP_RE;
1340                 break;
1341         }
1342         if (last_op)
1343                 /* RETURN_IDLE */
1344                 tmp |= LLOP_RETURN_IDLE;
1345
1346         dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1347
1348         brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1349         (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1350
1351         brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1352         return brcmnand_waitfunc(mtd, chip);
1353 }
1354
1355 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1356                              int column, int page_addr)
1357 {
1358         struct nand_chip *chip = mtd_to_nand(mtd);
1359         struct brcmnand_host *host = nand_get_controller_data(chip);
1360         struct brcmnand_controller *ctrl = host->ctrl;
1361         u64 addr = (u64)page_addr << chip->page_shift;
1362         int native_cmd = 0;
1363
1364         if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1365                         command == NAND_CMD_RNDOUT)
1366                 addr = (u64)column;
1367         /* Avoid propagating a negative, don't-care address */
1368         else if (page_addr < 0)
1369                 addr = 0;
1370
1371         dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1372                 (unsigned long long)addr);
1373
1374         host->last_cmd = command;
1375         host->last_byte = 0;
1376         host->last_addr = addr;
1377
1378         switch (command) {
1379         case NAND_CMD_RESET:
1380                 native_cmd = CMD_FLASH_RESET;
1381                 break;
1382         case NAND_CMD_STATUS:
1383                 native_cmd = CMD_STATUS_READ;
1384                 break;
1385         case NAND_CMD_READID:
1386                 native_cmd = CMD_DEVICE_ID_READ;
1387                 break;
1388         case NAND_CMD_READOOB:
1389                 native_cmd = CMD_SPARE_AREA_READ;
1390                 break;
1391         case NAND_CMD_ERASE1:
1392                 native_cmd = CMD_BLOCK_ERASE;
1393                 brcmnand_wp(mtd, 0);
1394                 break;
1395         case NAND_CMD_PARAM:
1396                 native_cmd = CMD_PARAMETER_READ;
1397                 break;
1398         case NAND_CMD_SET_FEATURES:
1399         case NAND_CMD_GET_FEATURES:
1400                 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1401                 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1402                 break;
1403         case NAND_CMD_RNDOUT:
1404                 native_cmd = CMD_PARAMETER_CHANGE_COL;
1405                 addr &= ~((u64)(FC_BYTES - 1));
1406                 /*
1407                  * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1408                  * NB: hwcfg.sector_size_1k may not be initialized yet
1409                  */
1410                 if (brcmnand_get_sector_size_1k(host)) {
1411                         host->hwcfg.sector_size_1k =
1412                                 brcmnand_get_sector_size_1k(host);
1413                         brcmnand_set_sector_size_1k(host, 0);
1414                 }
1415                 break;
1416         }
1417
1418         if (!native_cmd)
1419                 return;
1420
1421         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1422                 (host->cs << 16) | ((addr >> 32) & 0xffff));
1423         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1424         brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1425         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1426
1427         brcmnand_send_cmd(host, native_cmd);
1428         brcmnand_waitfunc(mtd, chip);
1429
1430         if (native_cmd == CMD_PARAMETER_READ ||
1431                         native_cmd == CMD_PARAMETER_CHANGE_COL) {
1432                 /* Copy flash cache word-wise */
1433                 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1434                 int i;
1435
1436                 brcmnand_soc_data_bus_prepare(ctrl->soc, true);
1437
1438                 /*
1439                  * Must cache the FLASH_CACHE now, since changes in
1440                  * SECTOR_SIZE_1K may invalidate it
1441                  */
1442                 for (i = 0; i < FC_WORDS; i++)
1443                         /*
1444                          * Flash cache is big endian for parameter pages, at
1445                          * least on STB SoCs
1446                          */
1447                         flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
1448
1449                 brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
1450
1451                 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1452                 if (host->hwcfg.sector_size_1k)
1453                         brcmnand_set_sector_size_1k(host,
1454                                                     host->hwcfg.sector_size_1k);
1455         }
1456
1457         /* Re-enable protection is necessary only after erase */
1458         if (command == NAND_CMD_ERASE1)
1459                 brcmnand_wp(mtd, 1);
1460 }
1461
1462 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1463 {
1464         struct nand_chip *chip = mtd_to_nand(mtd);
1465         struct brcmnand_host *host = nand_get_controller_data(chip);
1466         struct brcmnand_controller *ctrl = host->ctrl;
1467         uint8_t ret = 0;
1468         int addr, offs;
1469
1470         switch (host->last_cmd) {
1471         case NAND_CMD_READID:
1472                 if (host->last_byte < 4)
1473                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1474                                 (24 - (host->last_byte << 3));
1475                 else if (host->last_byte < 8)
1476                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1477                                 (56 - (host->last_byte << 3));
1478                 break;
1479
1480         case NAND_CMD_READOOB:
1481                 ret = oob_reg_read(ctrl, host->last_byte);
1482                 break;
1483
1484         case NAND_CMD_STATUS:
1485                 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1486                                         INTFC_FLASH_STATUS;
1487                 if (wp_on) /* hide WP status */
1488                         ret |= NAND_STATUS_WP;
1489                 break;
1490
1491         case NAND_CMD_PARAM:
1492         case NAND_CMD_RNDOUT:
1493                 addr = host->last_addr + host->last_byte;
1494                 offs = addr & (FC_BYTES - 1);
1495
1496                 /* At FC_BYTES boundary, switch to next column */
1497                 if (host->last_byte > 0 && offs == 0)
1498                         nand_change_read_column_op(chip, addr, NULL, 0, false);
1499
1500                 ret = ctrl->flash_cache[offs];
1501                 break;
1502         case NAND_CMD_GET_FEATURES:
1503                 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1504                         ret = 0;
1505                 } else {
1506                         bool last = host->last_byte ==
1507                                 ONFI_SUBFEATURE_PARAM_LEN - 1;
1508                         brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1509                         ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1510                 }
1511         }
1512
1513         dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1514         host->last_byte++;
1515
1516         return ret;
1517 }
1518
1519 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1520 {
1521         int i;
1522
1523         for (i = 0; i < len; i++, buf++)
1524                 *buf = brcmnand_read_byte(mtd);
1525 }
1526
1527 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1528                                    int len)
1529 {
1530         int i;
1531         struct nand_chip *chip = mtd_to_nand(mtd);
1532         struct brcmnand_host *host = nand_get_controller_data(chip);
1533
1534         switch (host->last_cmd) {
1535         case NAND_CMD_SET_FEATURES:
1536                 for (i = 0; i < len; i++)
1537                         brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1538                                                   (i + 1) == len);
1539                 break;
1540         default:
1541                 BUG();
1542                 break;
1543         }
1544 }
1545
1546 /**
1547  * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1548  * following ahead of time:
1549  *  - Is this descriptor the beginning or end of a linked list?
1550  *  - What is the (DMA) address of the next descriptor in the linked list?
1551  */
1552 #ifndef __UBOOT__
1553 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1554                                   struct brcm_nand_dma_desc *desc, u64 addr,
1555                                   dma_addr_t buf, u32 len, u8 dma_cmd,
1556                                   bool begin, bool end,
1557                                   dma_addr_t next_desc)
1558 {
1559         memset(desc, 0, sizeof(*desc));
1560         /* Descriptors are written in native byte order (wordwise) */
1561         desc->next_desc = lower_32_bits(next_desc);
1562         desc->next_desc_ext = upper_32_bits(next_desc);
1563         desc->cmd_irq = (dma_cmd << 24) |
1564                 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1565                 (!!begin) | ((!!end) << 1); /* head, tail */
1566 #ifdef CONFIG_CPU_BIG_ENDIAN
1567         desc->cmd_irq |= 0x01 << 12;
1568 #endif
1569         desc->dram_addr = lower_32_bits(buf);
1570         desc->dram_addr_ext = upper_32_bits(buf);
1571         desc->tfr_len = len;
1572         desc->total_len = len;
1573         desc->flash_addr = lower_32_bits(addr);
1574         desc->flash_addr_ext = upper_32_bits(addr);
1575         desc->cs = host->cs;
1576         desc->status_valid = 0x01;
1577         return 0;
1578 }
1579
1580 /**
1581  * Kick the FLASH_DMA engine, with a given DMA descriptor
1582  */
1583 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1584 {
1585         struct brcmnand_controller *ctrl = host->ctrl;
1586         unsigned long timeo = msecs_to_jiffies(100);
1587
1588         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1589         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1590         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1591         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1592
1593         /* Start FLASH_DMA engine */
1594         ctrl->dma_pending = true;
1595         mb(); /* flush previous writes */
1596         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1597
1598         if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1599                 dev_err(ctrl->dev,
1600                                 "timeout waiting for DMA; status %#x, error status %#x\n",
1601                                 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1602                                 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1603         }
1604         ctrl->dma_pending = false;
1605         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1606 }
1607
1608 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1609                               u32 len, u8 dma_cmd)
1610 {
1611         struct brcmnand_controller *ctrl = host->ctrl;
1612         dma_addr_t buf_pa;
1613         int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1614
1615         buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1616         if (dma_mapping_error(ctrl->dev, buf_pa)) {
1617                 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1618                 return -ENOMEM;
1619         }
1620
1621         brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1622                                    dma_cmd, true, true, 0);
1623
1624         brcmnand_dma_run(host, ctrl->dma_pa);
1625
1626         dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1627
1628         if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1629                 return -EBADMSG;
1630         else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1631                 return -EUCLEAN;
1632
1633         return 0;
1634 }
1635 #endif /* __UBOOT__ */
1636
1637 /*
1638  * Assumes proper CS is already set
1639  */
1640 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1641                                 u64 addr, unsigned int trans, u32 *buf,
1642                                 u8 *oob, u64 *err_addr)
1643 {
1644         struct brcmnand_host *host = nand_get_controller_data(chip);
1645         struct brcmnand_controller *ctrl = host->ctrl;
1646         int i, j, ret = 0;
1647
1648         /* Clear error addresses */
1649         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1650         brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1651         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
1652         brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
1653
1654         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1655                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1656         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1657
1658         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1659                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1660                                    lower_32_bits(addr));
1661                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1662                 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1663                 brcmnand_send_cmd(host, CMD_PAGE_READ);
1664                 brcmnand_waitfunc(mtd, chip);
1665
1666                 if (likely(buf)) {
1667                         brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1668
1669                         for (j = 0; j < FC_WORDS; j++, buf++)
1670                                 *buf = brcmnand_read_fc(ctrl, j);
1671
1672                         brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1673                 }
1674
1675                 if (oob)
1676                         oob += read_oob_from_regs(ctrl, i, oob,
1677                                         mtd->oobsize / trans,
1678                                         host->hwcfg.sector_size_1k);
1679
1680                 if (!ret) {
1681                         *err_addr = brcmnand_read_reg(ctrl,
1682                                         BRCMNAND_UNCORR_ADDR) |
1683                                 ((u64)(brcmnand_read_reg(ctrl,
1684                                                 BRCMNAND_UNCORR_EXT_ADDR)
1685                                         & 0xffff) << 32);
1686                         if (*err_addr)
1687                                 ret = -EBADMSG;
1688                 }
1689
1690                 if (!ret) {
1691                         *err_addr = brcmnand_read_reg(ctrl,
1692                                         BRCMNAND_CORR_ADDR) |
1693                                 ((u64)(brcmnand_read_reg(ctrl,
1694                                                 BRCMNAND_CORR_EXT_ADDR)
1695                                         & 0xffff) << 32);
1696                         if (*err_addr)
1697                                 ret = -EUCLEAN;
1698                 }
1699         }
1700
1701         return ret;
1702 }
1703
1704 /*
1705  * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
1706  * error
1707  *
1708  * Because the HW ECC signals an ECC error if an erase paged has even a single
1709  * bitflip, we must check each ECC error to see if it is actually an erased
1710  * page with bitflips, not a truly corrupted page.
1711  *
1712  * On a real error, return a negative error code (-EBADMSG for ECC error), and
1713  * buf will contain raw data.
1714  * Otherwise, buf gets filled with 0xffs and return the maximum number of
1715  * bitflips-per-ECC-sector to the caller.
1716  *
1717  */
1718 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
1719                   struct nand_chip *chip, void *buf, u64 addr)
1720 {
1721         int i, sas;
1722         void *oob = chip->oob_poi;
1723         int bitflips = 0;
1724         int page = addr >> chip->page_shift;
1725         int ret;
1726
1727         if (!buf) {
1728 #ifndef __UBOOT__
1729                 buf = chip->data_buf;
1730 #else
1731                 buf = chip->buffers->databuf;
1732 #endif
1733                 /* Invalidate page cache */
1734                 chip->pagebuf = -1;
1735         }
1736
1737         sas = mtd->oobsize / chip->ecc.steps;
1738
1739         /* read without ecc for verification */
1740         ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
1741         if (ret)
1742                 return ret;
1743
1744         for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
1745                 ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
1746                                                   oob, sas, NULL, 0,
1747                                                   chip->ecc.strength);
1748                 if (ret < 0)
1749                         return ret;
1750
1751                 bitflips = max(bitflips, ret);
1752         }
1753
1754         return bitflips;
1755 }
1756
1757 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1758                          u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1759 {
1760         struct brcmnand_host *host = nand_get_controller_data(chip);
1761         struct brcmnand_controller *ctrl = host->ctrl;
1762         u64 err_addr = 0;
1763         int err;
1764         bool retry = true;
1765
1766         dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1767
1768 try_dmaread:
1769         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1770
1771 #ifndef __UBOOT__
1772         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1773                 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1774                                              CMD_PAGE_READ);
1775                 if (err) {
1776                         if (mtd_is_bitflip_or_eccerr(err))
1777                                 err_addr = addr;
1778                         else
1779                                 return -EIO;
1780                 }
1781         } else {
1782                 if (oob)
1783                         memset(oob, 0x99, mtd->oobsize);
1784
1785                 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1786                                                oob, &err_addr);
1787         }
1788 #else
1789         if (oob)
1790                 memset(oob, 0x99, mtd->oobsize);
1791
1792         err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1793                                                            oob, &err_addr);
1794 #endif /* __UBOOT__ */
1795
1796         if (mtd_is_eccerr(err)) {
1797                 /*
1798                  * On controller version and 7.0, 7.1 , DMA read after a
1799                  * prior PIO read that reported uncorrectable error,
1800                  * the DMA engine captures this error following DMA read
1801                  * cleared only on subsequent DMA read, so just retry once
1802                  * to clear a possible false error reported for current DMA
1803                  * read
1804                  */
1805                 if ((ctrl->nand_version == 0x0700) ||
1806                     (ctrl->nand_version == 0x0701)) {
1807                         if (retry) {
1808                                 retry = false;
1809                                 goto try_dmaread;
1810                         }
1811                 }
1812
1813                 /*
1814                  * Controller version 7.2 has hw encoder to detect erased page
1815                  * bitflips, apply sw verification for older controllers only
1816                  */
1817                 if (ctrl->nand_version < 0x0702) {
1818                         err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
1819                                                               addr);
1820                         /* erased page bitflips corrected */
1821                         if (err >= 0)
1822                                 return err;
1823                 }
1824
1825                 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1826                         (unsigned long long)err_addr);
1827                 mtd->ecc_stats.failed++;
1828                 /* NAND layer expects zero on ECC errors */
1829                 return 0;
1830         }
1831
1832         if (mtd_is_bitflip(err)) {
1833                 unsigned int corrected = brcmnand_count_corrected(ctrl);
1834
1835                 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1836                         (unsigned long long)err_addr);
1837                 mtd->ecc_stats.corrected += corrected;
1838                 /* Always exceed the software-imposed threshold */
1839                 return max(mtd->bitflip_threshold, corrected);
1840         }
1841
1842         return 0;
1843 }
1844
1845 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1846                               uint8_t *buf, int oob_required, int page)
1847 {
1848         struct brcmnand_host *host = nand_get_controller_data(chip);
1849         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1850
1851         nand_read_page_op(chip, page, 0, NULL, 0);
1852
1853         return brcmnand_read(mtd, chip, host->last_addr,
1854                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1855 }
1856
1857 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1858                                   uint8_t *buf, int oob_required, int page)
1859 {
1860         struct brcmnand_host *host = nand_get_controller_data(chip);
1861         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1862         int ret;
1863
1864         nand_read_page_op(chip, page, 0, NULL, 0);
1865
1866         brcmnand_set_ecc_enabled(host, 0);
1867         ret = brcmnand_read(mtd, chip, host->last_addr,
1868                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1869         brcmnand_set_ecc_enabled(host, 1);
1870         return ret;
1871 }
1872
1873 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1874                              int page)
1875 {
1876         return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1877                         mtd->writesize >> FC_SHIFT,
1878                         NULL, (u8 *)chip->oob_poi);
1879 }
1880
1881 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1882                                  int page)
1883 {
1884         struct brcmnand_host *host = nand_get_controller_data(chip);
1885
1886         brcmnand_set_ecc_enabled(host, 0);
1887         brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1888                 mtd->writesize >> FC_SHIFT,
1889                 NULL, (u8 *)chip->oob_poi);
1890         brcmnand_set_ecc_enabled(host, 1);
1891         return 0;
1892 }
1893
1894 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1895                           u64 addr, const u32 *buf, u8 *oob)
1896 {
1897         struct brcmnand_host *host = nand_get_controller_data(chip);
1898         struct brcmnand_controller *ctrl = host->ctrl;
1899         unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1900         int status, ret = 0;
1901
1902         dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1903
1904         if (unlikely((unsigned long)buf & 0x03)) {
1905                 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1906                 buf = (u32 *)((unsigned long)buf & ~0x03);
1907         }
1908
1909         brcmnand_wp(mtd, 0);
1910
1911         for (i = 0; i < ctrl->max_oob; i += 4)
1912                 oob_reg_write(ctrl, i, 0xffffffff);
1913
1914 #ifndef __UBOOT__
1915         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1916                 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1917                                         mtd->writesize, CMD_PROGRAM_PAGE))
1918                         ret = -EIO;
1919                 goto out;
1920         }
1921 #endif /* __UBOOT__ */
1922
1923         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1924                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1925         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1926
1927         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1928                 /* full address MUST be set before populating FC */
1929                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1930                                    lower_32_bits(addr));
1931                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1932
1933                 if (buf) {
1934                         brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1935
1936                         for (j = 0; j < FC_WORDS; j++, buf++)
1937                                 brcmnand_write_fc(ctrl, j, *buf);
1938
1939                         brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1940                 } else if (oob) {
1941                         for (j = 0; j < FC_WORDS; j++)
1942                                 brcmnand_write_fc(ctrl, j, 0xffffffff);
1943                 }
1944
1945                 if (oob) {
1946                         oob += write_oob_to_regs(ctrl, i, oob,
1947                                         mtd->oobsize / trans,
1948                                         host->hwcfg.sector_size_1k);
1949                 }
1950
1951                 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1952                 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1953                 status = brcmnand_waitfunc(mtd, chip);
1954
1955                 if (status & NAND_STATUS_FAIL) {
1956                         dev_info(ctrl->dev, "program failed at %llx\n",
1957                                 (unsigned long long)addr);
1958                         ret = -EIO;
1959                         goto out;
1960                 }
1961         }
1962 out:
1963         brcmnand_wp(mtd, 1);
1964         return ret;
1965 }
1966
1967 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1968                                const uint8_t *buf, int oob_required, int page)
1969 {
1970         struct brcmnand_host *host = nand_get_controller_data(chip);
1971         void *oob = oob_required ? chip->oob_poi : NULL;
1972
1973         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1974         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1975
1976         return nand_prog_page_end_op(chip);
1977 }
1978
1979 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1980                                    struct nand_chip *chip, const uint8_t *buf,
1981                                    int oob_required, int page)
1982 {
1983         struct brcmnand_host *host = nand_get_controller_data(chip);
1984         void *oob = oob_required ? chip->oob_poi : NULL;
1985
1986         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1987         brcmnand_set_ecc_enabled(host, 0);
1988         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1989         brcmnand_set_ecc_enabled(host, 1);
1990
1991         return nand_prog_page_end_op(chip);
1992 }
1993
1994 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1995                                   int page)
1996 {
1997         return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1998                                   NULL, chip->oob_poi);
1999 }
2000
2001 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
2002                                   int page)
2003 {
2004         struct brcmnand_host *host = nand_get_controller_data(chip);
2005         int ret;
2006
2007         brcmnand_set_ecc_enabled(host, 0);
2008         ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
2009                                  (u8 *)chip->oob_poi);
2010         brcmnand_set_ecc_enabled(host, 1);
2011
2012         return ret;
2013 }
2014
2015 /***********************************************************************
2016  * Per-CS setup (1 NAND device)
2017  ***********************************************************************/
2018
2019 static int brcmnand_set_cfg(struct brcmnand_host *host,
2020                             struct brcmnand_cfg *cfg)
2021 {
2022         struct brcmnand_controller *ctrl = host->ctrl;
2023         struct nand_chip *chip = &host->chip;
2024         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2025         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2026                         BRCMNAND_CS_CFG_EXT);
2027         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2028                         BRCMNAND_CS_ACC_CONTROL);
2029         u8 block_size = 0, page_size = 0, device_size = 0;
2030         u32 tmp;
2031
2032         if (ctrl->block_sizes) {
2033                 int i, found;
2034
2035                 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
2036                         if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
2037                                 block_size = i;
2038                                 found = 1;
2039                         }
2040                 if (!found) {
2041                         dev_warn(ctrl->dev, "invalid block size %u\n",
2042                                         cfg->block_size);
2043                         return -EINVAL;
2044                 }
2045         } else {
2046                 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
2047         }
2048
2049         if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
2050                                 cfg->block_size > ctrl->max_block_size)) {
2051                 dev_warn(ctrl->dev, "invalid block size %u\n",
2052                                 cfg->block_size);
2053                 block_size = 0;
2054         }
2055
2056         if (ctrl->page_sizes) {
2057                 int i, found;
2058
2059                 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
2060                         if (ctrl->page_sizes[i] == cfg->page_size) {
2061                                 page_size = i;
2062                                 found = 1;
2063                         }
2064                 if (!found) {
2065                         dev_warn(ctrl->dev, "invalid page size %u\n",
2066                                         cfg->page_size);
2067                         return -EINVAL;
2068                 }
2069         } else {
2070                 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
2071         }
2072
2073         if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
2074                                 cfg->page_size > ctrl->max_page_size)) {
2075                 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
2076                 return -EINVAL;
2077         }
2078
2079         if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
2080                 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
2081                         (unsigned long long)cfg->device_size);
2082                 return -EINVAL;
2083         }
2084         device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
2085
2086         tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
2087                 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
2088                 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
2089                 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
2090                 (device_size << CFG_DEVICE_SIZE_SHIFT);
2091         if (cfg_offs == cfg_ext_offs) {
2092                 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
2093                        (block_size << CFG_BLK_SIZE_SHIFT);
2094                 nand_writereg(ctrl, cfg_offs, tmp);
2095         } else {
2096                 nand_writereg(ctrl, cfg_offs, tmp);
2097                 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
2098                       (block_size << CFG_EXT_BLK_SIZE_SHIFT);
2099                 nand_writereg(ctrl, cfg_ext_offs, tmp);
2100         }
2101
2102         tmp = nand_readreg(ctrl, acc_control_offs);
2103         tmp &= ~brcmnand_ecc_level_mask(ctrl);
2104         tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
2105         tmp &= ~brcmnand_spare_area_mask(ctrl);
2106         tmp |= cfg->spare_area_size;
2107         nand_writereg(ctrl, acc_control_offs, tmp);
2108
2109         brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
2110
2111         /* threshold = ceil(BCH-level * 0.75) */
2112         brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2113
2114         return 0;
2115 }
2116
2117 static void brcmnand_print_cfg(struct brcmnand_host *host,
2118                                char *buf, struct brcmnand_cfg *cfg)
2119 {
2120         buf += sprintf(buf,
2121                 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2122                 (unsigned long long)cfg->device_size >> 20,
2123                 cfg->block_size >> 10,
2124                 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2125                 cfg->page_size >= 1024 ? "KiB" : "B",
2126                 cfg->spare_area_size, cfg->device_width);
2127
2128         /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2129         if (is_hamming_ecc(host->ctrl, cfg))
2130                 sprintf(buf, ", Hamming ECC");
2131         else if (cfg->sector_size_1k)
2132                 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2133         else
2134                 sprintf(buf, ", BCH-%u", cfg->ecc_level);
2135 }
2136
2137 /*
2138  * Minimum number of bytes to address a page. Calculated as:
2139  *     roundup(log2(size / page-size) / 8)
2140  *
2141  * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2142  *     OK because many other things will break if 'size' is irregular...
2143  */
2144 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2145 {
2146         return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2147 }
2148
2149 static int brcmnand_setup_dev(struct brcmnand_host *host)
2150 {
2151         struct mtd_info *mtd = nand_to_mtd(&host->chip);
2152         struct nand_chip *chip = &host->chip;
2153         struct brcmnand_controller *ctrl = host->ctrl;
2154         struct brcmnand_cfg *cfg = &host->hwcfg;
2155         char msg[128];
2156         u32 offs, tmp, oob_sector;
2157         int ret;
2158
2159         memset(cfg, 0, sizeof(*cfg));
2160
2161 #ifndef __UBOOT__
2162         ret = of_property_read_u32(nand_get_flash_node(chip),
2163                                    "brcm,nand-oob-sector-size",
2164                                    &oob_sector);
2165 #else
2166         ret = ofnode_read_u32(nand_get_flash_node(chip),
2167                               "brcm,nand-oob-sector-size",
2168                               &oob_sector);
2169 #endif /* __UBOOT__ */
2170         if (ret) {
2171                 /* Use detected size */
2172                 cfg->spare_area_size = mtd->oobsize /
2173                                         (mtd->writesize >> FC_SHIFT);
2174         } else {
2175                 cfg->spare_area_size = oob_sector;
2176         }
2177         if (cfg->spare_area_size > ctrl->max_oob)
2178                 cfg->spare_area_size = ctrl->max_oob;
2179         /*
2180          * Set oobsize to be consistent with controller's spare_area_size, as
2181          * the rest is inaccessible.
2182          */
2183         mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2184
2185         cfg->device_size = mtd->size;
2186         cfg->block_size = mtd->erasesize;
2187         cfg->page_size = mtd->writesize;
2188         cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2189         cfg->col_adr_bytes = 2;
2190         cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2191
2192         if (chip->ecc.mode != NAND_ECC_HW) {
2193                 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2194                         chip->ecc.mode);
2195                 return -EINVAL;
2196         }
2197
2198         if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
2199                 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2200                         /* Default to Hamming for 1-bit ECC, if unspecified */
2201                         chip->ecc.algo = NAND_ECC_HAMMING;
2202                 else
2203                         /* Otherwise, BCH */
2204                         chip->ecc.algo = NAND_ECC_BCH;
2205         }
2206
2207         if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
2208                                                    chip->ecc.size != 512)) {
2209                 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2210                         chip->ecc.strength, chip->ecc.size);
2211                 return -EINVAL;
2212         }
2213
2214         switch (chip->ecc.size) {
2215         case 512:
2216                 if (chip->ecc.algo == NAND_ECC_HAMMING)
2217                         cfg->ecc_level = 15;
2218                 else
2219                         cfg->ecc_level = chip->ecc.strength;
2220                 cfg->sector_size_1k = 0;
2221                 break;
2222         case 1024:
2223                 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2224                         dev_err(ctrl->dev, "1KB sectors not supported\n");
2225                         return -EINVAL;
2226                 }
2227                 if (chip->ecc.strength & 0x1) {
2228                         dev_err(ctrl->dev,
2229                                 "odd ECC not supported with 1KB sectors\n");
2230                         return -EINVAL;
2231                 }
2232
2233                 cfg->ecc_level = chip->ecc.strength >> 1;
2234                 cfg->sector_size_1k = 1;
2235                 break;
2236         default:
2237                 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
2238                         chip->ecc.size);
2239                 return -EINVAL;
2240         }
2241
2242         cfg->ful_adr_bytes = cfg->blk_adr_bytes;
2243         if (mtd->writesize > 512)
2244                 cfg->ful_adr_bytes += cfg->col_adr_bytes;
2245         else
2246                 cfg->ful_adr_bytes += 1;
2247
2248         ret = brcmnand_set_cfg(host, cfg);
2249         if (ret)
2250                 return ret;
2251
2252         brcmnand_set_ecc_enabled(host, 1);
2253
2254         brcmnand_print_cfg(host, msg, cfg);
2255         dev_info(ctrl->dev, "detected %s\n", msg);
2256
2257         /* Configure ACC_CONTROL */
2258         offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
2259         tmp = nand_readreg(ctrl, offs);
2260         tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
2261         tmp &= ~ACC_CONTROL_RD_ERASED;
2262
2263         /* We need to turn on Read from erased paged protected by ECC */
2264         if (ctrl->nand_version >= 0x0702)
2265                 tmp |= ACC_CONTROL_RD_ERASED;
2266         tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
2267         if (ctrl->features & BRCMNAND_HAS_PREFETCH)
2268                 tmp &= ~ACC_CONTROL_PREFETCH;
2269
2270         nand_writereg(ctrl, offs, tmp);
2271
2272         return 0;
2273 }
2274
2275 #ifndef __UBOOT__
2276 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
2277 #else
2278 static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn)
2279 #endif
2280 {
2281         struct brcmnand_controller *ctrl = host->ctrl;
2282 #ifndef __UBOOT__
2283         struct platform_device *pdev = host->pdev;
2284 #else
2285         struct udevice *pdev = host->pdev;
2286 #endif /* __UBOOT__ */
2287         struct mtd_info *mtd;
2288         struct nand_chip *chip;
2289         int ret;
2290         u16 cfg_offs;
2291
2292 #ifndef __UBOOT__
2293         ret = of_property_read_u32(dn, "reg", &host->cs);
2294 #else
2295         ret = ofnode_read_s32(dn, "reg", &host->cs);
2296 #endif
2297         if (ret) {
2298                 dev_err(&pdev->dev, "can't get chip-select\n");
2299                 return -ENXIO;
2300         }
2301
2302         mtd = nand_to_mtd(&host->chip);
2303         chip = &host->chip;
2304
2305         nand_set_flash_node(chip, dn);
2306         nand_set_controller_data(chip, host);
2307 #ifndef __UBOOT__
2308         mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
2309                                    host->cs);
2310 #else
2311         mtd->name = devm_kasprintf(pdev, GFP_KERNEL, "brcmnand.%d",
2312                                    host->cs);
2313 #endif /* __UBOOT__ */
2314         if (!mtd->name)
2315                 return -ENOMEM;
2316
2317         mtd->owner = THIS_MODULE;
2318 #ifndef __UBOOT__
2319         mtd->dev.parent = &pdev->dev;
2320 #else
2321         mtd->dev->parent = pdev;
2322 #endif /* __UBOOT__ */
2323
2324         chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
2325         chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
2326
2327         chip->cmd_ctrl = brcmnand_cmd_ctrl;
2328         chip->cmdfunc = brcmnand_cmdfunc;
2329         chip->waitfunc = brcmnand_waitfunc;
2330         chip->read_byte = brcmnand_read_byte;
2331         chip->read_buf = brcmnand_read_buf;
2332         chip->write_buf = brcmnand_write_buf;
2333
2334         chip->ecc.mode = NAND_ECC_HW;
2335         chip->ecc.read_page = brcmnand_read_page;
2336         chip->ecc.write_page = brcmnand_write_page;
2337         chip->ecc.read_page_raw = brcmnand_read_page_raw;
2338         chip->ecc.write_page_raw = brcmnand_write_page_raw;
2339         chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2340         chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2341         chip->ecc.read_oob = brcmnand_read_oob;
2342         chip->ecc.write_oob = brcmnand_write_oob;
2343
2344         chip->controller = &ctrl->controller;
2345
2346         /*
2347          * The bootloader might have configured 16bit mode but
2348          * NAND READID command only works in 8bit mode. We force
2349          * 8bit mode here to ensure that NAND READID commands works.
2350          */
2351         cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2352         nand_writereg(ctrl, cfg_offs,
2353                       nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
2354
2355         ret = nand_scan_ident(mtd, 1, NULL);
2356         if (ret)
2357                 return ret;
2358
2359         chip->options |= NAND_NO_SUBPAGE_WRITE;
2360         /*
2361          * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2362          * to/from, and have nand_base pass us a bounce buffer instead, as
2363          * needed.
2364          */
2365         chip->options |= NAND_USE_BOUNCE_BUFFER;
2366
2367         if (chip->bbt_options & NAND_BBT_USE_FLASH)
2368                 chip->bbt_options |= NAND_BBT_NO_OOB;
2369
2370         if (brcmnand_setup_dev(host))
2371                 return -ENXIO;
2372
2373         chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2374         /* only use our internal HW threshold */
2375         mtd->bitflip_threshold = 1;
2376
2377         ret = brcmstb_choose_ecc_layout(host);
2378         if (ret)
2379                 return ret;
2380
2381         ret = nand_scan_tail(mtd);
2382         if (ret)
2383                 return ret;
2384
2385 #ifndef __UBOOT__
2386         ret = mtd_device_register(mtd, NULL, 0);
2387         if (ret)
2388                 nand_cleanup(chip);
2389 #else
2390         ret = nand_register(0, mtd);
2391 #endif /* __UBOOT__ */
2392
2393         return ret;
2394 }
2395
2396 #ifndef __UBOOT__
2397 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2398                                             int restore)
2399 {
2400         struct brcmnand_controller *ctrl = host->ctrl;
2401         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2402         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2403                         BRCMNAND_CS_CFG_EXT);
2404         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2405                         BRCMNAND_CS_ACC_CONTROL);
2406         u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2407         u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2408
2409         if (restore) {
2410                 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2411                 if (cfg_offs != cfg_ext_offs)
2412                         nand_writereg(ctrl, cfg_ext_offs,
2413                                       host->hwcfg.config_ext);
2414                 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2415                 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2416                 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2417         } else {
2418                 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2419                 if (cfg_offs != cfg_ext_offs)
2420                         host->hwcfg.config_ext =
2421                                 nand_readreg(ctrl, cfg_ext_offs);
2422                 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2423                 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2424                 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2425         }
2426 }
2427
2428 static int brcmnand_suspend(struct device *dev)
2429 {
2430         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2431         struct brcmnand_host *host;
2432
2433         list_for_each_entry(host, &ctrl->host_list, node)
2434                 brcmnand_save_restore_cs_config(host, 0);
2435
2436         ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2437         ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2438         ctrl->corr_stat_threshold =
2439                 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2440
2441         if (has_flash_dma(ctrl))
2442                 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2443
2444         return 0;
2445 }
2446
2447 static int brcmnand_resume(struct device *dev)
2448 {
2449         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2450         struct brcmnand_host *host;
2451
2452         if (has_flash_dma(ctrl)) {
2453                 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2454                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2455         }
2456
2457         brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2458         brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2459         brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2460                         ctrl->corr_stat_threshold);
2461         if (ctrl->soc) {
2462                 /* Clear/re-enable interrupt */
2463                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2464                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2465         }
2466
2467         list_for_each_entry(host, &ctrl->host_list, node) {
2468                 struct nand_chip *chip = &host->chip;
2469
2470                 brcmnand_save_restore_cs_config(host, 1);
2471
2472                 /* Reset the chip, required by some chips after power-up */
2473                 nand_reset_op(chip);
2474         }
2475
2476         return 0;
2477 }
2478
2479 const struct dev_pm_ops brcmnand_pm_ops = {
2480         .suspend                = brcmnand_suspend,
2481         .resume                 = brcmnand_resume,
2482 };
2483 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2484
2485 static const struct of_device_id brcmnand_of_match[] = {
2486         { .compatible = "brcm,brcmnand-v4.0" },
2487         { .compatible = "brcm,brcmnand-v5.0" },
2488         { .compatible = "brcm,brcmnand-v6.0" },
2489         { .compatible = "brcm,brcmnand-v6.1" },
2490         { .compatible = "brcm,brcmnand-v6.2" },
2491         { .compatible = "brcm,brcmnand-v7.0" },
2492         { .compatible = "brcm,brcmnand-v7.1" },
2493         { .compatible = "brcm,brcmnand-v7.2" },
2494         {},
2495 };
2496 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2497 #endif  /* __UBOOT__ */
2498
2499 /***********************************************************************
2500  * Platform driver setup (per controller)
2501  ***********************************************************************/
2502
2503 #ifndef __UBOOT__
2504 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2505 #else
2506 int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc)
2507 #endif /* __UBOOT__ */
2508 {
2509 #ifndef __UBOOT__
2510         struct device *dev = &pdev->dev;
2511         struct device_node *dn = dev->of_node, *child;
2512 #else
2513         ofnode child;
2514         struct udevice *pdev = dev;
2515 #endif /* __UBOOT__ */
2516         struct brcmnand_controller *ctrl;
2517 #ifndef __UBOOT__
2518         struct resource *res;
2519 #else
2520         struct resource res;
2521 #endif /* __UBOOT__ */
2522         int ret;
2523
2524 #ifndef __UBOOT__
2525         /* We only support device-tree instantiation */
2526         if (!dn)
2527                 return -ENODEV;
2528
2529         if (!of_match_node(brcmnand_of_match, dn))
2530                 return -ENODEV;
2531 #endif /* __UBOOT__ */
2532
2533         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2534         if (!ctrl)
2535                 return -ENOMEM;
2536
2537 #ifndef __UBOOT__
2538         dev_set_drvdata(dev, ctrl);
2539 #else
2540         /*
2541          * in u-boot, the data for the driver is allocated before probing
2542          * so to keep the reference to ctrl, we store it in the variable soc
2543          */
2544         soc->ctrl = ctrl;
2545 #endif /* __UBOOT__ */
2546         ctrl->dev = dev;
2547
2548         init_completion(&ctrl->done);
2549         init_completion(&ctrl->dma_done);
2550         nand_hw_control_init(&ctrl->controller);
2551         INIT_LIST_HEAD(&ctrl->host_list);
2552
2553         /* NAND register range */
2554 #ifndef __UBOOT__
2555         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2556         ctrl->nand_base = devm_ioremap_resource(dev, res);
2557 #else
2558         dev_read_resource(pdev, 0, &res);
2559         ctrl->nand_base = devm_ioremap(pdev, res.start, resource_size(&res));
2560 #endif
2561         if (IS_ERR(ctrl->nand_base))
2562                 return PTR_ERR(ctrl->nand_base);
2563
2564         /* Enable clock before using NAND registers */
2565         ctrl->clk = devm_clk_get(dev, "nand");
2566         if (!IS_ERR(ctrl->clk)) {
2567                 ret = clk_prepare_enable(ctrl->clk);
2568                 if (ret)
2569                         return ret;
2570         } else {
2571                 ret = PTR_ERR(ctrl->clk);
2572                 if (ret == -EPROBE_DEFER)
2573                         return ret;
2574
2575                 ctrl->clk = NULL;
2576         }
2577
2578         /* Initialize NAND revision */
2579         ret = brcmnand_revision_init(ctrl);
2580         if (ret)
2581                 goto err;
2582
2583         /*
2584          * Most chips have this cache at a fixed offset within 'nand' block.
2585          * Some must specify this region separately.
2586          */
2587 #ifndef __UBOOT__
2588         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2589         if (res) {
2590                 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2591                 if (IS_ERR(ctrl->nand_fc)) {
2592                         ret = PTR_ERR(ctrl->nand_fc);
2593                         goto err;
2594                 }
2595         } else {
2596                 ctrl->nand_fc = ctrl->nand_base +
2597                                 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2598         }
2599 #else
2600         if (!dev_read_resource_byname(pdev, "nand-cache", &res)) {
2601                 ctrl->nand_fc = devm_ioremap(dev, res.start,
2602                                              resource_size(&res));
2603                 if (IS_ERR(ctrl->nand_fc)) {
2604                         ret = PTR_ERR(ctrl->nand_fc);
2605                         goto err;
2606                 }
2607         } else {
2608                 ctrl->nand_fc = ctrl->nand_base +
2609                                 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2610         }
2611 #endif
2612
2613 #ifndef __UBOOT__
2614         /* FLASH_DMA */
2615         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2616         if (res) {
2617                 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2618                 if (IS_ERR(ctrl->flash_dma_base)) {
2619                         ret = PTR_ERR(ctrl->flash_dma_base);
2620                         goto err;
2621                 }
2622
2623                 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2624                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2625
2626                 /* Allocate descriptor(s) */
2627                 ctrl->dma_desc = dmam_alloc_coherent(dev,
2628                                                      sizeof(*ctrl->dma_desc),
2629                                                      &ctrl->dma_pa, GFP_KERNEL);
2630                 if (!ctrl->dma_desc) {
2631                         ret = -ENOMEM;
2632                         goto err;
2633                 }
2634
2635                 ctrl->dma_irq = platform_get_irq(pdev, 1);
2636                 if ((int)ctrl->dma_irq < 0) {
2637                         dev_err(dev, "missing FLASH_DMA IRQ\n");
2638                         ret = -ENODEV;
2639                         goto err;
2640                 }
2641
2642                 ret = devm_request_irq(dev, ctrl->dma_irq,
2643                                 brcmnand_dma_irq, 0, DRV_NAME,
2644                                 ctrl);
2645                 if (ret < 0) {
2646                         dev_err(dev, "can't allocate IRQ %d: error %d\n",
2647                                         ctrl->dma_irq, ret);
2648                         goto err;
2649                 }
2650
2651                 dev_info(dev, "enabling FLASH_DMA\n");
2652         }
2653 #endif /* __UBOOT__ */
2654
2655         /* Disable automatic device ID config, direct addressing */
2656         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2657                          CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2658         /* Disable XOR addressing */
2659         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2660
2661         if (ctrl->features & BRCMNAND_HAS_WP) {
2662                 /* Permanently disable write protection */
2663                 if (wp_on == 2)
2664                         brcmnand_set_wp(ctrl, false);
2665         } else {
2666                 wp_on = 0;
2667         }
2668
2669 #ifndef __UBOOT__
2670         /* IRQ */
2671         ctrl->irq = platform_get_irq(pdev, 0);
2672         if ((int)ctrl->irq < 0) {
2673                 dev_err(dev, "no IRQ defined\n");
2674                 ret = -ENODEV;
2675                 goto err;
2676         }
2677
2678         /*
2679          * Some SoCs integrate this controller (e.g., its interrupt bits) in
2680          * interesting ways
2681          */
2682         if (soc) {
2683                 ctrl->soc = soc;
2684
2685                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2686                                        DRV_NAME, ctrl);
2687
2688                 /* Enable interrupt */
2689                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2690                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2691         } else {
2692                 /* Use standard interrupt infrastructure */
2693                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2694                                        DRV_NAME, ctrl);
2695         }
2696         if (ret < 0) {
2697                 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2698                         ctrl->irq, ret);
2699                 goto err;
2700         }
2701 #endif /* __UBOOT__ */
2702
2703 #ifndef __UBOOT__
2704         for_each_available_child_of_node(dn, child) {
2705                 if (of_device_is_compatible(child, "brcm,nandcs")) {
2706                         struct brcmnand_host *host;
2707
2708                         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2709                         if (!host) {
2710                                 of_node_put(child);
2711                                 ret = -ENOMEM;
2712                                 goto err;
2713                         }
2714                         host->pdev = pdev;
2715                         host->ctrl = ctrl;
2716
2717                         ret = brcmnand_init_cs(host, child);
2718                         if (ret) {
2719                                 devm_kfree(dev, host);
2720                                 continue; /* Try all chip-selects */
2721                         }
2722
2723                         list_add_tail(&host->node, &ctrl->host_list);
2724                 }
2725         }
2726 #else
2727         ofnode_for_each_subnode(child, dev_ofnode(dev)) {
2728                 if (ofnode_device_is_compatible(child, "brcm,nandcs")) {
2729                         struct brcmnand_host *host;
2730
2731                         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2732                         if (!host) {
2733                                 ret = -ENOMEM;
2734                                 goto err;
2735                         }
2736                         host->pdev = pdev;
2737                         host->ctrl = ctrl;
2738
2739                         ret = brcmnand_init_cs(host, child);
2740                         if (ret) {
2741                                 devm_kfree(dev, host);
2742                                 continue; /* Try all chip-selects */
2743                         }
2744
2745                         list_add_tail(&host->node, &ctrl->host_list);
2746                 }
2747         }
2748 #endif /* __UBOOT__ */
2749
2750 err:
2751 #ifndef __UBOOT__
2752         clk_disable_unprepare(ctrl->clk);
2753 #else
2754         if (ctrl->clk)
2755                 clk_disable(ctrl->clk);
2756 #endif /* __UBOOT__ */
2757         return ret;
2758
2759 }
2760 EXPORT_SYMBOL_GPL(brcmnand_probe);
2761
2762 #ifndef __UBOOT__
2763 int brcmnand_remove(struct platform_device *pdev)
2764 {
2765         struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2766         struct brcmnand_host *host;
2767
2768         list_for_each_entry(host, &ctrl->host_list, node)
2769                 nand_release(nand_to_mtd(&host->chip));
2770
2771         clk_disable_unprepare(ctrl->clk);
2772
2773         dev_set_drvdata(&pdev->dev, NULL);
2774
2775         return 0;
2776 }
2777 #else
2778 int brcmnand_remove(struct udevice *pdev)
2779 {
2780         return 0;
2781 }
2782 #endif /* __UBOOT__ */
2783 EXPORT_SYMBOL_GPL(brcmnand_remove);
2784
2785 MODULE_LICENSE("GPL v2");
2786 MODULE_AUTHOR("Kevin Cernekee");
2787 MODULE_AUTHOR("Brian Norris");
2788 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2789 MODULE_ALIAS("platform:brcmnand");