drivers/mtd/nand/raw/atmel_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   8  *
   9  * Add Programmable Multibit ECC support for various AT91 SoC
  10  *     (C) Copyright 2012 ATMEL, Hong Xu
  11  */
  12
  13 #include <common.h>
  14 #include <log.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/gpio.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19
  20 #include <malloc.h>
  21 #include <nand.h>
  22 #include <watchdog.h>
  23 #include <linux/mtd/nand_ecc.h>
  24
  25 #ifdef CONFIG_ATMEL_NAND_HWECC
  26
  27 /* Register access macros */
  28 #define ecc_readl(add, reg)                             \
  29         readl(add + ATMEL_ECC_##reg)
  30 #define ecc_writel(add, reg, value)                     \
  31         writel((value), add + ATMEL_ECC_##reg)
  32
  33 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  34
  35 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 #undef CONFIG_SYS_NAND_ONFI_DETECTION
  39 #endif
  40
  41 struct atmel_nand_host {
  42         struct pmecc_regs __iomem *pmecc;
  43         struct pmecc_errloc_regs __iomem *pmerrloc;
  44         void __iomem            *pmecc_rom_base;
  45
  46         u8              pmecc_corr_cap;
  47         u16             pmecc_sector_size;
  48         u32             pmecc_index_table_offset;
  49         u32             pmecc_version;
  50
  51         int             pmecc_bytes_per_sector;
  52         int             pmecc_sector_number;
  53         int             pmecc_degree;   /* Degree of remainders */
  54         int             pmecc_cw_len;   /* Length of codeword */
  55
  56         /* lookup table for alpha_to and index_of */
  57         void __iomem    *pmecc_alpha_to;
  58         void __iomem    *pmecc_index_of;
  59
  60         /* data for pmecc computation */
  61         int16_t *pmecc_smu;
  62         int16_t *pmecc_partial_syn;
  63         int16_t *pmecc_si;
  64         int16_t *pmecc_lmu; /* polynomal order */
  65         int     *pmecc_mu;
  66         int     *pmecc_dmu;
  67         int     *pmecc_delta;
  68 };
  69
  70 static struct atmel_nand_host pmecc_host;
  71 static struct nand_ecclayout atmel_pmecc_oobinfo;
  72
  73 /*
  74  * Return number of ecc bytes per sector according to sector size and
  75  * correction capability
  76  *
  77  * Following table shows what at91 PMECC supported:
  78  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  79  * =====================        ================        =================
  80  *                2-bits                 4-bytes                  4-bytes
  81  *                4-bits                 7-bytes                  7-bytes
  82  *                8-bits                13-bytes                 14-bytes
  83  *               12-bits                20-bytes                 21-bytes
  84  *               24-bits                39-bytes                 42-bytes
  85  *               32-bits                52-bytes                 56-bytes
  86  */
  87 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  88 {
  89         int m = 12 + sector_size / 512;
  90         return (m * cap + 7) / 8;
  91 }
  92
  93 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  94         int oobsize, int ecc_len)
  95 {
  96         int i;
  97
  98         layout->eccbytes = ecc_len;
  99
 100         /* ECC will occupy the last ecc_len bytes continuously */
 101         for (i = 0; i < ecc_len; i++)
 102                 layout->eccpos[i] = oobsize - ecc_len + i;
 103
 104         layout->oobfree[0].offset = 2;
 105         layout->oobfree[0].length =
 106                 oobsize - ecc_len - layout->oobfree[0].offset;
 107 }
 108
 109 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 110 {
 111         int table_size;
 112
 113         table_size = host->pmecc_sector_size == 512 ?
 114                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 115
 116         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 117         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 118                         table_size * sizeof(int16_t);
 119 }
 120
 121 static void pmecc_data_free(struct atmel_nand_host *host)
 122 {
 123         free(host->pmecc_partial_syn);
 124         free(host->pmecc_si);
 125         free(host->pmecc_lmu);
 126         free(host->pmecc_smu);
 127         free(host->pmecc_mu);
 128         free(host->pmecc_dmu);
 129         free(host->pmecc_delta);
 130 }
 131
 132 static int pmecc_data_alloc(struct atmel_nand_host *host)
 133 {
 134         const int cap = host->pmecc_corr_cap;
 135         int size;
 136
 137         size = (2 * cap + 1) * sizeof(int16_t);
 138         host->pmecc_partial_syn = malloc(size);
 139         host->pmecc_si = malloc(size);
 140         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 141         host->pmecc_smu = malloc((cap + 2) * size);
 142
 143         size = (cap + 1) * sizeof(int);
 144         host->pmecc_mu = malloc(size);
 145         host->pmecc_dmu = malloc(size);
 146         host->pmecc_delta = malloc(size);
 147
 148         if (host->pmecc_partial_syn &&
 149                         host->pmecc_si &&
 150                         host->pmecc_lmu &&
 151                         host->pmecc_smu &&
 152                         host->pmecc_mu &&
 153                         host->pmecc_dmu &&
 154                         host->pmecc_delta)
 155                 return 0;
 156
 157         /* error happened */
 158         pmecc_data_free(host);
 159         return -ENOMEM;
 160
 161 }
 162
 163 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 164 {
 165         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 166         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 167         int i;
 168         uint32_t value;
 169
 170         /* Fill odd syndromes */
 171         for (i = 0; i < host->pmecc_corr_cap; i++) {
 172                 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
 173                 if (i & 1)
 174                         value >>= 16;
 175                 value &= 0xffff;
 176                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 177         }
 178 }
 179
 180 static void pmecc_substitute(struct mtd_info *mtd)
 181 {
 182         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 183         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 184         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 185         int16_t __iomem *index_of = host->pmecc_index_of;
 186         int16_t *partial_syn = host->pmecc_partial_syn;
 187         const int cap = host->pmecc_corr_cap;
 188         int16_t *si;
 189         int i, j;
 190
 191         /* si[] is a table that holds the current syndrome value,
 192          * an element of that table belongs to the field
 193          */
 194         si = host->pmecc_si;
 195
 196         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 197
 198         /* Computation 2t syndromes based on S(x) */
 199         /* Odd syndromes */
 200         for (i = 1; i < 2 * cap; i += 2) {
 201                 for (j = 0; j < host->pmecc_degree; j++) {
 202                         if (partial_syn[i] & (0x1 << j))
 203                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 204                 }
 205         }
 206         /* Even syndrome = (Odd syndrome) ** 2 */
 207         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 208                 if (si[j] == 0) {
 209                         si[i] = 0;
 210                 } else {
 211                         int16_t tmp;
 212
 213                         tmp = readw(index_of + si[j]);
 214                         tmp = (tmp * 2) % host->pmecc_cw_len;
 215                         si[i] = readw(alpha_to + tmp);
 216                 }
 217         }
 218 }
 219
 220 /*
 221  * This function defines a Berlekamp iterative procedure for
 222  * finding the value of the error location polynomial.
 223  * The input is si[], initialize by pmecc_substitute().
 224  * The output is smu[][].
 225  *
 226  * This function is written according to chip datasheet Chapter:
 227  * Find the Error Location Polynomial Sigma(x) of Section:
 228  * Programmable Multibit ECC Control (PMECC).
 229  */
 230 static void pmecc_get_sigma(struct mtd_info *mtd)
 231 {
 232         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 233         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 234
 235         int16_t *lmu = host->pmecc_lmu;
 236         int16_t *si = host->pmecc_si;
 237         int *mu = host->pmecc_mu;
 238         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 239         int *delta = host->pmecc_delta; /* Delta order */
 240         int cw_len = host->pmecc_cw_len;
 241         const int16_t cap = host->pmecc_corr_cap;
 242         const int num = 2 * cap + 1;
 243         int16_t __iomem *index_of = host->pmecc_index_of;
 244         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 245         int i, j, k;
 246         uint32_t dmu_0_count, tmp;
 247         int16_t *smu = host->pmecc_smu;
 248
 249         /* index of largest delta */
 250         int ro;
 251         int largest;
 252         int diff;
 253
 254         /* Init the Sigma(x) */
 255         memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
 256
 257         dmu_0_count = 0;
 258
 259         /* First Row */
 260
 261         /* Mu */
 262         mu[0] = -1;
 263
 264         smu[0] = 1;
 265
 266         /* discrepancy set to 1 */
 267         dmu[0] = 1;
 268         /* polynom order set to 0 */
 269         lmu[0] = 0;
 270         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 271         delta[0] = -1;
 272
 273         /* Second Row */
 274
 275         /* Mu */
 276         mu[1] = 0;
 277         /* Sigma(x) set to 1 */
 278         smu[num] = 1;
 279
 280         /* discrepancy set to S1 */
 281         dmu[1] = si[1];
 282
 283         /* polynom order set to 0 */
 284         lmu[1] = 0;
 285
 286         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 287         delta[1] = 0;
 288
 289         for (i = 1; i <= cap; i++) {
 290                 mu[i + 1] = i << 1;
 291                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 292                 /* check if discrepancy is set to 0 */
 293                 if (dmu[i] == 0) {
 294                         dmu_0_count++;
 295
 296                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 297                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 298                                 tmp += 2;
 299                         else
 300                                 tmp += 1;
 301
 302                         if (dmu_0_count == tmp) {
 303                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 304                                         smu[(cap + 1) * num + j] =
 305                                                         smu[i * num + j];
 306
 307                                 lmu[cap + 1] = lmu[i];
 308                                 return;
 309                         }
 310
 311                         /* copy polynom */
 312                         for (j = 0; j <= lmu[i] >> 1; j++)
 313                                 smu[(i + 1) * num + j] = smu[i * num + j];
 314
 315                         /* copy previous polynom order to the next */
 316                         lmu[i + 1] = lmu[i];
 317                 } else {
 318                         ro = 0;
 319                         largest = -1;
 320                         /* find largest delta with dmu != 0 */
 321                         for (j = 0; j < i; j++) {
 322                                 if ((dmu[j]) && (delta[j] > largest)) {
 323                                         largest = delta[j];
 324                                         ro = j;
 325                                 }
 326                         }
 327
 328                         /* compute difference */
 329                         diff = (mu[i] - mu[ro]);
 330
 331                         /* Compute degree of the new smu polynomial */
 332                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 333                                 lmu[i + 1] = lmu[i];
 334                         else
 335                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 336
 337                         /* Init smu[i+1] with 0 */
 338                         for (k = 0; k < num; k++)
 339                                 smu[(i + 1) * num + k] = 0;
 340
 341                         /* Compute smu[i+1] */
 342                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 343                                 int16_t a, b, c;
 344
 345                                 if (!(smu[ro * num + k] && dmu[i]))
 346                                         continue;
 347                                 a = readw(index_of + dmu[i]);
 348                                 b = readw(index_of + dmu[ro]);
 349                                 c = readw(index_of + smu[ro * num + k]);
 350                                 tmp = a + (cw_len - b) + c;
 351                                 a = readw(alpha_to + tmp % cw_len);
 352                                 smu[(i + 1) * num + (k + diff)] = a;
 353                         }
 354
 355                         for (k = 0; k <= lmu[i] >> 1; k++)
 356                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 357                 }
 358
 359                 /* End Computing Sigma (Mu+1) and L(mu) */
 360                 /* In either case compute delta */
 361                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 362
 363                 /* Do not compute discrepancy for the last iteration */
 364                 if (i >= cap)
 365                         continue;
 366
 367                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 368                         tmp = 2 * (i - 1);
 369                         if (k == 0) {
 370                                 dmu[i + 1] = si[tmp + 3];
 371                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 372                                 int16_t a, b, c;
 373                                 a = readw(index_of +
 374                                                 smu[(i + 1) * num + k]);
 375                                 b = si[2 * (i - 1) + 3 - k];
 376                                 c = readw(index_of + b);
 377                                 tmp = a + c;
 378                                 tmp %= cw_len;
 379                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 380                                         dmu[i + 1];
 381                         }
 382                 }
 383         }
 384 }
 385
 386 static int pmecc_err_location(struct mtd_info *mtd)
 387 {
 388         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 389         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 390         const int cap = host->pmecc_corr_cap;
 391         const int num = 2 * cap + 1;
 392         int sector_size = host->pmecc_sector_size;
 393         int err_nbr = 0;        /* number of error */
 394         int roots_nbr;          /* number of roots */
 395         int i;
 396         uint32_t val;
 397         int16_t *smu = host->pmecc_smu;
 398         int timeout = PMECC_MAX_TIMEOUT_US;
 399
 400         pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
 401
 402         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 403                 pmecc_writel(host->pmerrloc, sigma[i],
 404                              smu[(cap + 1) * num + i]);
 405                 err_nbr++;
 406         }
 407
 408         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 409         if (sector_size == 1024)
 410                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 411
 412         pmecc_writel(host->pmerrloc, elcfg, val);
 413         pmecc_writel(host->pmerrloc, elen,
 414                      sector_size * 8 + host->pmecc_degree * cap);
 415
 416         while (--timeout) {
 417                 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
 418                         break;
 419                 WATCHDOG_RESET();
 420                 udelay(1);
 421         }
 422
 423         if (!timeout) {
 424                 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
 425                 return -1;
 426         }
 427
 428         roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
 429                         >> 8;
 430         /* Number of roots == degree of smu hence <= cap */
 431         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 432                 return err_nbr - 1;
 433
 434         /* Number of roots does not match the degree of smu
 435          * unable to correct error */
 436         return -1;
 437 }
 438
 439 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 440                 int sector_num, int extra_bytes, int err_nbr)
 441 {
 442         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 443         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 444         int i = 0;
 445         int byte_pos, bit_pos, sector_size, pos;
 446         uint32_t tmp;
 447         uint8_t err_byte;
 448
 449         sector_size = host->pmecc_sector_size;
 450
 451         while (err_nbr) {
 452                 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
 453                 byte_pos = tmp / 8;
 454                 bit_pos  = tmp % 8;
 455
 456                 if (byte_pos >= (sector_size + extra_bytes))
 457                         BUG();  /* should never happen */
 458
 459                 if (byte_pos < sector_size) {
 460                         err_byte = *(buf + byte_pos);
 461                         *(buf + byte_pos) ^= (1 << bit_pos);
 462
 463                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 464                         dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 465                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 466                 } else {
 467                         /* Bit flip in OOB area */
 468                         tmp = sector_num * host->pmecc_bytes_per_sector
 469                                         + (byte_pos - sector_size);
 470                         err_byte = ecc[tmp];
 471                         ecc[tmp] ^= (1 << bit_pos);
 472
 473                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 474                         dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 475                                 pos, bit_pos, err_byte, ecc[tmp]);
 476                 }
 477
 478                 i++;
 479                 err_nbr--;
 480         }
 481
 482         return;
 483 }
 484
 485 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 486         u8 *ecc)
 487 {
 488         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 489         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 490         int i, err_nbr, eccbytes;
 491         uint8_t *buf_pos;
 492
 493         /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
 494         if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
 495                 goto normal_check;
 496
 497         eccbytes = nand_chip->ecc.bytes;
 498         for (i = 0; i < eccbytes; i++)
 499                 if (ecc[i] != 0xff)
 500                         goto normal_check;
 501         /* Erased page, return OK */
 502         return 0;
 503
 504 normal_check:
 505         for (i = 0; i < host->pmecc_sector_number; i++) {
 506                 err_nbr = 0;
 507                 if (pmecc_stat & 0x1) {
 508                         buf_pos = buf + i * host->pmecc_sector_size;
 509
 510                         pmecc_gen_syndrome(mtd, i);
 511                         pmecc_substitute(mtd);
 512                         pmecc_get_sigma(mtd);
 513
 514                         err_nbr = pmecc_err_location(mtd);
 515                         if (err_nbr == -1) {
 516                                 dev_err(host->dev, "PMECC: Too many errors\n");
 517                                 mtd->ecc_stats.failed++;
 518                                 return -EBADMSG;
 519                         } else {
 520                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 521                                         host->pmecc_bytes_per_sector, err_nbr);
 522                                 mtd->ecc_stats.corrected += err_nbr;
 523                         }
 524                 }
 525                 pmecc_stat >>= 1;
 526         }
 527
 528         return 0;
 529 }
 530
 531 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 532         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 533 {
 534         struct atmel_nand_host *host = nand_get_controller_data(chip);
 535         int eccsize = chip->ecc.size;
 536         uint8_t *oob = chip->oob_poi;
 537         uint32_t *eccpos = chip->ecc.layout->eccpos;
 538         uint32_t stat;
 539         int timeout = PMECC_MAX_TIMEOUT_US;
 540
 541         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 542         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 543         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 544                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 545
 546         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 547         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 548
 549         chip->read_buf(mtd, buf, eccsize);
 550         chip->read_buf(mtd, oob, mtd->oobsize);
 551
 552         while (--timeout) {
 553                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 554                         break;
 555                 WATCHDOG_RESET();
 556                 udelay(1);
 557         }
 558
 559         if (!timeout) {
 560                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
 561                 return -1;
 562         }
 563
 564         stat = pmecc_readl(host->pmecc, isr);
 565         if (stat != 0)
 566                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 567                         return -EBADMSG;
 568
 569         return 0;
 570 }
 571
 572 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 573                 struct nand_chip *chip, const uint8_t *buf,
 574                 int oob_required, int page)
 575 {
 576         struct atmel_nand_host *host = nand_get_controller_data(chip);
 577         uint32_t *eccpos = chip->ecc.layout->eccpos;
 578         int i, j;
 579         int timeout = PMECC_MAX_TIMEOUT_US;
 580
 581         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 582         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 583
 584         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 585                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 586
 587         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 588         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 589
 590         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 591
 592         while (--timeout) {
 593                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 594                         break;
 595                 WATCHDOG_RESET();
 596                 udelay(1);
 597         }
 598
 599         if (!timeout) {
 600                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
 601                 goto out;
 602         }
 603
 604         for (i = 0; i < host->pmecc_sector_number; i++) {
 605                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 606                         int pos;
 607
 608                         pos = i * host->pmecc_bytes_per_sector + j;
 609                         chip->oob_poi[eccpos[pos]] =
 610                                 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
 611                 }
 612         }
 613         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 614 out:
 615         return 0;
 616 }
 617
 618 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 619 {
 620         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 621         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 622         uint32_t val = 0;
 623         struct nand_ecclayout *ecc_layout;
 624
 625         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 626         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 627
 628         switch (host->pmecc_corr_cap) {
 629         case 2:
 630                 val = PMECC_CFG_BCH_ERR2;
 631                 break;
 632         case 4:
 633                 val = PMECC_CFG_BCH_ERR4;
 634                 break;
 635         case 8:
 636                 val = PMECC_CFG_BCH_ERR8;
 637                 break;
 638         case 12:
 639                 val = PMECC_CFG_BCH_ERR12;
 640                 break;
 641         case 24:
 642                 val = PMECC_CFG_BCH_ERR24;
 643                 break;
 644         case 32:
 645                 val = PMECC_CFG_BCH_ERR32;
 646                 break;
 647         }
 648
 649         if (host->pmecc_sector_size == 512)
 650                 val |= PMECC_CFG_SECTOR512;
 651         else if (host->pmecc_sector_size == 1024)
 652                 val |= PMECC_CFG_SECTOR1024;
 653
 654         switch (host->pmecc_sector_number) {
 655         case 1:
 656                 val |= PMECC_CFG_PAGE_1SECTOR;
 657                 break;
 658         case 2:
 659                 val |= PMECC_CFG_PAGE_2SECTORS;
 660                 break;
 661         case 4:
 662                 val |= PMECC_CFG_PAGE_4SECTORS;
 663                 break;
 664         case 8:
 665                 val |= PMECC_CFG_PAGE_8SECTORS;
 666                 break;
 667         }
 668
 669         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 670                 | PMECC_CFG_AUTO_DISABLE);
 671         pmecc_writel(host->pmecc, cfg, val);
 672
 673         ecc_layout = nand_chip->ecc.layout;
 674         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 675         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 676         pmecc_writel(host->pmecc, eaddr,
 677                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 678         /* See datasheet about PMECC Clock Control Register */
 679         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 680         pmecc_writel(host->pmecc, idr, 0xff);
 681         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 682 }
 683
 684 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 685 /*
 686  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
 687  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
 688  *                    ONFI ECC parameters.
 689  * @host: point to an atmel_nand_host structure.
 690  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
 691  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
 692  * @chip: point to an nand_chip structure.
 693  * @cap: store the ONFI ECC correct bits capbility
 694  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 695  *
 696  * Return 0 if success. otherwise return the error code.
 697  */
 698 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 699                 struct nand_chip *chip,
 700                 int *cap, int *sector_size)
 701 {
 702         /* Get ECC requirement from ONFI parameters */
 703         *cap = *sector_size = 0;
 704         if (chip->onfi_version) {
 705                 *cap = chip->ecc_strength_ds;
 706                 *sector_size = chip->ecc_step_ds;
 707                 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
 708                          *cap, *sector_size);
 709         }
 710
 711         if (*cap == 0 && *sector_size == 0) {
 712                 /* Non-ONFI compliant */
 713                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
 714                 *cap = 2;
 715                 *sector_size = 512;
 716         }
 717
 718         /* If head file doesn't specify then use the one in ONFI parameters */
 719         if (host->pmecc_corr_cap == 0) {
 720                 /* use the most fitable ecc bits (the near bigger one ) */
 721                 if (*cap <= 2)
 722                         host->pmecc_corr_cap = 2;
 723                 else if (*cap <= 4)
 724                         host->pmecc_corr_cap = 4;
 725                 else if (*cap <= 8)
 726                         host->pmecc_corr_cap = 8;
 727                 else if (*cap <= 12)
 728                         host->pmecc_corr_cap = 12;
 729                 else if (*cap <= 24)
 730                         host->pmecc_corr_cap = 24;
 731                 else
 732 #ifdef CONFIG_SAMA5D2
 733                         host->pmecc_corr_cap = 32;
 734 #else
 735                         host->pmecc_corr_cap = 24;
 736 #endif
 737         }
 738         if (host->pmecc_sector_size == 0) {
 739                 /* use the most fitable sector size (the near smaller one ) */
 740                 if (*sector_size >= 1024)
 741                         host->pmecc_sector_size = 1024;
 742                 else if (*sector_size >= 512)
 743                         host->pmecc_sector_size = 512;
 744                 else
 745                         return -EINVAL;
 746         }
 747         return 0;
 748 }
 749 #endif
 750
 751 #if defined(NO_GALOIS_TABLE_IN_ROM)
 752 static uint16_t *pmecc_galois_table;
 753 static inline int deg(unsigned int poly)
 754 {
 755         /* polynomial degree is the most-significant bit index */
 756         return fls(poly) - 1;
 757 }
 758
 759 static int build_gf_tables(int mm, unsigned int poly,
 760                            int16_t *index_of, int16_t *alpha_to)
 761 {
 762         unsigned int i, x = 1;
 763         const unsigned int k = 1 << deg(poly);
 764         unsigned int nn = (1 << mm) - 1;
 765
 766         /* primitive polynomial must be of degree m */
 767         if (k != (1u << mm))
 768                 return -EINVAL;
 769
 770         for (i = 0; i < nn; i++) {
 771                 alpha_to[i] = x;
 772                 index_of[x] = i;
 773                 if (i && (x == 1))
 774                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
 775                         return -EINVAL;
 776                 x <<= 1;
 777                 if (x & k)
 778                         x ^= poly;
 779         }
 780
 781         alpha_to[nn] = 1;
 782         index_of[0] = 0;
 783
 784         return 0;
 785 }
 786
 787 static uint16_t *create_lookup_table(int sector_size)
 788 {
 789         int degree = (sector_size == 512) ?
 790                         PMECC_GF_DIMENSION_13 :
 791                         PMECC_GF_DIMENSION_14;
 792         unsigned int poly = (sector_size == 512) ?
 793                         PMECC_GF_13_PRIMITIVE_POLY :
 794                         PMECC_GF_14_PRIMITIVE_POLY;
 795         int table_size = (sector_size == 512) ?
 796                         PMECC_INDEX_TABLE_SIZE_512 :
 797                         PMECC_INDEX_TABLE_SIZE_1024;
 798
 799         int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
 800         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
 801                 return NULL;
 802
 803         return (uint16_t *)addr;
 804 }
 805 #endif
 806
 807 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 808                 struct mtd_info *mtd)
 809 {
 810         struct atmel_nand_host *host;
 811         int cap, sector_size;
 812
 813         host = &pmecc_host;
 814         nand_set_controller_data(nand, host);
 815
 816         nand->ecc.mode = NAND_ECC_HW;
 817         nand->ecc.calculate = NULL;
 818         nand->ecc.correct = NULL;
 819         nand->ecc.hwctl = NULL;
 820
 821 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 822         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
 823
 824 #ifdef CONFIG_PMECC_CAP
 825         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 826 #endif
 827 #ifdef CONFIG_PMECC_SECTOR_SIZE
 828         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 829 #endif
 830         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
 831          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
 832          * from ONFI.
 833          */
 834         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
 835                 dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
 836                         cap, sector_size);
 837                 return -EINVAL;
 838         }
 839
 840         if (cap > host->pmecc_corr_cap)
 841                 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
 842                                 host->pmecc_corr_cap, cap);
 843         if (sector_size < host->pmecc_sector_size)
 844                 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
 845                                 host->pmecc_sector_size, sector_size);
 846 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
 847         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 848         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 849 #endif
 850
 851         cap = host->pmecc_corr_cap;
 852         sector_size = host->pmecc_sector_size;
 853
 854         /* TODO: need check whether cap & sector_size is validate */
 855 #if defined(NO_GALOIS_TABLE_IN_ROM)
 856         /*
 857          * As pmecc_rom_base is the begin of the gallois field table, So the
 858          * index offset just set as 0.
 859          */
 860         host->pmecc_index_table_offset = 0;
 861 #else
 862         if (host->pmecc_sector_size == 512)
 863                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 864         else
 865                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 866 #endif
 867
 868         pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
 869                  cap, sector_size);
 870
 871         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 872         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 873                         ATMEL_BASE_PMERRLOC;
 874 #if defined(NO_GALOIS_TABLE_IN_ROM)
 875         pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
 876         if (!pmecc_galois_table) {
 877                 dev_err(host->dev, "out of memory\n");
 878                 return -ENOMEM;
 879         }
 880
 881         host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
 882 #else
 883         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 884 #endif
 885
 886         /* ECC is calculated for the whole page (1 step) */
 887         nand->ecc.size = mtd->writesize;
 888
 889         /* set ECC page size and oob layout */
 890         switch (mtd->writesize) {
 891         case 2048:
 892         case 4096:
 893         case 8192:
 894                 host->pmecc_degree = (sector_size == 512) ?
 895                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 896                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 897                 host->pmecc_sector_number = mtd->writesize / sector_size;
 898                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 899                         cap, sector_size);
 900                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 901                 host->pmecc_index_of = host->pmecc_rom_base +
 902                         host->pmecc_index_table_offset;
 903
 904                 nand->ecc.steps = 1;
 905                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 906                                        host->pmecc_sector_number;
 907
 908                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
 909                         dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
 910                                         MTD_MAX_ECCPOS_ENTRIES_LARGE);
 911                         return -EINVAL;
 912                 }
 913
 914                 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
 915                         dev_err(host->dev, "No room for ECC bytes\n");
 916                         return -EINVAL;
 917                 }
 918                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 919                                         mtd->oobsize,
 920                                         nand->ecc.bytes);
 921                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 922                 break;
 923         case 512:
 924         case 1024:
 925                 /* TODO */
 926                 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
 927         default:
 928                 /* page size not handled by HW ECC */
 929                 /* switching back to soft ECC */
 930                 nand->ecc.mode = NAND_ECC_SOFT;
 931                 nand->ecc.read_page = NULL;
 932                 nand->ecc.postpad = 0;
 933                 nand->ecc.prepad = 0;
 934                 nand->ecc.bytes = 0;
 935                 return 0;
 936         }
 937
 938         /* Allocate data for PMECC computation */
 939         if (pmecc_data_alloc(host)) {
 940                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
 941                 return -ENOMEM;
 942         }
 943
 944         nand->options |= NAND_NO_SUBPAGE_WRITE;
 945         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 946         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 947         nand->ecc.strength = cap;
 948
 949         /* Check the PMECC ip version */
 950         host->pmecc_version = pmecc_readl(host->pmerrloc, version);
 951         dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
 952
 953         atmel_pmecc_core_init(mtd);
 954
 955         return 0;
 956 }
 957
 958 #else
 959
 960 /* oob layout for large page size
 961  * bad block info is on bytes 0 and 1
 962  * the bytes have to be consecutives to avoid
 963  * several NAND_CMD_RNDOUT during read
 964  */
 965 static struct nand_ecclayout atmel_oobinfo_large = {
 966         .eccbytes = 4,
 967         .eccpos = {60, 61, 62, 63},
 968         .oobfree = {
 969                 {2, 58}
 970         },
 971 };
 972
 973 /* oob layout for small page size
 974  * bad block info is on bytes 4 and 5
 975  * the bytes have to be consecutives to avoid
 976  * several NAND_CMD_RNDOUT during read
 977  */
 978 static struct nand_ecclayout atmel_oobinfo_small = {
 979         .eccbytes = 4,
 980         .eccpos = {0, 1, 2, 3},
 981         .oobfree = {
 982                 {6, 10}
 983         },
 984 };
 985
 986 /*
 987  * Calculate HW ECC
 988  *
 989  * function called after a write
 990  *
 991  * mtd:        MTD block structure
 992  * dat:        raw data (unused)
 993  * ecc_code:   buffer for ECC
 994  */
 995 static int atmel_nand_calculate(struct mtd_info *mtd,
 996                 const u_char *dat, unsigned char *ecc_code)
 997 {
 998         unsigned int ecc_value;
 999
1000         /* get the first 2 ECC bytes */
1001         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1002
1003         ecc_code[0] = ecc_value & 0xFF;
1004         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1005
1006         /* get the last 2 ECC bytes */
1007         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1008
1009         ecc_code[2] = ecc_value & 0xFF;
1010         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1011
1012         return 0;
1013 }
1014
1015 /*
1016  * HW ECC read page function
1017  *
1018  * mtd:        mtd info structure
1019  * chip:       nand chip info structure
1020  * buf:        buffer to store read data
1021  * oob_required:    caller expects OOB data read to chip->oob_poi
1022  */
1023 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1024                                 uint8_t *buf, int oob_required, int page)
1025 {
1026         int eccsize = chip->ecc.size;
1027         int eccbytes = chip->ecc.bytes;
1028         uint32_t *eccpos = chip->ecc.layout->eccpos;
1029         uint8_t *p = buf;
1030         uint8_t *oob = chip->oob_poi;
1031         uint8_t *ecc_pos;
1032         int stat;
1033
1034         /* read the page */
1035         chip->read_buf(mtd, p, eccsize);
1036
1037         /* move to ECC position if needed */
1038         if (eccpos[0] != 0) {
1039                 /* This only works on large pages
1040                  * because the ECC controller waits for
1041                  * NAND_CMD_RNDOUTSTART after the
1042                  * NAND_CMD_RNDOUT.
1043                  * anyway, for small pages, the eccpos[0] == 0
1044                  */
1045                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1046                                 mtd->writesize + eccpos[0], -1);
1047         }
1048
1049         /* the ECC controller needs to read the ECC just after the data */
1050         ecc_pos = oob + eccpos[0];
1051         chip->read_buf(mtd, ecc_pos, eccbytes);
1052
1053         /* check if there's an error */
1054         stat = chip->ecc.correct(mtd, p, oob, NULL);
1055
1056         if (stat < 0)
1057                 mtd->ecc_stats.failed++;
1058         else
1059                 mtd->ecc_stats.corrected += stat;
1060
1061         /* get back to oob start (end of page) */
1062         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1063
1064         /* read the oob */
1065         chip->read_buf(mtd, oob, mtd->oobsize);
1066
1067         return 0;
1068 }
1069
1070 /*
1071  * HW ECC Correction
1072  *
1073  * function called after a read
1074  *
1075  * mtd:        MTD block structure
1076  * dat:        raw data read from the chip
1077  * read_ecc:   ECC from the chip (unused)
1078  * isnull:     unused
1079  *
1080  * Detect and correct a 1 bit error for a page
1081  */
1082 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1083                 u_char *read_ecc, u_char *isnull)
1084 {
1085         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1086         unsigned int ecc_status;
1087         unsigned int ecc_word, ecc_bit;
1088
1089         /* get the status from the Status Register */
1090         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1091
1092         /* if there's no error */
1093         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1094                 return 0;
1095
1096         /* get error bit offset (4 bits) */
1097         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1098         /* get word address (12 bits) */
1099         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1100         ecc_word >>= 4;
1101
1102         /* if there are multiple errors */
1103         if (ecc_status & ATMEL_ECC_MULERR) {
1104                 /* check if it is a freshly erased block
1105                  * (filled with 0xff) */
1106                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1107                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1108                         /* the block has just been erased, return OK */
1109                         return 0;
1110                 }
1111                 /* it doesn't seems to be a freshly
1112                  * erased block.
1113                  * We can't correct so many errors */
1114                 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1115                                 " Unable to correct.\n");
1116                 return -EBADMSG;
1117         }
1118
1119         /* if there's a single bit error : we can correct it */
1120         if (ecc_status & ATMEL_ECC_ECCERR) {
1121                 /* there's nothing much to do here.
1122                  * the bit error is on the ECC itself.
1123                  */
1124                 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1125                                 " Nothing to correct\n");
1126                 return 0;
1127         }
1128
1129         dev_warn(host->dev, "atmel_nand : one bit error on data."
1130                         " (word offset in the page :"
1131                         " 0x%x bit offset : 0x%x)\n",
1132                         ecc_word, ecc_bit);
1133         /* correct the error */
1134         if (nand_chip->options & NAND_BUSWIDTH_16) {
1135                 /* 16 bits words */
1136                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1137         } else {
1138                 /* 8 bits words */
1139                 dat[ecc_word] ^= (1 << ecc_bit);
1140         }
1141         dev_warn(host->dev, "atmel_nand : error corrected\n");
1142         return 1;
1143 }
1144
1145 /*
1146  * Enable HW ECC : unused on most chips
1147  */
1148 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1149 {
1150 }
1151
1152 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1153 {
1154         nand->ecc.mode = NAND_ECC_HW;
1155         nand->ecc.calculate = atmel_nand_calculate;
1156         nand->ecc.correct = atmel_nand_correct;
1157         nand->ecc.hwctl = atmel_nand_hwctl;
1158         nand->ecc.read_page = atmel_nand_read_page;
1159         nand->ecc.bytes = 4;
1160         nand->ecc.strength = 4;
1161
1162         if (nand->ecc.mode == NAND_ECC_HW) {
1163                 /* ECC is calculated for the whole page (1 step) */
1164                 nand->ecc.size = mtd->writesize;
1165
1166                 /* set ECC page size and oob layout */
1167                 switch (mtd->writesize) {
1168                 case 512:
1169                         nand->ecc.layout = &atmel_oobinfo_small;
1170                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1171                                         ATMEL_ECC_PAGESIZE_528);
1172                         break;
1173                 case 1024:
1174                         nand->ecc.layout = &atmel_oobinfo_large;
1175                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1176                                         ATMEL_ECC_PAGESIZE_1056);
1177                         break;
1178                 case 2048:
1179                         nand->ecc.layout = &atmel_oobinfo_large;
1180                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1181                                         ATMEL_ECC_PAGESIZE_2112);
1182                         break;
1183                 case 4096:
1184                         nand->ecc.layout = &atmel_oobinfo_large;
1185                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1186                                         ATMEL_ECC_PAGESIZE_4224);
1187                         break;
1188                 default:
1189                         /* page size not handled by HW ECC */
1190                         /* switching back to soft ECC */
1191                         nand->ecc.mode = NAND_ECC_SOFT;
1192                         nand->ecc.calculate = NULL;
1193                         nand->ecc.correct = NULL;
1194                         nand->ecc.hwctl = NULL;
1195                         nand->ecc.read_page = NULL;
1196                         nand->ecc.postpad = 0;
1197                         nand->ecc.prepad = 0;
1198                         nand->ecc.bytes = 0;
1199                         break;
1200                 }
1201         }
1202
1203         return 0;
1204 }
1205
1206 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1207
1208 #endif /* CONFIG_ATMEL_NAND_HWECC */
1209
1210 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1211                                          int cmd, unsigned int ctrl)
1212 {
1213         struct nand_chip *this = mtd_to_nand(mtd);
1214
1215         if (ctrl & NAND_CTRL_CHANGE) {
1216                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1217                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1218                              | CONFIG_SYS_NAND_MASK_CLE);
1219
1220                 if (ctrl & NAND_CLE)
1221                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1222                 if (ctrl & NAND_ALE)
1223                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1224
1225 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1226                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1227                                     !(ctrl & NAND_NCE));
1228 #endif
1229                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1230         }
1231
1232         if (cmd != NAND_CMD_NONE)
1233                 writeb(cmd, this->IO_ADDR_W);
1234 }
1235
1236 #ifdef CONFIG_SYS_NAND_READY_PIN
1237 static int at91_nand_ready(struct mtd_info *mtd)
1238 {
1239         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1240 }
1241 #endif
1242
1243 #ifdef CONFIG_SPL_BUILD
1244 /* The following code is for SPL */
1245 static struct mtd_info *mtd;
1246 static struct nand_chip nand_chip;
1247
1248 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1249 {
1250         struct nand_chip *this = mtd_to_nand(mtd);
1251         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1252         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1253                         unsigned int ctrl) = this->cmd_ctrl;
1254
1255         while (!this->dev_ready(mtd))
1256                 ;
1257
1258         if (cmd == NAND_CMD_READOOB) {
1259                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1260                 cmd = NAND_CMD_READ0;
1261         }
1262
1263         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1264
1265         if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1266                 offs >>= 1;
1267
1268         hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1269         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1270         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1271         hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1272 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1273         hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1274 #endif
1275         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1276
1277         hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1278         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1279
1280         while (!this->dev_ready(mtd))
1281                 ;
1282
1283         return 0;
1284 }
1285
1286 static int nand_is_bad_block(int block)
1287 {
1288         struct nand_chip *this = mtd_to_nand(mtd);
1289
1290         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1291
1292         if (this->options & NAND_BUSWIDTH_16) {
1293                 if (readw(this->IO_ADDR_R) != 0xffff)
1294                         return 1;
1295         } else {
1296                 if (readb(this->IO_ADDR_R) != 0xff)
1297                         return 1;
1298         }
1299
1300         return 0;
1301 }
1302
1303 #ifdef CONFIG_SPL_NAND_ECC
1304 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1305 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1306                   CONFIG_SYS_NAND_ECCSIZE)
1307 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1308
1309 static int nand_read_page(int block, int page, void *dst)
1310 {
1311         struct nand_chip *this = mtd_to_nand(mtd);
1312         u_char ecc_calc[ECCTOTAL];
1313         u_char ecc_code[ECCTOTAL];
1314         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1315         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1316         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1317         int eccsteps = ECCSTEPS;
1318         int i;
1319         uint8_t *p = dst;
1320         nand_command(block, page, 0, NAND_CMD_READ0);
1321
1322         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1323                 if (this->ecc.mode != NAND_ECC_SOFT)
1324                         this->ecc.hwctl(mtd, NAND_ECC_READ);
1325                 this->read_buf(mtd, p, eccsize);
1326                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
1327         }
1328         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1329
1330         for (i = 0; i < ECCTOTAL; i++)
1331                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1332
1333         eccsteps = ECCSTEPS;
1334         p = dst;
1335
1336         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1337                 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1338
1339         return 0;
1340 }
1341
1342 int spl_nand_erase_one(int block, int page)
1343 {
1344         struct nand_chip *this = mtd_to_nand(mtd);
1345         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1346                         unsigned int ctrl) = this->cmd_ctrl;
1347         int page_addr;
1348
1349         if (nand_chip.select_chip)
1350                 nand_chip.select_chip(mtd, 0);
1351
1352         page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1353         hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1354         /* Row address */
1355         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1356         hwctrl(mtd, ((page_addr >> 8) & 0xff),
1357                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1358 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1359         /* One more address cycle for devices > 128MiB */
1360         hwctrl(mtd, (page_addr >> 16) & 0x0f,
1361                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1362 #endif
1363         hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1364
1365         while (!this->dev_ready(mtd))
1366                 ;
1367
1368         nand_deselect();
1369
1370         return 0;
1371 }
1372 #else
1373 static int nand_read_page(int block, int page, void *dst)
1374 {
1375         struct nand_chip *this = mtd_to_nand(mtd);
1376
1377         nand_command(block, page, 0, NAND_CMD_READ0);
1378         atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1379
1380         return 0;
1381 }
1382 #endif /* CONFIG_SPL_NAND_ECC */
1383
1384 int at91_nand_wait_ready(struct mtd_info *mtd)
1385 {
1386         struct nand_chip *this = mtd_to_nand(mtd);
1387
1388         udelay(this->chip_delay);
1389
1390         return 1;
1391 }
1392
1393 int board_nand_init(struct nand_chip *nand)
1394 {
1395         int ret = 0;
1396
1397         nand->ecc.mode = NAND_ECC_SOFT;
1398 #ifdef CONFIG_SYS_NAND_DBW_16
1399         nand->options = NAND_BUSWIDTH_16;
1400         nand->read_buf = nand_read_buf16;
1401 #else
1402         nand->read_buf = nand_read_buf;
1403 #endif
1404         nand->cmd_ctrl = at91_nand_hwcontrol;
1405 #ifdef CONFIG_SYS_NAND_READY_PIN
1406         nand->dev_ready = at91_nand_ready;
1407 #else
1408         nand->dev_ready = at91_nand_wait_ready;
1409 #endif
1410         nand->chip_delay = 20;
1411 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1412         nand->bbt_options |= NAND_BBT_USE_FLASH;
1413 #endif
1414
1415 #ifdef CONFIG_ATMEL_NAND_HWECC
1416 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1417         ret = atmel_pmecc_nand_init_params(nand, mtd);
1418 #endif
1419 #endif
1420
1421         return ret;
1422 }
1423
1424 void nand_init(void)
1425 {
1426         mtd = nand_to_mtd(&nand_chip);
1427         mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1428         mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1429         nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1430         nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1431         board_nand_init(&nand_chip);
1432
1433 #ifdef CONFIG_SPL_NAND_ECC
1434         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1435                 nand_chip.ecc.calculate = nand_calculate_ecc;
1436                 nand_chip.ecc.correct = nand_correct_data;
1437         }
1438 #endif
1439
1440         if (nand_chip.select_chip)
1441                 nand_chip.select_chip(mtd, 0);
1442 }
1443
1444 void nand_deselect(void)
1445 {
1446         if (nand_chip.select_chip)
1447                 nand_chip.select_chip(mtd, -1);
1448 }
1449
1450 #include "nand_spl_loaders.c"
1451
1452 #else
1453
1454 #ifndef CONFIG_SYS_NAND_BASE_LIST
1455 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1456 #endif
1457 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1458 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1459
1460 int atmel_nand_chip_init(int devnum, ulong base_addr)
1461 {
1462         int ret;
1463         struct nand_chip *nand = &nand_chip[devnum];
1464         struct mtd_info *mtd = nand_to_mtd(nand);
1465
1466         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1467
1468 #ifdef CONFIG_NAND_ECC_BCH
1469         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1470 #else
1471         nand->ecc.mode = NAND_ECC_SOFT;
1472 #endif
1473 #ifdef CONFIG_SYS_NAND_DBW_16
1474         nand->options = NAND_BUSWIDTH_16;
1475 #endif
1476         nand->cmd_ctrl = at91_nand_hwcontrol;
1477 #ifdef CONFIG_SYS_NAND_READY_PIN
1478         nand->dev_ready = at91_nand_ready;
1479 #endif
1480         nand->chip_delay = 75;
1481 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1482         nand->bbt_options |= NAND_BBT_USE_FLASH;
1483 #endif
1484
1485         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1486         if (ret)
1487                 return ret;
1488
1489 #ifdef CONFIG_ATMEL_NAND_HWECC
1490 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1491         ret = atmel_pmecc_nand_init_params(nand, mtd);
1492 #else
1493         ret = atmel_hwecc_nand_init_param(nand, mtd);
1494 #endif
1495         if (ret)
1496                 return ret;
1497 #endif
1498
1499         ret = nand_scan_tail(mtd);
1500         if (!ret)
1501                 nand_register(devnum, mtd);
1502
1503         return ret;
1504 }
1505
1506 void board_nand_init(void)
1507 {
1508         int i;
1509         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1510                 if (atmel_nand_chip_init(i, base_addr[i]))
1511                         dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1512                                 i);
1513 }
1514 #endif /* CONFIG_SPL_BUILD */