drivers/mtd/nand/raw/atmel_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   8  *
   9  * Add Programmable Multibit ECC support for various AT91 SoC
  10  *     (C) Copyright 2012 ATMEL, Hong Xu
  11  */
  12
  13 #include <common.h>
  14 #include <log.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/gpio.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19 #include <linux/bitops.h>
  20 #include <linux/bug.h>
  21 #include <linux/delay.h>
  22
  23 #include <malloc.h>
  24 #include <nand.h>
  25 #include <watchdog.h>
  26 #include <linux/mtd/nand_ecc.h>
  27
  28 #ifdef CONFIG_ATMEL_NAND_HWECC
  29
  30 /* Register access macros */
  31 #define ecc_readl(add, reg)                             \
  32         readl(add + ATMEL_ECC_##reg)
  33 #define ecc_writel(add, reg, value)                     \
  34         writel((value), add + ATMEL_ECC_##reg)
  35
  36 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  37
  38 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  39
  40 #ifdef CONFIG_SPL_BUILD
  41 #undef CONFIG_SYS_NAND_ONFI_DETECTION
  42 #endif
  43
  44 struct atmel_nand_host {
  45         struct pmecc_regs __iomem *pmecc;
  46         struct pmecc_errloc_regs __iomem *pmerrloc;
  47         void __iomem            *pmecc_rom_base;
  48
  49         u8              pmecc_corr_cap;
  50         u16             pmecc_sector_size;
  51         u32             pmecc_index_table_offset;
  52         u32             pmecc_version;
  53
  54         int             pmecc_bytes_per_sector;
  55         int             pmecc_sector_number;
  56         int             pmecc_degree;   /* Degree of remainders */
  57         int             pmecc_cw_len;   /* Length of codeword */
  58
  59         /* lookup table for alpha_to and index_of */
  60         void __iomem    *pmecc_alpha_to;
  61         void __iomem    *pmecc_index_of;
  62
  63         /* data for pmecc computation */
  64         int16_t *pmecc_smu;
  65         int16_t *pmecc_partial_syn;
  66         int16_t *pmecc_si;
  67         int16_t *pmecc_lmu; /* polynomal order */
  68         int     *pmecc_mu;
  69         int     *pmecc_dmu;
  70         int     *pmecc_delta;
  71 };
  72
  73 static struct atmel_nand_host pmecc_host;
  74 static struct nand_ecclayout atmel_pmecc_oobinfo;
  75
  76 /*
  77  * Return number of ecc bytes per sector according to sector size and
  78  * correction capability
  79  *
  80  * Following table shows what at91 PMECC supported:
  81  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  82  * =====================        ================        =================
  83  *                2-bits                 4-bytes                  4-bytes
  84  *                4-bits                 7-bytes                  7-bytes
  85  *                8-bits                13-bytes                 14-bytes
  86  *               12-bits                20-bytes                 21-bytes
  87  *               24-bits                39-bytes                 42-bytes
  88  *               32-bits                52-bytes                 56-bytes
  89  */
  90 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  91 {
  92         int m = 12 + sector_size / 512;
  93         return (m * cap + 7) / 8;
  94 }
  95
  96 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  97         int oobsize, int ecc_len)
  98 {
  99         int i;
 100
 101         layout->eccbytes = ecc_len;
 102
 103         /* ECC will occupy the last ecc_len bytes continuously */
 104         for (i = 0; i < ecc_len; i++)
 105                 layout->eccpos[i] = oobsize - ecc_len + i;
 106
 107         layout->oobfree[0].offset = 2;
 108         layout->oobfree[0].length =
 109                 oobsize - ecc_len - layout->oobfree[0].offset;
 110 }
 111
 112 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 113 {
 114         int table_size;
 115
 116         table_size = host->pmecc_sector_size == 512 ?
 117                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 118
 119         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 120         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 121                         table_size * sizeof(int16_t);
 122 }
 123
 124 static void pmecc_data_free(struct atmel_nand_host *host)
 125 {
 126         free(host->pmecc_partial_syn);
 127         free(host->pmecc_si);
 128         free(host->pmecc_lmu);
 129         free(host->pmecc_smu);
 130         free(host->pmecc_mu);
 131         free(host->pmecc_dmu);
 132         free(host->pmecc_delta);
 133 }
 134
 135 static int pmecc_data_alloc(struct atmel_nand_host *host)
 136 {
 137         const int cap = host->pmecc_corr_cap;
 138         int size;
 139
 140         size = (2 * cap + 1) * sizeof(int16_t);
 141         host->pmecc_partial_syn = malloc(size);
 142         host->pmecc_si = malloc(size);
 143         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 144         host->pmecc_smu = malloc((cap + 2) * size);
 145
 146         size = (cap + 1) * sizeof(int);
 147         host->pmecc_mu = malloc(size);
 148         host->pmecc_dmu = malloc(size);
 149         host->pmecc_delta = malloc(size);
 150
 151         if (host->pmecc_partial_syn &&
 152                         host->pmecc_si &&
 153                         host->pmecc_lmu &&
 154                         host->pmecc_smu &&
 155                         host->pmecc_mu &&
 156                         host->pmecc_dmu &&
 157                         host->pmecc_delta)
 158                 return 0;
 159
 160         /* error happened */
 161         pmecc_data_free(host);
 162         return -ENOMEM;
 163
 164 }
 165
 166 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 167 {
 168         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 169         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 170         int i;
 171         uint32_t value;
 172
 173         /* Fill odd syndromes */
 174         for (i = 0; i < host->pmecc_corr_cap; i++) {
 175                 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
 176                 if (i & 1)
 177                         value >>= 16;
 178                 value &= 0xffff;
 179                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 180         }
 181 }
 182
 183 static void pmecc_substitute(struct mtd_info *mtd)
 184 {
 185         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 186         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 187         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 188         int16_t __iomem *index_of = host->pmecc_index_of;
 189         int16_t *partial_syn = host->pmecc_partial_syn;
 190         const int cap = host->pmecc_corr_cap;
 191         int16_t *si;
 192         int i, j;
 193
 194         /* si[] is a table that holds the current syndrome value,
 195          * an element of that table belongs to the field
 196          */
 197         si = host->pmecc_si;
 198
 199         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 200
 201         /* Computation 2t syndromes based on S(x) */
 202         /* Odd syndromes */
 203         for (i = 1; i < 2 * cap; i += 2) {
 204                 for (j = 0; j < host->pmecc_degree; j++) {
 205                         if (partial_syn[i] & (0x1 << j))
 206                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 207                 }
 208         }
 209         /* Even syndrome = (Odd syndrome) ** 2 */
 210         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 211                 if (si[j] == 0) {
 212                         si[i] = 0;
 213                 } else {
 214                         int16_t tmp;
 215
 216                         tmp = readw(index_of + si[j]);
 217                         tmp = (tmp * 2) % host->pmecc_cw_len;
 218                         si[i] = readw(alpha_to + tmp);
 219                 }
 220         }
 221 }
 222
 223 /*
 224  * This function defines a Berlekamp iterative procedure for
 225  * finding the value of the error location polynomial.
 226  * The input is si[], initialize by pmecc_substitute().
 227  * The output is smu[][].
 228  *
 229  * This function is written according to chip datasheet Chapter:
 230  * Find the Error Location Polynomial Sigma(x) of Section:
 231  * Programmable Multibit ECC Control (PMECC).
 232  */
 233 static void pmecc_get_sigma(struct mtd_info *mtd)
 234 {
 235         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 236         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 237
 238         int16_t *lmu = host->pmecc_lmu;
 239         int16_t *si = host->pmecc_si;
 240         int *mu = host->pmecc_mu;
 241         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 242         int *delta = host->pmecc_delta; /* Delta order */
 243         int cw_len = host->pmecc_cw_len;
 244         const int16_t cap = host->pmecc_corr_cap;
 245         const int num = 2 * cap + 1;
 246         int16_t __iomem *index_of = host->pmecc_index_of;
 247         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 248         int i, j, k;
 249         uint32_t dmu_0_count, tmp;
 250         int16_t *smu = host->pmecc_smu;
 251
 252         /* index of largest delta */
 253         int ro;
 254         int largest;
 255         int diff;
 256
 257         /* Init the Sigma(x) */
 258         memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
 259
 260         dmu_0_count = 0;
 261
 262         /* First Row */
 263
 264         /* Mu */
 265         mu[0] = -1;
 266
 267         smu[0] = 1;
 268
 269         /* discrepancy set to 1 */
 270         dmu[0] = 1;
 271         /* polynom order set to 0 */
 272         lmu[0] = 0;
 273         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 274         delta[0] = -1;
 275
 276         /* Second Row */
 277
 278         /* Mu */
 279         mu[1] = 0;
 280         /* Sigma(x) set to 1 */
 281         smu[num] = 1;
 282
 283         /* discrepancy set to S1 */
 284         dmu[1] = si[1];
 285
 286         /* polynom order set to 0 */
 287         lmu[1] = 0;
 288
 289         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 290         delta[1] = 0;
 291
 292         for (i = 1; i <= cap; i++) {
 293                 mu[i + 1] = i << 1;
 294                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 295                 /* check if discrepancy is set to 0 */
 296                 if (dmu[i] == 0) {
 297                         dmu_0_count++;
 298
 299                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 300                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 301                                 tmp += 2;
 302                         else
 303                                 tmp += 1;
 304
 305                         if (dmu_0_count == tmp) {
 306                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 307                                         smu[(cap + 1) * num + j] =
 308                                                         smu[i * num + j];
 309
 310                                 lmu[cap + 1] = lmu[i];
 311                                 return;
 312                         }
 313
 314                         /* copy polynom */
 315                         for (j = 0; j <= lmu[i] >> 1; j++)
 316                                 smu[(i + 1) * num + j] = smu[i * num + j];
 317
 318                         /* copy previous polynom order to the next */
 319                         lmu[i + 1] = lmu[i];
 320                 } else {
 321                         ro = 0;
 322                         largest = -1;
 323                         /* find largest delta with dmu != 0 */
 324                         for (j = 0; j < i; j++) {
 325                                 if ((dmu[j]) && (delta[j] > largest)) {
 326                                         largest = delta[j];
 327                                         ro = j;
 328                                 }
 329                         }
 330
 331                         /* compute difference */
 332                         diff = (mu[i] - mu[ro]);
 333
 334                         /* Compute degree of the new smu polynomial */
 335                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 336                                 lmu[i + 1] = lmu[i];
 337                         else
 338                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 339
 340                         /* Init smu[i+1] with 0 */
 341                         for (k = 0; k < num; k++)
 342                                 smu[(i + 1) * num + k] = 0;
 343
 344                         /* Compute smu[i+1] */
 345                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 346                                 int16_t a, b, c;
 347
 348                                 if (!(smu[ro * num + k] && dmu[i]))
 349                                         continue;
 350                                 a = readw(index_of + dmu[i]);
 351                                 b = readw(index_of + dmu[ro]);
 352                                 c = readw(index_of + smu[ro * num + k]);
 353                                 tmp = a + (cw_len - b) + c;
 354                                 a = readw(alpha_to + tmp % cw_len);
 355                                 smu[(i + 1) * num + (k + diff)] = a;
 356                         }
 357
 358                         for (k = 0; k <= lmu[i] >> 1; k++)
 359                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 360                 }
 361
 362                 /* End Computing Sigma (Mu+1) and L(mu) */
 363                 /* In either case compute delta */
 364                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 365
 366                 /* Do not compute discrepancy for the last iteration */
 367                 if (i >= cap)
 368                         continue;
 369
 370                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 371                         tmp = 2 * (i - 1);
 372                         if (k == 0) {
 373                                 dmu[i + 1] = si[tmp + 3];
 374                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 375                                 int16_t a, b, c;
 376                                 a = readw(index_of +
 377                                                 smu[(i + 1) * num + k]);
 378                                 b = si[2 * (i - 1) + 3 - k];
 379                                 c = readw(index_of + b);
 380                                 tmp = a + c;
 381                                 tmp %= cw_len;
 382                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 383                                         dmu[i + 1];
 384                         }
 385                 }
 386         }
 387 }
 388
 389 static int pmecc_err_location(struct mtd_info *mtd)
 390 {
 391         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 392         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 393         const int cap = host->pmecc_corr_cap;
 394         const int num = 2 * cap + 1;
 395         int sector_size = host->pmecc_sector_size;
 396         int err_nbr = 0;        /* number of error */
 397         int roots_nbr;          /* number of roots */
 398         int i;
 399         uint32_t val;
 400         int16_t *smu = host->pmecc_smu;
 401         int timeout = PMECC_MAX_TIMEOUT_US;
 402
 403         pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
 404
 405         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 406                 pmecc_writel(host->pmerrloc, sigma[i],
 407                              smu[(cap + 1) * num + i]);
 408                 err_nbr++;
 409         }
 410
 411         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 412         if (sector_size == 1024)
 413                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 414
 415         pmecc_writel(host->pmerrloc, elcfg, val);
 416         pmecc_writel(host->pmerrloc, elen,
 417                      sector_size * 8 + host->pmecc_degree * cap);
 418
 419         while (--timeout) {
 420                 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
 421                         break;
 422                 WATCHDOG_RESET();
 423                 udelay(1);
 424         }
 425
 426         if (!timeout) {
 427                 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
 428                 return -1;
 429         }
 430
 431         roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
 432                         >> 8;
 433         /* Number of roots == degree of smu hence <= cap */
 434         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 435                 return err_nbr - 1;
 436
 437         /* Number of roots does not match the degree of smu
 438          * unable to correct error */
 439         return -1;
 440 }
 441
 442 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 443                 int sector_num, int extra_bytes, int err_nbr)
 444 {
 445         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 446         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 447         int i = 0;
 448         int byte_pos, bit_pos, sector_size, pos;
 449         uint32_t tmp;
 450         uint8_t err_byte;
 451
 452         sector_size = host->pmecc_sector_size;
 453
 454         while (err_nbr) {
 455                 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
 456                 byte_pos = tmp / 8;
 457                 bit_pos  = tmp % 8;
 458
 459                 if (byte_pos >= (sector_size + extra_bytes))
 460                         BUG();  /* should never happen */
 461
 462                 if (byte_pos < sector_size) {
 463                         err_byte = *(buf + byte_pos);
 464                         *(buf + byte_pos) ^= (1 << bit_pos);
 465
 466                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 467                         dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 468                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 469                 } else {
 470                         /* Bit flip in OOB area */
 471                         tmp = sector_num * host->pmecc_bytes_per_sector
 472                                         + (byte_pos - sector_size);
 473                         err_byte = ecc[tmp];
 474                         ecc[tmp] ^= (1 << bit_pos);
 475
 476                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 477                         dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 478                                 pos, bit_pos, err_byte, ecc[tmp]);
 479                 }
 480
 481                 i++;
 482                 err_nbr--;
 483         }
 484
 485         return;
 486 }
 487
 488 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 489         u8 *ecc)
 490 {
 491         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 492         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 493         int i, err_nbr, eccbytes;
 494         uint8_t *buf_pos;
 495
 496         /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
 497         if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
 498                 goto normal_check;
 499
 500         eccbytes = nand_chip->ecc.bytes;
 501         for (i = 0; i < eccbytes; i++)
 502                 if (ecc[i] != 0xff)
 503                         goto normal_check;
 504         /* Erased page, return OK */
 505         return 0;
 506
 507 normal_check:
 508         for (i = 0; i < host->pmecc_sector_number; i++) {
 509                 err_nbr = 0;
 510                 if (pmecc_stat & 0x1) {
 511                         buf_pos = buf + i * host->pmecc_sector_size;
 512
 513                         pmecc_gen_syndrome(mtd, i);
 514                         pmecc_substitute(mtd);
 515                         pmecc_get_sigma(mtd);
 516
 517                         err_nbr = pmecc_err_location(mtd);
 518                         if (err_nbr == -1) {
 519                                 dev_err(host->dev, "PMECC: Too many errors\n");
 520                                 mtd->ecc_stats.failed++;
 521                                 return -EBADMSG;
 522                         } else {
 523                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 524                                         host->pmecc_bytes_per_sector, err_nbr);
 525                                 mtd->ecc_stats.corrected += err_nbr;
 526                         }
 527                 }
 528                 pmecc_stat >>= 1;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 535         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 536 {
 537         struct atmel_nand_host *host = nand_get_controller_data(chip);
 538         int eccsize = chip->ecc.size;
 539         uint8_t *oob = chip->oob_poi;
 540         uint32_t *eccpos = chip->ecc.layout->eccpos;
 541         uint32_t stat;
 542         int timeout = PMECC_MAX_TIMEOUT_US;
 543
 544         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 545         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 546         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 547                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 548
 549         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 550         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 551
 552         chip->read_buf(mtd, buf, eccsize);
 553         chip->read_buf(mtd, oob, mtd->oobsize);
 554
 555         while (--timeout) {
 556                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 557                         break;
 558                 WATCHDOG_RESET();
 559                 udelay(1);
 560         }
 561
 562         if (!timeout) {
 563                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
 564                 return -1;
 565         }
 566
 567         stat = pmecc_readl(host->pmecc, isr);
 568         if (stat != 0)
 569                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 570                         return -EBADMSG;
 571
 572         return 0;
 573 }
 574
 575 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 576                 struct nand_chip *chip, const uint8_t *buf,
 577                 int oob_required, int page)
 578 {
 579         struct atmel_nand_host *host = nand_get_controller_data(chip);
 580         uint32_t *eccpos = chip->ecc.layout->eccpos;
 581         int i, j;
 582         int timeout = PMECC_MAX_TIMEOUT_US;
 583
 584         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 585         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 586
 587         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 588                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 589
 590         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 591         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 592
 593         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 594
 595         while (--timeout) {
 596                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 597                         break;
 598                 WATCHDOG_RESET();
 599                 udelay(1);
 600         }
 601
 602         if (!timeout) {
 603                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
 604                 goto out;
 605         }
 606
 607         for (i = 0; i < host->pmecc_sector_number; i++) {
 608                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 609                         int pos;
 610
 611                         pos = i * host->pmecc_bytes_per_sector + j;
 612                         chip->oob_poi[eccpos[pos]] =
 613                                 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
 614                 }
 615         }
 616         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 617 out:
 618         return 0;
 619 }
 620
 621 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 622 {
 623         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 624         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 625         uint32_t val = 0;
 626         struct nand_ecclayout *ecc_layout;
 627
 628         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 629         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 630
 631         switch (host->pmecc_corr_cap) {
 632         case 2:
 633                 val = PMECC_CFG_BCH_ERR2;
 634                 break;
 635         case 4:
 636                 val = PMECC_CFG_BCH_ERR4;
 637                 break;
 638         case 8:
 639                 val = PMECC_CFG_BCH_ERR8;
 640                 break;
 641         case 12:
 642                 val = PMECC_CFG_BCH_ERR12;
 643                 break;
 644         case 24:
 645                 val = PMECC_CFG_BCH_ERR24;
 646                 break;
 647         case 32:
 648                 val = PMECC_CFG_BCH_ERR32;
 649                 break;
 650         }
 651
 652         if (host->pmecc_sector_size == 512)
 653                 val |= PMECC_CFG_SECTOR512;
 654         else if (host->pmecc_sector_size == 1024)
 655                 val |= PMECC_CFG_SECTOR1024;
 656
 657         switch (host->pmecc_sector_number) {
 658         case 1:
 659                 val |= PMECC_CFG_PAGE_1SECTOR;
 660                 break;
 661         case 2:
 662                 val |= PMECC_CFG_PAGE_2SECTORS;
 663                 break;
 664         case 4:
 665                 val |= PMECC_CFG_PAGE_4SECTORS;
 666                 break;
 667         case 8:
 668                 val |= PMECC_CFG_PAGE_8SECTORS;
 669                 break;
 670         }
 671
 672         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 673                 | PMECC_CFG_AUTO_DISABLE);
 674         pmecc_writel(host->pmecc, cfg, val);
 675
 676         ecc_layout = nand_chip->ecc.layout;
 677         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 678         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 679         pmecc_writel(host->pmecc, eaddr,
 680                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 681         /* See datasheet about PMECC Clock Control Register */
 682         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 683         pmecc_writel(host->pmecc, idr, 0xff);
 684         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 685 }
 686
 687 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 688 /*
 689  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
 690  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
 691  *                    ONFI ECC parameters.
 692  * @host: point to an atmel_nand_host structure.
 693  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
 694  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
 695  * @chip: point to an nand_chip structure.
 696  * @cap: store the ONFI ECC correct bits capbility
 697  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 698  *
 699  * Return 0 if success. otherwise return the error code.
 700  */
 701 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 702                 struct nand_chip *chip,
 703                 int *cap, int *sector_size)
 704 {
 705         /* Get ECC requirement from ONFI parameters */
 706         *cap = *sector_size = 0;
 707         if (chip->onfi_version) {
 708                 *cap = chip->ecc_strength_ds;
 709                 *sector_size = chip->ecc_step_ds;
 710                 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
 711                          *cap, *sector_size);
 712         }
 713
 714         if (*cap == 0 && *sector_size == 0) {
 715                 /* Non-ONFI compliant */
 716                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
 717                 *cap = 2;
 718                 *sector_size = 512;
 719         }
 720
 721         /* If head file doesn't specify then use the one in ONFI parameters */
 722         if (host->pmecc_corr_cap == 0) {
 723                 /* use the most fitable ecc bits (the near bigger one ) */
 724                 if (*cap <= 2)
 725                         host->pmecc_corr_cap = 2;
 726                 else if (*cap <= 4)
 727                         host->pmecc_corr_cap = 4;
 728                 else if (*cap <= 8)
 729                         host->pmecc_corr_cap = 8;
 730                 else if (*cap <= 12)
 731                         host->pmecc_corr_cap = 12;
 732                 else if (*cap <= 24)
 733                         host->pmecc_corr_cap = 24;
 734                 else
 735 #ifdef CONFIG_SAMA5D2
 736                         host->pmecc_corr_cap = 32;
 737 #else
 738                         host->pmecc_corr_cap = 24;
 739 #endif
 740         }
 741         if (host->pmecc_sector_size == 0) {
 742                 /* use the most fitable sector size (the near smaller one ) */
 743                 if (*sector_size >= 1024)
 744                         host->pmecc_sector_size = 1024;
 745                 else if (*sector_size >= 512)
 746                         host->pmecc_sector_size = 512;
 747                 else
 748                         return -EINVAL;
 749         }
 750         return 0;
 751 }
 752 #endif
 753
 754 #if defined(NO_GALOIS_TABLE_IN_ROM)
 755 static uint16_t *pmecc_galois_table;
 756 static inline int deg(unsigned int poly)
 757 {
 758         /* polynomial degree is the most-significant bit index */
 759         return fls(poly) - 1;
 760 }
 761
 762 static int build_gf_tables(int mm, unsigned int poly,
 763                            int16_t *index_of, int16_t *alpha_to)
 764 {
 765         unsigned int i, x = 1;
 766         const unsigned int k = 1 << deg(poly);
 767         unsigned int nn = (1 << mm) - 1;
 768
 769         /* primitive polynomial must be of degree m */
 770         if (k != (1u << mm))
 771                 return -EINVAL;
 772
 773         for (i = 0; i < nn; i++) {
 774                 alpha_to[i] = x;
 775                 index_of[x] = i;
 776                 if (i && (x == 1))
 777                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
 778                         return -EINVAL;
 779                 x <<= 1;
 780                 if (x & k)
 781                         x ^= poly;
 782         }
 783
 784         alpha_to[nn] = 1;
 785         index_of[0] = 0;
 786
 787         return 0;
 788 }
 789
 790 static uint16_t *create_lookup_table(int sector_size)
 791 {
 792         int degree = (sector_size == 512) ?
 793                         PMECC_GF_DIMENSION_13 :
 794                         PMECC_GF_DIMENSION_14;
 795         unsigned int poly = (sector_size == 512) ?
 796                         PMECC_GF_13_PRIMITIVE_POLY :
 797                         PMECC_GF_14_PRIMITIVE_POLY;
 798         int table_size = (sector_size == 512) ?
 799                         PMECC_INDEX_TABLE_SIZE_512 :
 800                         PMECC_INDEX_TABLE_SIZE_1024;
 801
 802         int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
 803         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
 804                 return NULL;
 805
 806         return (uint16_t *)addr;
 807 }
 808 #endif
 809
 810 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 811                 struct mtd_info *mtd)
 812 {
 813         struct atmel_nand_host *host;
 814         int cap, sector_size;
 815
 816         host = &pmecc_host;
 817         nand_set_controller_data(nand, host);
 818
 819         nand->ecc.mode = NAND_ECC_HW;
 820         nand->ecc.calculate = NULL;
 821         nand->ecc.correct = NULL;
 822         nand->ecc.hwctl = NULL;
 823
 824 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 825         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
 826
 827 #ifdef CONFIG_PMECC_CAP
 828         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 829 #endif
 830 #ifdef CONFIG_PMECC_SECTOR_SIZE
 831         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 832 #endif
 833         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
 834          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
 835          * from ONFI.
 836          */
 837         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
 838                 dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
 839                         cap, sector_size);
 840                 return -EINVAL;
 841         }
 842
 843         if (cap > host->pmecc_corr_cap)
 844                 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
 845                                 host->pmecc_corr_cap, cap);
 846         if (sector_size < host->pmecc_sector_size)
 847                 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
 848                                 host->pmecc_sector_size, sector_size);
 849 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
 850         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 851         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 852 #endif
 853
 854         cap = host->pmecc_corr_cap;
 855         sector_size = host->pmecc_sector_size;
 856
 857         /* TODO: need check whether cap & sector_size is validate */
 858 #if defined(NO_GALOIS_TABLE_IN_ROM)
 859         /*
 860          * As pmecc_rom_base is the begin of the gallois field table, So the
 861          * index offset just set as 0.
 862          */
 863         host->pmecc_index_table_offset = 0;
 864 #else
 865         if (host->pmecc_sector_size == 512)
 866                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 867         else
 868                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 869 #endif
 870
 871         pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
 872                  cap, sector_size);
 873
 874         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 875         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 876                         ATMEL_BASE_PMERRLOC;
 877 #if defined(NO_GALOIS_TABLE_IN_ROM)
 878         pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
 879         if (!pmecc_galois_table) {
 880                 dev_err(host->dev, "out of memory\n");
 881                 return -ENOMEM;
 882         }
 883
 884         host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
 885 #else
 886         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 887 #endif
 888
 889         /* ECC is calculated for the whole page (1 step) */
 890         nand->ecc.size = mtd->writesize;
 891
 892         /* set ECC page size and oob layout */
 893         switch (mtd->writesize) {
 894         case 2048:
 895         case 4096:
 896         case 8192:
 897                 host->pmecc_degree = (sector_size == 512) ?
 898                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 899                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 900                 host->pmecc_sector_number = mtd->writesize / sector_size;
 901                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 902                         cap, sector_size);
 903                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 904                 host->pmecc_index_of = host->pmecc_rom_base +
 905                         host->pmecc_index_table_offset;
 906
 907                 nand->ecc.steps = 1;
 908                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 909                                        host->pmecc_sector_number;
 910
 911                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
 912                         dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
 913                                         MTD_MAX_ECCPOS_ENTRIES_LARGE);
 914                         return -EINVAL;
 915                 }
 916
 917                 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
 918                         dev_err(host->dev, "No room for ECC bytes\n");
 919                         return -EINVAL;
 920                 }
 921                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 922                                         mtd->oobsize,
 923                                         nand->ecc.bytes);
 924                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 925                 break;
 926         case 512:
 927         case 1024:
 928                 /* TODO */
 929                 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
 930         default:
 931                 /* page size not handled by HW ECC */
 932                 /* switching back to soft ECC */
 933                 nand->ecc.mode = NAND_ECC_SOFT;
 934                 nand->ecc.read_page = NULL;
 935                 nand->ecc.postpad = 0;
 936                 nand->ecc.prepad = 0;
 937                 nand->ecc.bytes = 0;
 938                 return 0;
 939         }
 940
 941         /* Allocate data for PMECC computation */
 942         if (pmecc_data_alloc(host)) {
 943                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
 944                 return -ENOMEM;
 945         }
 946
 947         nand->options |= NAND_NO_SUBPAGE_WRITE;
 948         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 949         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 950         nand->ecc.strength = cap;
 951
 952         /* Check the PMECC ip version */
 953         host->pmecc_version = pmecc_readl(host->pmerrloc, version);
 954         dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
 955
 956         atmel_pmecc_core_init(mtd);
 957
 958         return 0;
 959 }
 960
 961 #else
 962
 963 /* oob layout for large page size
 964  * bad block info is on bytes 0 and 1
 965  * the bytes have to be consecutives to avoid
 966  * several NAND_CMD_RNDOUT during read
 967  */
 968 static struct nand_ecclayout atmel_oobinfo_large = {
 969         .eccbytes = 4,
 970         .eccpos = {60, 61, 62, 63},
 971         .oobfree = {
 972                 {2, 58}
 973         },
 974 };
 975
 976 /* oob layout for small page size
 977  * bad block info is on bytes 4 and 5
 978  * the bytes have to be consecutives to avoid
 979  * several NAND_CMD_RNDOUT during read
 980  */
 981 static struct nand_ecclayout atmel_oobinfo_small = {
 982         .eccbytes = 4,
 983         .eccpos = {0, 1, 2, 3},
 984         .oobfree = {
 985                 {6, 10}
 986         },
 987 };
 988
 989 /*
 990  * Calculate HW ECC
 991  *
 992  * function called after a write
 993  *
 994  * mtd:        MTD block structure
 995  * dat:        raw data (unused)
 996  * ecc_code:   buffer for ECC
 997  */
 998 static int atmel_nand_calculate(struct mtd_info *mtd,
 999                 const u_char *dat, unsigned char *ecc_code)
1000 {
1001         unsigned int ecc_value;
1002
1003         /* get the first 2 ECC bytes */
1004         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1005
1006         ecc_code[0] = ecc_value & 0xFF;
1007         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1008
1009         /* get the last 2 ECC bytes */
1010         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1011
1012         ecc_code[2] = ecc_value & 0xFF;
1013         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1014
1015         return 0;
1016 }
1017
1018 /*
1019  * HW ECC read page function
1020  *
1021  * mtd:        mtd info structure
1022  * chip:       nand chip info structure
1023  * buf:        buffer to store read data
1024  * oob_required:    caller expects OOB data read to chip->oob_poi
1025  */
1026 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1027                                 uint8_t *buf, int oob_required, int page)
1028 {
1029         int eccsize = chip->ecc.size;
1030         int eccbytes = chip->ecc.bytes;
1031         uint32_t *eccpos = chip->ecc.layout->eccpos;
1032         uint8_t *p = buf;
1033         uint8_t *oob = chip->oob_poi;
1034         uint8_t *ecc_pos;
1035         int stat;
1036
1037         /* read the page */
1038         chip->read_buf(mtd, p, eccsize);
1039
1040         /* move to ECC position if needed */
1041         if (eccpos[0] != 0) {
1042                 /* This only works on large pages
1043                  * because the ECC controller waits for
1044                  * NAND_CMD_RNDOUTSTART after the
1045                  * NAND_CMD_RNDOUT.
1046                  * anyway, for small pages, the eccpos[0] == 0
1047                  */
1048                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1049                                 mtd->writesize + eccpos[0], -1);
1050         }
1051
1052         /* the ECC controller needs to read the ECC just after the data */
1053         ecc_pos = oob + eccpos[0];
1054         chip->read_buf(mtd, ecc_pos, eccbytes);
1055
1056         /* check if there's an error */
1057         stat = chip->ecc.correct(mtd, p, oob, NULL);
1058
1059         if (stat < 0)
1060                 mtd->ecc_stats.failed++;
1061         else
1062                 mtd->ecc_stats.corrected += stat;
1063
1064         /* get back to oob start (end of page) */
1065         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1066
1067         /* read the oob */
1068         chip->read_buf(mtd, oob, mtd->oobsize);
1069
1070         return 0;
1071 }
1072
1073 /*
1074  * HW ECC Correction
1075  *
1076  * function called after a read
1077  *
1078  * mtd:        MTD block structure
1079  * dat:        raw data read from the chip
1080  * read_ecc:   ECC from the chip (unused)
1081  * isnull:     unused
1082  *
1083  * Detect and correct a 1 bit error for a page
1084  */
1085 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1086                 u_char *read_ecc, u_char *isnull)
1087 {
1088         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1089         unsigned int ecc_status;
1090         unsigned int ecc_word, ecc_bit;
1091
1092         /* get the status from the Status Register */
1093         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1094
1095         /* if there's no error */
1096         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1097                 return 0;
1098
1099         /* get error bit offset (4 bits) */
1100         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1101         /* get word address (12 bits) */
1102         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1103         ecc_word >>= 4;
1104
1105         /* if there are multiple errors */
1106         if (ecc_status & ATMEL_ECC_MULERR) {
1107                 /* check if it is a freshly erased block
1108                  * (filled with 0xff) */
1109                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1110                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1111                         /* the block has just been erased, return OK */
1112                         return 0;
1113                 }
1114                 /* it doesn't seems to be a freshly
1115                  * erased block.
1116                  * We can't correct so many errors */
1117                 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1118                                 " Unable to correct.\n");
1119                 return -EBADMSG;
1120         }
1121
1122         /* if there's a single bit error : we can correct it */
1123         if (ecc_status & ATMEL_ECC_ECCERR) {
1124                 /* there's nothing much to do here.
1125                  * the bit error is on the ECC itself.
1126                  */
1127                 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1128                                 " Nothing to correct\n");
1129                 return 0;
1130         }
1131
1132         dev_warn(host->dev, "atmel_nand : one bit error on data."
1133                         " (word offset in the page :"
1134                         " 0x%x bit offset : 0x%x)\n",
1135                         ecc_word, ecc_bit);
1136         /* correct the error */
1137         if (nand_chip->options & NAND_BUSWIDTH_16) {
1138                 /* 16 bits words */
1139                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1140         } else {
1141                 /* 8 bits words */
1142                 dat[ecc_word] ^= (1 << ecc_bit);
1143         }
1144         dev_warn(host->dev, "atmel_nand : error corrected\n");
1145         return 1;
1146 }
1147
1148 /*
1149  * Enable HW ECC : unused on most chips
1150  */
1151 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1152 {
1153 }
1154
1155 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1156 {
1157         nand->ecc.mode = NAND_ECC_HW;
1158         nand->ecc.calculate = atmel_nand_calculate;
1159         nand->ecc.correct = atmel_nand_correct;
1160         nand->ecc.hwctl = atmel_nand_hwctl;
1161         nand->ecc.read_page = atmel_nand_read_page;
1162         nand->ecc.bytes = 4;
1163         nand->ecc.strength = 4;
1164
1165         if (nand->ecc.mode == NAND_ECC_HW) {
1166                 /* ECC is calculated for the whole page (1 step) */
1167                 nand->ecc.size = mtd->writesize;
1168
1169                 /* set ECC page size and oob layout */
1170                 switch (mtd->writesize) {
1171                 case 512:
1172                         nand->ecc.layout = &atmel_oobinfo_small;
1173                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1174                                         ATMEL_ECC_PAGESIZE_528);
1175                         break;
1176                 case 1024:
1177                         nand->ecc.layout = &atmel_oobinfo_large;
1178                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1179                                         ATMEL_ECC_PAGESIZE_1056);
1180                         break;
1181                 case 2048:
1182                         nand->ecc.layout = &atmel_oobinfo_large;
1183                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1184                                         ATMEL_ECC_PAGESIZE_2112);
1185                         break;
1186                 case 4096:
1187                         nand->ecc.layout = &atmel_oobinfo_large;
1188                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1189                                         ATMEL_ECC_PAGESIZE_4224);
1190                         break;
1191                 default:
1192                         /* page size not handled by HW ECC */
1193                         /* switching back to soft ECC */
1194                         nand->ecc.mode = NAND_ECC_SOFT;
1195                         nand->ecc.calculate = NULL;
1196                         nand->ecc.correct = NULL;
1197                         nand->ecc.hwctl = NULL;
1198                         nand->ecc.read_page = NULL;
1199                         nand->ecc.postpad = 0;
1200                         nand->ecc.prepad = 0;
1201                         nand->ecc.bytes = 0;
1202                         break;
1203                 }
1204         }
1205
1206         return 0;
1207 }
1208
1209 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1210
1211 #endif /* CONFIG_ATMEL_NAND_HWECC */
1212
1213 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1214                                          int cmd, unsigned int ctrl)
1215 {
1216         struct nand_chip *this = mtd_to_nand(mtd);
1217
1218         if (ctrl & NAND_CTRL_CHANGE) {
1219                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1220                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1221                              | CONFIG_SYS_NAND_MASK_CLE);
1222
1223                 if (ctrl & NAND_CLE)
1224                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1225                 if (ctrl & NAND_ALE)
1226                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1227
1228 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1229                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1230                                     !(ctrl & NAND_NCE));
1231 #endif
1232                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1233         }
1234
1235         if (cmd != NAND_CMD_NONE)
1236                 writeb(cmd, this->IO_ADDR_W);
1237 }
1238
1239 #ifdef CONFIG_SYS_NAND_READY_PIN
1240 static int at91_nand_ready(struct mtd_info *mtd)
1241 {
1242         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1243 }
1244 #endif
1245
1246 #ifdef CONFIG_SPL_BUILD
1247 /* The following code is for SPL */
1248 static struct mtd_info *mtd;
1249 static struct nand_chip nand_chip;
1250
1251 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1252 {
1253         struct nand_chip *this = mtd_to_nand(mtd);
1254         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1255         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1256                         unsigned int ctrl) = this->cmd_ctrl;
1257
1258         while (!this->dev_ready(mtd))
1259                 ;
1260
1261         if (cmd == NAND_CMD_READOOB) {
1262                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1263                 cmd = NAND_CMD_READ0;
1264         }
1265
1266         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1267
1268         if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1269                 offs >>= 1;
1270
1271         hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1272         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1273         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1274         hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1275 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1276         hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1277 #endif
1278         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1279
1280         hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1281         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1282
1283         while (!this->dev_ready(mtd))
1284                 ;
1285
1286         return 0;
1287 }
1288
1289 static int nand_is_bad_block(int block)
1290 {
1291         struct nand_chip *this = mtd_to_nand(mtd);
1292
1293         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1294
1295         if (this->options & NAND_BUSWIDTH_16) {
1296                 if (readw(this->IO_ADDR_R) != 0xffff)
1297                         return 1;
1298         } else {
1299                 if (readb(this->IO_ADDR_R) != 0xff)
1300                         return 1;
1301         }
1302
1303         return 0;
1304 }
1305
1306 #ifdef CONFIG_SPL_NAND_ECC
1307 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1308 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1309                   CONFIG_SYS_NAND_ECCSIZE)
1310 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1311
1312 static int nand_read_page(int block, int page, void *dst)
1313 {
1314         struct nand_chip *this = mtd_to_nand(mtd);
1315         u_char ecc_calc[ECCTOTAL];
1316         u_char ecc_code[ECCTOTAL];
1317         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1318         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1319         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1320         int eccsteps = ECCSTEPS;
1321         int i;
1322         uint8_t *p = dst;
1323         nand_command(block, page, 0, NAND_CMD_READ0);
1324
1325         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1326                 if (this->ecc.mode != NAND_ECC_SOFT)
1327                         this->ecc.hwctl(mtd, NAND_ECC_READ);
1328                 this->read_buf(mtd, p, eccsize);
1329                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
1330         }
1331         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1332
1333         for (i = 0; i < ECCTOTAL; i++)
1334                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1335
1336         eccsteps = ECCSTEPS;
1337         p = dst;
1338
1339         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1340                 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1341
1342         return 0;
1343 }
1344
1345 int spl_nand_erase_one(int block, int page)
1346 {
1347         struct nand_chip *this = mtd_to_nand(mtd);
1348         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1349                         unsigned int ctrl) = this->cmd_ctrl;
1350         int page_addr;
1351
1352         if (nand_chip.select_chip)
1353                 nand_chip.select_chip(mtd, 0);
1354
1355         page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1356         hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1357         /* Row address */
1358         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1359         hwctrl(mtd, ((page_addr >> 8) & 0xff),
1360                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1361 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1362         /* One more address cycle for devices > 128MiB */
1363         hwctrl(mtd, (page_addr >> 16) & 0x0f,
1364                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1365 #endif
1366         hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1367
1368         while (!this->dev_ready(mtd))
1369                 ;
1370
1371         nand_deselect();
1372
1373         return 0;
1374 }
1375 #else
1376 static int nand_read_page(int block, int page, void *dst)
1377 {
1378         struct nand_chip *this = mtd_to_nand(mtd);
1379
1380         nand_command(block, page, 0, NAND_CMD_READ0);
1381         atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1382
1383         return 0;
1384 }
1385 #endif /* CONFIG_SPL_NAND_ECC */
1386
1387 int at91_nand_wait_ready(struct mtd_info *mtd)
1388 {
1389         struct nand_chip *this = mtd_to_nand(mtd);
1390
1391         udelay(this->chip_delay);
1392
1393         return 1;
1394 }
1395
1396 int board_nand_init(struct nand_chip *nand)
1397 {
1398         int ret = 0;
1399
1400         nand->ecc.mode = NAND_ECC_SOFT;
1401 #ifdef CONFIG_SYS_NAND_DBW_16
1402         nand->options = NAND_BUSWIDTH_16;
1403         nand->read_buf = nand_read_buf16;
1404 #else
1405         nand->read_buf = nand_read_buf;
1406 #endif
1407         nand->cmd_ctrl = at91_nand_hwcontrol;
1408 #ifdef CONFIG_SYS_NAND_READY_PIN
1409         nand->dev_ready = at91_nand_ready;
1410 #else
1411         nand->dev_ready = at91_nand_wait_ready;
1412 #endif
1413         nand->chip_delay = 20;
1414 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1415         nand->bbt_options |= NAND_BBT_USE_FLASH;
1416 #endif
1417
1418 #ifdef CONFIG_ATMEL_NAND_HWECC
1419 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1420         ret = atmel_pmecc_nand_init_params(nand, mtd);
1421 #endif
1422 #endif
1423
1424         return ret;
1425 }
1426
1427 void nand_init(void)
1428 {
1429         mtd = nand_to_mtd(&nand_chip);
1430         mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1431         mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1432         nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1433         nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1434         board_nand_init(&nand_chip);
1435
1436 #ifdef CONFIG_SPL_NAND_ECC
1437         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1438                 nand_chip.ecc.calculate = nand_calculate_ecc;
1439                 nand_chip.ecc.correct = nand_correct_data;
1440         }
1441 #endif
1442
1443         if (nand_chip.select_chip)
1444                 nand_chip.select_chip(mtd, 0);
1445 }
1446
1447 void nand_deselect(void)
1448 {
1449         if (nand_chip.select_chip)
1450                 nand_chip.select_chip(mtd, -1);
1451 }
1452
1453 #include "nand_spl_loaders.c"
1454
1455 #else
1456
1457 #ifndef CONFIG_SYS_NAND_BASE_LIST
1458 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1459 #endif
1460 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1461 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1462
1463 int atmel_nand_chip_init(int devnum, ulong base_addr)
1464 {
1465         int ret;
1466         struct nand_chip *nand = &nand_chip[devnum];
1467         struct mtd_info *mtd = nand_to_mtd(nand);
1468
1469         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1470
1471 #ifdef CONFIG_NAND_ECC_BCH
1472         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1473 #else
1474         nand->ecc.mode = NAND_ECC_SOFT;
1475 #endif
1476 #ifdef CONFIG_SYS_NAND_DBW_16
1477         nand->options = NAND_BUSWIDTH_16;
1478 #endif
1479         nand->cmd_ctrl = at91_nand_hwcontrol;
1480 #ifdef CONFIG_SYS_NAND_READY_PIN
1481         nand->dev_ready = at91_nand_ready;
1482 #endif
1483         nand->chip_delay = 75;
1484 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1485         nand->bbt_options |= NAND_BBT_USE_FLASH;
1486 #endif
1487
1488         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1489         if (ret)
1490                 return ret;
1491
1492 #ifdef CONFIG_ATMEL_NAND_HWECC
1493 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1494         ret = atmel_pmecc_nand_init_params(nand, mtd);
1495 #else
1496         ret = atmel_hwecc_nand_init_param(nand, mtd);
1497 #endif
1498         if (ret)
1499                 return ret;
1500 #endif
1501
1502         ret = nand_scan_tail(mtd);
1503         if (!ret)
1504                 nand_register(devnum, mtd);
1505
1506         return ret;
1507 }
1508
1509 void board_nand_init(void)
1510 {
1511         int i;
1512         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1513                 if (atmel_nand_chip_init(i, base_addr[i]))
1514                         dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1515                                 i);
1516 }
1517 #endif /* CONFIG_SPL_BUILD */