drivers/mtd/nand/raw/atmel_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   8  *
   9  * Add Programmable Multibit ECC support for various AT91 SoC
  10  *     (C) Copyright 2012 ATMEL, Hong Xu
  11  */
  12
  13 #include <common.h>
  14 #include <log.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/gpio.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19 #include <linux/bitops.h>
  20 #include <linux/bug.h>
  21 #include <linux/delay.h>
  22
  23 #include <malloc.h>
  24 #include <nand.h>
  25 #include <watchdog.h>
  26 #include <linux/mtd/nand_ecc.h>
  27
  28 #ifdef CONFIG_ATMEL_NAND_HWECC
  29
  30 /* Register access macros */
  31 #define ecc_readl(add, reg)                             \
  32         readl(add + ATMEL_ECC_##reg)
  33 #define ecc_writel(add, reg, value)                     \
  34         writel((value), add + ATMEL_ECC_##reg)
  35
  36 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  37
  38 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  39
  40 #ifdef CONFIG_SPL_BUILD
  41 #undef CONFIG_SYS_NAND_ONFI_DETECTION
  42 #endif
  43
  44 struct atmel_nand_host {
  45         struct pmecc_regs __iomem *pmecc;
  46         struct pmecc_errloc_regs __iomem *pmerrloc;
  47         void __iomem            *pmecc_rom_base;
  48
  49         u8              pmecc_corr_cap;
  50         u16             pmecc_sector_size;
  51         u32             pmecc_index_table_offset;
  52         u32             pmecc_version;
  53
  54         int             pmecc_bytes_per_sector;
  55         int             pmecc_sector_number;
  56         int             pmecc_degree;   /* Degree of remainders */
  57         int             pmecc_cw_len;   /* Length of codeword */
  58
  59         /* lookup table for alpha_to and index_of */
  60         void __iomem    *pmecc_alpha_to;
  61         void __iomem    *pmecc_index_of;
  62
  63         /* data for pmecc computation */
  64         int16_t *pmecc_smu;
  65         int16_t *pmecc_partial_syn;
  66         int16_t *pmecc_si;
  67         int16_t *pmecc_lmu; /* polynomal order */
  68         int     *pmecc_mu;
  69         int     *pmecc_dmu;
  70         int     *pmecc_delta;
  71 };
  72
  73 static struct atmel_nand_host pmecc_host;
  74 static struct nand_ecclayout atmel_pmecc_oobinfo;
  75
  76 /*
  77  * Return number of ecc bytes per sector according to sector size and
  78  * correction capability
  79  *
  80  * Following table shows what at91 PMECC supported:
  81  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  82  * =====================        ================        =================
  83  *                2-bits                 4-bytes                  4-bytes
  84  *                4-bits                 7-bytes                  7-bytes
  85  *                8-bits                13-bytes                 14-bytes
  86  *               12-bits                20-bytes                 21-bytes
  87  *               24-bits                39-bytes                 42-bytes
  88  *               32-bits                52-bytes                 56-bytes
  89  */
  90 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  91 {
  92         int m = 12 + sector_size / 512;
  93         return (m * cap + 7) / 8;
  94 }
  95
  96 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  97         int oobsize, int ecc_len)
  98 {
  99         int i;
 100
 101         layout->eccbytes = ecc_len;
 102
 103         /* ECC will occupy the last ecc_len bytes continuously */
 104         for (i = 0; i < ecc_len; i++)
 105                 layout->eccpos[i] = oobsize - ecc_len + i;
 106
 107         layout->oobfree[0].offset = 2;
 108         layout->oobfree[0].length =
 109                 oobsize - ecc_len - layout->oobfree[0].offset;
 110 }
 111
 112 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 113 {
 114         int table_size;
 115
 116         table_size = host->pmecc_sector_size == 512 ?
 117                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 118
 119         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 120         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 121                         table_size * sizeof(int16_t);
 122 }
 123
 124 static void pmecc_data_free(struct atmel_nand_host *host)
 125 {
 126         free(host->pmecc_partial_syn);
 127         free(host->pmecc_si);
 128         free(host->pmecc_lmu);
 129         free(host->pmecc_smu);
 130         free(host->pmecc_mu);
 131         free(host->pmecc_dmu);
 132         free(host->pmecc_delta);
 133 }
 134
 135 static int pmecc_data_alloc(struct atmel_nand_host *host)
 136 {
 137         const int cap = host->pmecc_corr_cap;
 138         int size;
 139
 140         size = (2 * cap + 1) * sizeof(int16_t);
 141         host->pmecc_partial_syn = malloc(size);
 142         host->pmecc_si = malloc(size);
 143         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 144         host->pmecc_smu = malloc((cap + 2) * size);
 145
 146         size = (cap + 1) * sizeof(int);
 147         host->pmecc_mu = malloc(size);
 148         host->pmecc_dmu = malloc(size);
 149         host->pmecc_delta = malloc(size);
 150
 151         if (host->pmecc_partial_syn &&
 152                         host->pmecc_si &&
 153                         host->pmecc_lmu &&
 154                         host->pmecc_smu &&
 155                         host->pmecc_mu &&
 156                         host->pmecc_dmu &&
 157                         host->pmecc_delta)
 158                 return 0;
 159
 160         /* error happened */
 161         pmecc_data_free(host);
 162         return -ENOMEM;
 163
 164 }
 165
 166 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 167 {
 168         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 169         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 170         int i;
 171         uint32_t value;
 172
 173         /* Fill odd syndromes */
 174         for (i = 0; i < host->pmecc_corr_cap; i++) {
 175                 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
 176                 if (i & 1)
 177                         value >>= 16;
 178                 value &= 0xffff;
 179                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 180         }
 181 }
 182
 183 static void pmecc_substitute(struct mtd_info *mtd)
 184 {
 185         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 186         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 187         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 188         int16_t __iomem *index_of = host->pmecc_index_of;
 189         int16_t *partial_syn = host->pmecc_partial_syn;
 190         const int cap = host->pmecc_corr_cap;
 191         int16_t *si;
 192         int i, j;
 193
 194         /* si[] is a table that holds the current syndrome value,
 195          * an element of that table belongs to the field
 196          */
 197         si = host->pmecc_si;
 198
 199         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 200
 201         /* Computation 2t syndromes based on S(x) */
 202         /* Odd syndromes */
 203         for (i = 1; i < 2 * cap; i += 2) {
 204                 for (j = 0; j < host->pmecc_degree; j++) {
 205                         if (partial_syn[i] & (0x1 << j))
 206                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 207                 }
 208         }
 209         /* Even syndrome = (Odd syndrome) ** 2 */
 210         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 211                 if (si[j] == 0) {
 212                         si[i] = 0;
 213                 } else {
 214                         int16_t tmp;
 215
 216                         tmp = readw(index_of + si[j]);
 217                         tmp = (tmp * 2) % host->pmecc_cw_len;
 218                         si[i] = readw(alpha_to + tmp);
 219                 }
 220         }
 221 }
 222
 223 /*
 224  * This function defines a Berlekamp iterative procedure for
 225  * finding the value of the error location polynomial.
 226  * The input is si[], initialize by pmecc_substitute().
 227  * The output is smu[][].
 228  *
 229  * This function is written according to chip datasheet Chapter:
 230  * Find the Error Location Polynomial Sigma(x) of Section:
 231  * Programmable Multibit ECC Control (PMECC).
 232  */
 233 static void pmecc_get_sigma(struct mtd_info *mtd)
 234 {
 235         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 236         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 237
 238         int16_t *lmu = host->pmecc_lmu;
 239         int16_t *si = host->pmecc_si;
 240         int *mu = host->pmecc_mu;
 241         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 242         int *delta = host->pmecc_delta; /* Delta order */
 243         int cw_len = host->pmecc_cw_len;
 244         const int16_t cap = host->pmecc_corr_cap;
 245         const int num = 2 * cap + 1;
 246         int16_t __iomem *index_of = host->pmecc_index_of;
 247         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 248         int i, j, k;
 249         uint32_t dmu_0_count, tmp;
 250         int16_t *smu = host->pmecc_smu;
 251
 252         /* index of largest delta */
 253         int ro;
 254         int largest;
 255         int diff;
 256
 257         /* Init the Sigma(x) */
 258         memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
 259
 260         dmu_0_count = 0;
 261
 262         /* First Row */
 263
 264         /* Mu */
 265         mu[0] = -1;
 266
 267         smu[0] = 1;
 268
 269         /* discrepancy set to 1 */
 270         dmu[0] = 1;
 271         /* polynom order set to 0 */
 272         lmu[0] = 0;
 273         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 274         delta[0] = -1;
 275
 276         /* Second Row */
 277
 278         /* Mu */
 279         mu[1] = 0;
 280         /* Sigma(x) set to 1 */
 281         smu[num] = 1;
 282
 283         /* discrepancy set to S1 */
 284         dmu[1] = si[1];
 285
 286         /* polynom order set to 0 */
 287         lmu[1] = 0;
 288
 289         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 290         delta[1] = 0;
 291
 292         for (i = 1; i <= cap; i++) {
 293                 mu[i + 1] = i << 1;
 294                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 295                 /* check if discrepancy is set to 0 */
 296                 if (dmu[i] == 0) {
 297                         dmu_0_count++;
 298
 299                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 300                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 301                                 tmp += 2;
 302                         else
 303                                 tmp += 1;
 304
 305                         if (dmu_0_count == tmp) {
 306                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 307                                         smu[(cap + 1) * num + j] =
 308                                                         smu[i * num + j];
 309
 310                                 lmu[cap + 1] = lmu[i];
 311                                 return;
 312                         }
 313
 314                         /* copy polynom */
 315                         for (j = 0; j <= lmu[i] >> 1; j++)
 316                                 smu[(i + 1) * num + j] = smu[i * num + j];
 317
 318                         /* copy previous polynom order to the next */
 319                         lmu[i + 1] = lmu[i];
 320                 } else {
 321                         ro = 0;
 322                         largest = -1;
 323                         /* find largest delta with dmu != 0 */
 324                         for (j = 0; j < i; j++) {
 325                                 if ((dmu[j]) && (delta[j] > largest)) {
 326                                         largest = delta[j];
 327                                         ro = j;
 328                                 }
 329                         }
 330
 331                         /* compute difference */
 332                         diff = (mu[i] - mu[ro]);
 333
 334                         /* Compute degree of the new smu polynomial */
 335                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 336                                 lmu[i + 1] = lmu[i];
 337                         else
 338                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 339
 340                         /* Init smu[i+1] with 0 */
 341                         for (k = 0; k < num; k++)
 342                                 smu[(i + 1) * num + k] = 0;
 343
 344                         /* Compute smu[i+1] */
 345                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 346                                 int16_t a, b, c;
 347
 348                                 if (!(smu[ro * num + k] && dmu[i]))
 349                                         continue;
 350                                 a = readw(index_of + dmu[i]);
 351                                 b = readw(index_of + dmu[ro]);
 352                                 c = readw(index_of + smu[ro * num + k]);
 353                                 tmp = a + (cw_len - b) + c;
 354                                 a = readw(alpha_to + tmp % cw_len);
 355                                 smu[(i + 1) * num + (k + diff)] = a;
 356                         }
 357
 358                         for (k = 0; k <= lmu[i] >> 1; k++)
 359                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 360                 }
 361
 362                 /* End Computing Sigma (Mu+1) and L(mu) */
 363                 /* In either case compute delta */
 364                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 365
 366                 /* Do not compute discrepancy for the last iteration */
 367                 if (i >= cap)
 368                         continue;
 369
 370                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 371                         tmp = 2 * (i - 1);
 372                         if (k == 0) {
 373                                 dmu[i + 1] = si[tmp + 3];
 374                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 375                                 int16_t a, b, c;
 376                                 a = readw(index_of +
 377                                                 smu[(i + 1) * num + k]);
 378                                 b = si[2 * (i - 1) + 3 - k];
 379                                 c = readw(index_of + b);
 380                                 tmp = a + c;
 381                                 tmp %= cw_len;
 382                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 383                                         dmu[i + 1];
 384                         }
 385                 }
 386         }
 387 }
 388
 389 static int pmecc_err_location(struct mtd_info *mtd)
 390 {
 391         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 392         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 393         const int cap = host->pmecc_corr_cap;
 394         const int num = 2 * cap + 1;
 395         int sector_size = host->pmecc_sector_size;
 396         int err_nbr = 0;        /* number of error */
 397         int roots_nbr;          /* number of roots */
 398         int i;
 399         uint32_t val;
 400         int16_t *smu = host->pmecc_smu;
 401         int timeout = PMECC_MAX_TIMEOUT_US;
 402
 403         pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
 404
 405         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 406                 pmecc_writel(host->pmerrloc, sigma[i],
 407                              smu[(cap + 1) * num + i]);
 408                 err_nbr++;
 409         }
 410
 411         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 412         if (sector_size == 1024)
 413                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 414
 415         pmecc_writel(host->pmerrloc, elcfg, val);
 416         pmecc_writel(host->pmerrloc, elen,
 417                      sector_size * 8 + host->pmecc_degree * cap);
 418
 419         while (--timeout) {
 420                 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
 421                         break;
 422                 WATCHDOG_RESET();
 423                 udelay(1);
 424         }
 425
 426         if (!timeout) {
 427                 dev_err(mtd->dev,
 428                         "Timeout to calculate PMECC error location\n");
 429                 return -1;
 430         }
 431
 432         roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
 433                         >> 8;
 434         /* Number of roots == degree of smu hence <= cap */
 435         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 436                 return err_nbr - 1;
 437
 438         /* Number of roots does not match the degree of smu
 439          * unable to correct error */
 440         return -1;
 441 }
 442
 443 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 444                 int sector_num, int extra_bytes, int err_nbr)
 445 {
 446         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 447         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 448         int i = 0;
 449         int byte_pos, bit_pos, sector_size, pos;
 450         uint32_t tmp;
 451         uint8_t err_byte;
 452
 453         sector_size = host->pmecc_sector_size;
 454
 455         while (err_nbr) {
 456                 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
 457                 byte_pos = tmp / 8;
 458                 bit_pos  = tmp % 8;
 459
 460                 if (byte_pos >= (sector_size + extra_bytes))
 461                         BUG();  /* should never happen */
 462
 463                 if (byte_pos < sector_size) {
 464                         err_byte = *(buf + byte_pos);
 465                         *(buf + byte_pos) ^= (1 << bit_pos);
 466
 467                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 468                         dev_dbg(mtd->dev,
 469                                 "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 470                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 471                 } else {
 472                         /* Bit flip in OOB area */
 473                         tmp = sector_num * host->pmecc_bytes_per_sector
 474                                         + (byte_pos - sector_size);
 475                         err_byte = ecc[tmp];
 476                         ecc[tmp] ^= (1 << bit_pos);
 477
 478                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 479                         dev_dbg(mtd->dev,
 480                                 "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 481                                 pos, bit_pos, err_byte, ecc[tmp]);
 482                 }
 483
 484                 i++;
 485                 err_nbr--;
 486         }
 487
 488         return;
 489 }
 490
 491 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 492         u8 *ecc)
 493 {
 494         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 495         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 496         int i, err_nbr;
 497         u8 *buf_pos, *ecc_pos;
 498
 499         for (i = 0; i < host->pmecc_sector_number; i++) {
 500                 err_nbr = 0;
 501                 if (pmecc_stat & 0x1) {
 502                         buf_pos = buf + i * host->pmecc_sector_size;
 503
 504                         pmecc_gen_syndrome(mtd, i);
 505                         pmecc_substitute(mtd);
 506                         pmecc_get_sigma(mtd);
 507
 508                         err_nbr = pmecc_err_location(mtd);
 509                         if (err_nbr >= 0) {
 510                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 511                                                    host->pmecc_bytes_per_sector,
 512                                                    err_nbr);
 513                         } else if (host->pmecc_version < PMECC_VERSION_SAMA5D4) {
 514                                 ecc_pos = ecc + i * host->pmecc_bytes_per_sector;
 515
 516                                 err_nbr = nand_check_erased_ecc_chunk(
 517                                         buf_pos, host->pmecc_sector_size,
 518                                         ecc_pos, host->pmecc_bytes_per_sector,
 519                                         NULL, 0, host->pmecc_corr_cap);
 520                         }
 521
 522                         if (err_nbr < 0) {
 523                                 dev_err(mtd->dev, "PMECC: Too many errors\n");
 524                                 mtd->ecc_stats.failed++;
 525                                 return -EBADMSG;
 526                         }
 527
 528                         mtd->ecc_stats.corrected += err_nbr;
 529                 }
 530                 pmecc_stat >>= 1;
 531         }
 532
 533         return 0;
 534 }
 535
 536 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 537         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 538 {
 539         struct atmel_nand_host *host = nand_get_controller_data(chip);
 540         int eccsize = chip->ecc.size;
 541         uint8_t *oob = chip->oob_poi;
 542         uint32_t *eccpos = chip->ecc.layout->eccpos;
 543         uint32_t stat;
 544         int timeout = PMECC_MAX_TIMEOUT_US;
 545
 546         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 547         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 548         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 549                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 550
 551         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 552         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 553
 554         chip->read_buf(mtd, buf, eccsize);
 555         chip->read_buf(mtd, oob, mtd->oobsize);
 556
 557         while (--timeout) {
 558                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 559                         break;
 560                 WATCHDOG_RESET();
 561                 udelay(1);
 562         }
 563
 564         if (!timeout) {
 565                 dev_err(mtd->dev, "Timeout to read PMECC page\n");
 566                 return -1;
 567         }
 568
 569         stat = pmecc_readl(host->pmecc, isr);
 570         if (stat != 0)
 571                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 572                         return -EBADMSG;
 573
 574         return 0;
 575 }
 576
 577 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 578                 struct nand_chip *chip, const uint8_t *buf,
 579                 int oob_required, int page)
 580 {
 581         struct atmel_nand_host *host = nand_get_controller_data(chip);
 582         uint32_t *eccpos = chip->ecc.layout->eccpos;
 583         int i, j;
 584         int timeout = PMECC_MAX_TIMEOUT_US;
 585
 586         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 587         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 588
 589         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 590                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 591
 592         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 593         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 594
 595         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 596
 597         while (--timeout) {
 598                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 599                         break;
 600                 WATCHDOG_RESET();
 601                 udelay(1);
 602         }
 603
 604         if (!timeout) {
 605                 dev_err(mtd->dev,
 606                         "Timeout to read PMECC status, fail to write PMECC in oob\n");
 607                 goto out;
 608         }
 609
 610         for (i = 0; i < host->pmecc_sector_number; i++) {
 611                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 612                         int pos;
 613
 614                         pos = i * host->pmecc_bytes_per_sector + j;
 615                         chip->oob_poi[eccpos[pos]] =
 616                                 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
 617                 }
 618         }
 619         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 620 out:
 621         return 0;
 622 }
 623
 624 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 625 {
 626         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 627         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 628         uint32_t val = 0;
 629         struct nand_ecclayout *ecc_layout;
 630
 631         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 632         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 633
 634         switch (host->pmecc_corr_cap) {
 635         case 2:
 636                 val = PMECC_CFG_BCH_ERR2;
 637                 break;
 638         case 4:
 639                 val = PMECC_CFG_BCH_ERR4;
 640                 break;
 641         case 8:
 642                 val = PMECC_CFG_BCH_ERR8;
 643                 break;
 644         case 12:
 645                 val = PMECC_CFG_BCH_ERR12;
 646                 break;
 647         case 24:
 648                 val = PMECC_CFG_BCH_ERR24;
 649                 break;
 650         case 32:
 651                 val = PMECC_CFG_BCH_ERR32;
 652                 break;
 653         }
 654
 655         if (host->pmecc_sector_size == 512)
 656                 val |= PMECC_CFG_SECTOR512;
 657         else if (host->pmecc_sector_size == 1024)
 658                 val |= PMECC_CFG_SECTOR1024;
 659
 660         switch (host->pmecc_sector_number) {
 661         case 1:
 662                 val |= PMECC_CFG_PAGE_1SECTOR;
 663                 break;
 664         case 2:
 665                 val |= PMECC_CFG_PAGE_2SECTORS;
 666                 break;
 667         case 4:
 668                 val |= PMECC_CFG_PAGE_4SECTORS;
 669                 break;
 670         case 8:
 671                 val |= PMECC_CFG_PAGE_8SECTORS;
 672                 break;
 673         }
 674
 675         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 676                 | PMECC_CFG_AUTO_DISABLE);
 677         pmecc_writel(host->pmecc, cfg, val);
 678
 679         ecc_layout = nand_chip->ecc.layout;
 680         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 681         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 682         pmecc_writel(host->pmecc, eaddr,
 683                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 684         /* See datasheet about PMECC Clock Control Register */
 685         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 686         pmecc_writel(host->pmecc, idr, 0xff);
 687         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 688 }
 689
 690 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 691 /*
 692  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
 693  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
 694  *                    ONFI ECC parameters.
 695  * @host: point to an atmel_nand_host structure.
 696  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
 697  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
 698  * @chip: point to an nand_chip structure.
 699  * @cap: store the ONFI ECC correct bits capbility
 700  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 701  *
 702  * Return 0 if success. otherwise return the error code.
 703  */
 704 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 705                 struct nand_chip *chip,
 706                 int *cap, int *sector_size)
 707 {
 708         /* Get ECC requirement from ONFI parameters */
 709         *cap = *sector_size = 0;
 710         if (chip->onfi_version) {
 711                 *cap = chip->ecc_strength_ds;
 712                 *sector_size = chip->ecc_step_ds;
 713                 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
 714                          *cap, *sector_size);
 715         }
 716
 717         if (*cap == 0 && *sector_size == 0) {
 718                 /* Non-ONFI compliant */
 719                 dev_info(chip->mtd.dev,
 720                          "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
 721                 *cap = 2;
 722                 *sector_size = 512;
 723         }
 724
 725         /* If head file doesn't specify then use the one in ONFI parameters */
 726         if (host->pmecc_corr_cap == 0) {
 727                 /* use the most fitable ecc bits (the near bigger one ) */
 728                 if (*cap <= 2)
 729                         host->pmecc_corr_cap = 2;
 730                 else if (*cap <= 4)
 731                         host->pmecc_corr_cap = 4;
 732                 else if (*cap <= 8)
 733                         host->pmecc_corr_cap = 8;
 734                 else if (*cap <= 12)
 735                         host->pmecc_corr_cap = 12;
 736                 else if (*cap <= 24)
 737                         host->pmecc_corr_cap = 24;
 738                 else
 739 #ifdef CONFIG_SAMA5D2
 740                         host->pmecc_corr_cap = 32;
 741 #else
 742                         host->pmecc_corr_cap = 24;
 743 #endif
 744         }
 745         if (host->pmecc_sector_size == 0) {
 746                 /* use the most fitable sector size (the near smaller one ) */
 747                 if (*sector_size >= 1024)
 748                         host->pmecc_sector_size = 1024;
 749                 else if (*sector_size >= 512)
 750                         host->pmecc_sector_size = 512;
 751                 else
 752                         return -EINVAL;
 753         }
 754         return 0;
 755 }
 756 #endif
 757
 758 #if defined(NO_GALOIS_TABLE_IN_ROM)
 759 static uint16_t *pmecc_galois_table;
 760 static inline int deg(unsigned int poly)
 761 {
 762         /* polynomial degree is the most-significant bit index */
 763         return fls(poly) - 1;
 764 }
 765
 766 static int build_gf_tables(int mm, unsigned int poly,
 767                            int16_t *index_of, int16_t *alpha_to)
 768 {
 769         unsigned int i, x = 1;
 770         const unsigned int k = 1 << deg(poly);
 771         unsigned int nn = (1 << mm) - 1;
 772
 773         /* primitive polynomial must be of degree m */
 774         if (k != (1u << mm))
 775                 return -EINVAL;
 776
 777         for (i = 0; i < nn; i++) {
 778                 alpha_to[i] = x;
 779                 index_of[x] = i;
 780                 if (i && (x == 1))
 781                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
 782                         return -EINVAL;
 783                 x <<= 1;
 784                 if (x & k)
 785                         x ^= poly;
 786         }
 787
 788         alpha_to[nn] = 1;
 789         index_of[0] = 0;
 790
 791         return 0;
 792 }
 793
 794 static uint16_t *create_lookup_table(int sector_size)
 795 {
 796         int degree = (sector_size == 512) ?
 797                         PMECC_GF_DIMENSION_13 :
 798                         PMECC_GF_DIMENSION_14;
 799         unsigned int poly = (sector_size == 512) ?
 800                         PMECC_GF_13_PRIMITIVE_POLY :
 801                         PMECC_GF_14_PRIMITIVE_POLY;
 802         int table_size = (sector_size == 512) ?
 803                         PMECC_INDEX_TABLE_SIZE_512 :
 804                         PMECC_INDEX_TABLE_SIZE_1024;
 805
 806         int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
 807         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
 808                 return NULL;
 809
 810         return (uint16_t *)addr;
 811 }
 812 #endif
 813
 814 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 815                 struct mtd_info *mtd)
 816 {
 817         struct atmel_nand_host *host;
 818         int cap, sector_size;
 819
 820         host = &pmecc_host;
 821         nand_set_controller_data(nand, host);
 822
 823         nand->ecc.mode = NAND_ECC_HW;
 824         nand->ecc.calculate = NULL;
 825         nand->ecc.correct = NULL;
 826         nand->ecc.hwctl = NULL;
 827
 828 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 829         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
 830
 831 #ifdef CONFIG_PMECC_CAP
 832         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 833 #endif
 834 #ifdef CONFIG_PMECC_SECTOR_SIZE
 835         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 836 #endif
 837         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
 838          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
 839          * from ONFI.
 840          */
 841         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
 842                 dev_err(mtd->dev,
 843                         "Required ECC %d bits in %d bytes not supported!\n",
 844                         cap, sector_size);
 845                 return -EINVAL;
 846         }
 847
 848         if (cap > host->pmecc_corr_cap)
 849                 dev_info(mtd->dev,
 850                          "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
 851                          host->pmecc_corr_cap, cap);
 852         if (sector_size < host->pmecc_sector_size)
 853                 dev_info(mtd->dev,
 854                          "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
 855                          host->pmecc_sector_size, sector_size);
 856 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
 857         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 858         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 859 #endif
 860
 861         cap = host->pmecc_corr_cap;
 862         sector_size = host->pmecc_sector_size;
 863
 864         /* TODO: need check whether cap & sector_size is validate */
 865 #if defined(NO_GALOIS_TABLE_IN_ROM)
 866         /*
 867          * As pmecc_rom_base is the begin of the gallois field table, So the
 868          * index offset just set as 0.
 869          */
 870         host->pmecc_index_table_offset = 0;
 871 #else
 872         if (host->pmecc_sector_size == 512)
 873                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 874         else
 875                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 876 #endif
 877
 878         pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
 879                  cap, sector_size);
 880
 881         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 882         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 883                         ATMEL_BASE_PMERRLOC;
 884 #if defined(NO_GALOIS_TABLE_IN_ROM)
 885         pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
 886         if (!pmecc_galois_table) {
 887                 dev_err(mtd->dev, "out of memory\n");
 888                 return -ENOMEM;
 889         }
 890
 891         host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
 892 #else
 893         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 894 #endif
 895
 896         /* ECC is calculated for the whole page (1 step) */
 897         nand->ecc.size = mtd->writesize;
 898
 899         /* set ECC page size and oob layout */
 900         switch (mtd->writesize) {
 901         case 2048:
 902         case 4096:
 903         case 8192:
 904                 host->pmecc_degree = (sector_size == 512) ?
 905                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 906                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 907                 host->pmecc_sector_number = mtd->writesize / sector_size;
 908                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 909                         cap, sector_size);
 910                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 911                 host->pmecc_index_of = host->pmecc_rom_base +
 912                         host->pmecc_index_table_offset;
 913
 914                 nand->ecc.steps = 1;
 915                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 916                                        host->pmecc_sector_number;
 917
 918                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
 919                         dev_err(mtd->dev,
 920                                 "too large eccpos entries. max support ecc.bytes is %d\n",
 921                                 MTD_MAX_ECCPOS_ENTRIES_LARGE);
 922                         return -EINVAL;
 923                 }
 924
 925                 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
 926                         dev_err(mtd->dev, "No room for ECC bytes\n");
 927                         return -EINVAL;
 928                 }
 929                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 930                                         mtd->oobsize,
 931                                         nand->ecc.bytes);
 932                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 933                 break;
 934         case 512:
 935         case 1024:
 936                 /* TODO */
 937                 dev_err(mtd->dev,
 938                         "Unsupported page size for PMECC, use Software ECC\n");
 939         default:
 940                 /* page size not handled by HW ECC */
 941                 /* switching back to soft ECC */
 942                 nand->ecc.mode = NAND_ECC_SOFT;
 943                 nand->ecc.read_page = NULL;
 944                 nand->ecc.postpad = 0;
 945                 nand->ecc.prepad = 0;
 946                 nand->ecc.bytes = 0;
 947                 return 0;
 948         }
 949
 950         /* Allocate data for PMECC computation */
 951         if (pmecc_data_alloc(host)) {
 952                 dev_err(mtd->dev,
 953                         "Cannot allocate memory for PMECC computation!\n");
 954                 return -ENOMEM;
 955         }
 956
 957         nand->options |= NAND_NO_SUBPAGE_WRITE;
 958         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 959         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 960         nand->ecc.strength = cap;
 961
 962         /* Check the PMECC ip version */
 963         host->pmecc_version = pmecc_readl(host->pmerrloc, version);
 964         dev_dbg(mtd->dev, "PMECC IP version is: %x\n", host->pmecc_version);
 965
 966         atmel_pmecc_core_init(mtd);
 967
 968         return 0;
 969 }
 970
 971 #else
 972
 973 /* oob layout for large page size
 974  * bad block info is on bytes 0 and 1
 975  * the bytes have to be consecutives to avoid
 976  * several NAND_CMD_RNDOUT during read
 977  */
 978 static struct nand_ecclayout atmel_oobinfo_large = {
 979         .eccbytes = 4,
 980         .eccpos = {60, 61, 62, 63},
 981         .oobfree = {
 982                 {2, 58}
 983         },
 984 };
 985
 986 /* oob layout for small page size
 987  * bad block info is on bytes 4 and 5
 988  * the bytes have to be consecutives to avoid
 989  * several NAND_CMD_RNDOUT during read
 990  */
 991 static struct nand_ecclayout atmel_oobinfo_small = {
 992         .eccbytes = 4,
 993         .eccpos = {0, 1, 2, 3},
 994         .oobfree = {
 995                 {6, 10}
 996         },
 997 };
 998
 999 /*
1000  * Calculate HW ECC
1001  *
1002  * function called after a write
1003  *
1004  * mtd:        MTD block structure
1005  * dat:        raw data (unused)
1006  * ecc_code:   buffer for ECC
1007  */
1008 static int atmel_nand_calculate(struct mtd_info *mtd,
1009                 const u_char *dat, unsigned char *ecc_code)
1010 {
1011         unsigned int ecc_value;
1012
1013         /* get the first 2 ECC bytes */
1014         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1015
1016         ecc_code[0] = ecc_value & 0xFF;
1017         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1018
1019         /* get the last 2 ECC bytes */
1020         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1021
1022         ecc_code[2] = ecc_value & 0xFF;
1023         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1024
1025         return 0;
1026 }
1027
1028 /*
1029  * HW ECC read page function
1030  *
1031  * mtd:        mtd info structure
1032  * chip:       nand chip info structure
1033  * buf:        buffer to store read data
1034  * oob_required:    caller expects OOB data read to chip->oob_poi
1035  */
1036 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1037                                 uint8_t *buf, int oob_required, int page)
1038 {
1039         int eccsize = chip->ecc.size;
1040         int eccbytes = chip->ecc.bytes;
1041         uint32_t *eccpos = chip->ecc.layout->eccpos;
1042         uint8_t *p = buf;
1043         uint8_t *oob = chip->oob_poi;
1044         uint8_t *ecc_pos;
1045         int stat;
1046
1047         /* read the page */
1048         chip->read_buf(mtd, p, eccsize);
1049
1050         /* move to ECC position if needed */
1051         if (eccpos[0] != 0) {
1052                 /* This only works on large pages
1053                  * because the ECC controller waits for
1054                  * NAND_CMD_RNDOUTSTART after the
1055                  * NAND_CMD_RNDOUT.
1056                  * anyway, for small pages, the eccpos[0] == 0
1057                  */
1058                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1059                                 mtd->writesize + eccpos[0], -1);
1060         }
1061
1062         /* the ECC controller needs to read the ECC just after the data */
1063         ecc_pos = oob + eccpos[0];
1064         chip->read_buf(mtd, ecc_pos, eccbytes);
1065
1066         /* check if there's an error */
1067         stat = chip->ecc.correct(mtd, p, oob, NULL);
1068
1069         if (stat < 0)
1070                 mtd->ecc_stats.failed++;
1071         else
1072                 mtd->ecc_stats.corrected += stat;
1073
1074         /* get back to oob start (end of page) */
1075         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1076
1077         /* read the oob */
1078         chip->read_buf(mtd, oob, mtd->oobsize);
1079
1080         return 0;
1081 }
1082
1083 /*
1084  * HW ECC Correction
1085  *
1086  * function called after a read
1087  *
1088  * mtd:        MTD block structure
1089  * dat:        raw data read from the chip
1090  * read_ecc:   ECC from the chip (unused)
1091  * isnull:     unused
1092  *
1093  * Detect and correct a 1 bit error for a page
1094  */
1095 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1096                 u_char *read_ecc, u_char *isnull)
1097 {
1098         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1099         unsigned int ecc_status;
1100         unsigned int ecc_word, ecc_bit;
1101
1102         /* get the status from the Status Register */
1103         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1104
1105         /* if there's no error */
1106         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1107                 return 0;
1108
1109         /* get error bit offset (4 bits) */
1110         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1111         /* get word address (12 bits) */
1112         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1113         ecc_word >>= 4;
1114
1115         /* if there are multiple errors */
1116         if (ecc_status & ATMEL_ECC_MULERR) {
1117                 /* check if it is a freshly erased block
1118                  * (filled with 0xff) */
1119                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1120                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1121                         /* the block has just been erased, return OK */
1122                         return 0;
1123                 }
1124                 /* it doesn't seems to be a freshly
1125                  * erased block.
1126                  * We can't correct so many errors */
1127                 dev_warn(mtd->dev,
1128                          "multiple errors detected. Unable to correct.\n");
1129                 return -EBADMSG;
1130         }
1131
1132         /* if there's a single bit error : we can correct it */
1133         if (ecc_status & ATMEL_ECC_ECCERR) {
1134                 /* there's nothing much to do here.
1135                  * the bit error is on the ECC itself.
1136                  */
1137                 dev_warn(mtd->dev,
1138                          "one bit error on ECC code. Nothing to correct\n");
1139                 return 0;
1140         }
1141
1142         dev_warn(mtd->dev,
1143                  "one bit error on data. (word offset in the page : 0x%x bit offset : 0x%x)\n",
1144                  ecc_word, ecc_bit);
1145         /* correct the error */
1146         if (nand_chip->options & NAND_BUSWIDTH_16) {
1147                 /* 16 bits words */
1148                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1149         } else {
1150                 /* 8 bits words */
1151                 dat[ecc_word] ^= (1 << ecc_bit);
1152         }
1153         dev_warn(mtd->dev, "error corrected\n");
1154         return 1;
1155 }
1156
1157 /*
1158  * Enable HW ECC : unused on most chips
1159  */
1160 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1161 {
1162 }
1163
1164 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1165 {
1166         nand->ecc.mode = NAND_ECC_HW;
1167         nand->ecc.calculate = atmel_nand_calculate;
1168         nand->ecc.correct = atmel_nand_correct;
1169         nand->ecc.hwctl = atmel_nand_hwctl;
1170         nand->ecc.read_page = atmel_nand_read_page;
1171         nand->ecc.bytes = 4;
1172         nand->ecc.strength = 4;
1173
1174         if (nand->ecc.mode == NAND_ECC_HW) {
1175                 /* ECC is calculated for the whole page (1 step) */
1176                 nand->ecc.size = mtd->writesize;
1177
1178                 /* set ECC page size and oob layout */
1179                 switch (mtd->writesize) {
1180                 case 512:
1181                         nand->ecc.layout = &atmel_oobinfo_small;
1182                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1183                                         ATMEL_ECC_PAGESIZE_528);
1184                         break;
1185                 case 1024:
1186                         nand->ecc.layout = &atmel_oobinfo_large;
1187                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1188                                         ATMEL_ECC_PAGESIZE_1056);
1189                         break;
1190                 case 2048:
1191                         nand->ecc.layout = &atmel_oobinfo_large;
1192                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1193                                         ATMEL_ECC_PAGESIZE_2112);
1194                         break;
1195                 case 4096:
1196                         nand->ecc.layout = &atmel_oobinfo_large;
1197                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1198                                         ATMEL_ECC_PAGESIZE_4224);
1199                         break;
1200                 default:
1201                         /* page size not handled by HW ECC */
1202                         /* switching back to soft ECC */
1203                         nand->ecc.mode = NAND_ECC_SOFT;
1204                         nand->ecc.calculate = NULL;
1205                         nand->ecc.correct = NULL;
1206                         nand->ecc.hwctl = NULL;
1207                         nand->ecc.read_page = NULL;
1208                         nand->ecc.postpad = 0;
1209                         nand->ecc.prepad = 0;
1210                         nand->ecc.bytes = 0;
1211                         break;
1212                 }
1213         }
1214
1215         return 0;
1216 }
1217
1218 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1219
1220 #endif /* CONFIG_ATMEL_NAND_HWECC */
1221
1222 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1223                                          int cmd, unsigned int ctrl)
1224 {
1225         struct nand_chip *this = mtd_to_nand(mtd);
1226
1227         if (ctrl & NAND_CTRL_CHANGE) {
1228                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1229                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1230                              | CONFIG_SYS_NAND_MASK_CLE);
1231
1232                 if (ctrl & NAND_CLE)
1233                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1234                 if (ctrl & NAND_ALE)
1235                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1236
1237 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1238                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1239                                     !(ctrl & NAND_NCE));
1240 #endif
1241                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1242         }
1243
1244         if (cmd != NAND_CMD_NONE)
1245                 writeb(cmd, this->IO_ADDR_W);
1246 }
1247
1248 #ifdef CONFIG_SYS_NAND_READY_PIN
1249 static int at91_nand_ready(struct mtd_info *mtd)
1250 {
1251         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1252 }
1253 #endif
1254
1255 #ifdef CONFIG_SPL_BUILD
1256 /* The following code is for SPL */
1257 static struct mtd_info *mtd;
1258 static struct nand_chip nand_chip;
1259
1260 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1261 {
1262         struct nand_chip *this = mtd_to_nand(mtd);
1263         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1264         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1265                         unsigned int ctrl) = this->cmd_ctrl;
1266
1267         while (!this->dev_ready(mtd))
1268                 ;
1269
1270         if (cmd == NAND_CMD_READOOB) {
1271                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1272                 cmd = NAND_CMD_READ0;
1273         }
1274
1275         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1276
1277         if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1278                 offs >>= 1;
1279
1280         hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1281         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1282         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1283         hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1284 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1285         hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1286 #endif
1287         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1288
1289         hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1290         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1291
1292         while (!this->dev_ready(mtd))
1293                 ;
1294
1295         return 0;
1296 }
1297
1298 static int nand_is_bad_block(int block)
1299 {
1300         struct nand_chip *this = mtd_to_nand(mtd);
1301
1302         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1303
1304         if (this->options & NAND_BUSWIDTH_16) {
1305                 if (readw(this->IO_ADDR_R) != 0xffff)
1306                         return 1;
1307         } else {
1308                 if (readb(this->IO_ADDR_R) != 0xff)
1309                         return 1;
1310         }
1311
1312         return 0;
1313 }
1314
1315 #ifdef CONFIG_SPL_NAND_ECC
1316 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1317 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1318                   CONFIG_SYS_NAND_ECCSIZE)
1319 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1320
1321 static int nand_read_page(int block, int page, void *dst)
1322 {
1323         struct nand_chip *this = mtd_to_nand(mtd);
1324         u_char ecc_calc[ECCTOTAL];
1325         u_char ecc_code[ECCTOTAL];
1326         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1327         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1328         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1329         int eccsteps = ECCSTEPS;
1330         int i;
1331         uint8_t *p = dst;
1332         nand_command(block, page, 0, NAND_CMD_READ0);
1333
1334         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1335                 if (this->ecc.mode != NAND_ECC_SOFT)
1336                         this->ecc.hwctl(mtd, NAND_ECC_READ);
1337                 this->read_buf(mtd, p, eccsize);
1338                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
1339         }
1340         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1341
1342         for (i = 0; i < ECCTOTAL; i++)
1343                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1344
1345         eccsteps = ECCSTEPS;
1346         p = dst;
1347
1348         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1349                 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1350
1351         return 0;
1352 }
1353
1354 int spl_nand_erase_one(int block, int page)
1355 {
1356         struct nand_chip *this = mtd_to_nand(mtd);
1357         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1358                         unsigned int ctrl) = this->cmd_ctrl;
1359         int page_addr;
1360
1361         if (nand_chip.select_chip)
1362                 nand_chip.select_chip(mtd, 0);
1363
1364         page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1365         hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1366         /* Row address */
1367         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1368         hwctrl(mtd, ((page_addr >> 8) & 0xff),
1369                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1370 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1371         /* One more address cycle for devices > 128MiB */
1372         hwctrl(mtd, (page_addr >> 16) & 0x0f,
1373                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1374 #endif
1375         hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1376
1377         while (!this->dev_ready(mtd))
1378                 ;
1379
1380         nand_deselect();
1381
1382         return 0;
1383 }
1384 #else
1385 static int nand_read_page(int block, int page, void *dst)
1386 {
1387         struct nand_chip *this = mtd_to_nand(mtd);
1388
1389         nand_command(block, page, 0, NAND_CMD_READ0);
1390         atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1391
1392         return 0;
1393 }
1394 #endif /* CONFIG_SPL_NAND_ECC */
1395
1396 int at91_nand_wait_ready(struct mtd_info *mtd)
1397 {
1398         struct nand_chip *this = mtd_to_nand(mtd);
1399
1400         udelay(this->chip_delay);
1401
1402         return 1;
1403 }
1404
1405 int board_nand_init(struct nand_chip *nand)
1406 {
1407         int ret = 0;
1408
1409         nand->ecc.mode = NAND_ECC_SOFT;
1410 #ifdef CONFIG_SYS_NAND_DBW_16
1411         nand->options = NAND_BUSWIDTH_16;
1412         nand->read_buf = nand_read_buf16;
1413 #else
1414         nand->read_buf = nand_read_buf;
1415 #endif
1416         nand->cmd_ctrl = at91_nand_hwcontrol;
1417 #ifdef CONFIG_SYS_NAND_READY_PIN
1418         nand->dev_ready = at91_nand_ready;
1419 #else
1420         nand->dev_ready = at91_nand_wait_ready;
1421 #endif
1422         nand->chip_delay = 20;
1423 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1424         nand->bbt_options |= NAND_BBT_USE_FLASH;
1425 #endif
1426
1427 #ifdef CONFIG_ATMEL_NAND_HWECC
1428 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1429         ret = atmel_pmecc_nand_init_params(nand, mtd);
1430 #endif
1431 #endif
1432
1433         return ret;
1434 }
1435
1436 void nand_init(void)
1437 {
1438         mtd = nand_to_mtd(&nand_chip);
1439         mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1440         mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1441         nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1442         nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1443         board_nand_init(&nand_chip);
1444
1445 #ifdef CONFIG_SPL_NAND_ECC
1446         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1447                 nand_chip.ecc.calculate = nand_calculate_ecc;
1448                 nand_chip.ecc.correct = nand_correct_data;
1449         }
1450 #endif
1451
1452         if (nand_chip.select_chip)
1453                 nand_chip.select_chip(mtd, 0);
1454 }
1455
1456 void nand_deselect(void)
1457 {
1458         if (nand_chip.select_chip)
1459                 nand_chip.select_chip(mtd, -1);
1460 }
1461
1462 #include "nand_spl_loaders.c"
1463
1464 #else
1465
1466 #ifndef CONFIG_SYS_NAND_BASE_LIST
1467 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1468 #endif
1469 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1470 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1471
1472 int atmel_nand_chip_init(int devnum, ulong base_addr)
1473 {
1474         int ret;
1475         struct nand_chip *nand = &nand_chip[devnum];
1476         struct mtd_info *mtd = nand_to_mtd(nand);
1477
1478         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1479
1480 #ifdef CONFIG_NAND_ECC_BCH
1481         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1482 #else
1483         nand->ecc.mode = NAND_ECC_SOFT;
1484 #endif
1485 #ifdef CONFIG_SYS_NAND_DBW_16
1486         nand->options = NAND_BUSWIDTH_16;
1487 #endif
1488         nand->cmd_ctrl = at91_nand_hwcontrol;
1489 #ifdef CONFIG_SYS_NAND_READY_PIN
1490         nand->dev_ready = at91_nand_ready;
1491 #endif
1492         nand->chip_delay = 75;
1493 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1494         nand->bbt_options |= NAND_BBT_USE_FLASH;
1495 #endif
1496
1497         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1498         if (ret)
1499                 return ret;
1500
1501 #ifdef CONFIG_ATMEL_NAND_HWECC
1502 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1503         ret = atmel_pmecc_nand_init_params(nand, mtd);
1504 #else
1505         ret = atmel_hwecc_nand_init_param(nand, mtd);
1506 #endif
1507         if (ret)
1508                 return ret;
1509 #endif
1510
1511         ret = nand_scan_tail(mtd);
1512         if (!ret)
1513                 nand_register(devnum, mtd);
1514
1515         return ret;
1516 }
1517
1518 void board_nand_init(void)
1519 {
1520         int i;
1521         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1522                 if (atmel_nand_chip_init(i, base_addr[i]))
1523                         log_err("atmel_nand: Fail to initialize #%d chip", i);
1524 }
1525 #endif /* CONFIG_SPL_BUILD */