drivers/mtd/nand/raw/atmel_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   8  *
   9  * Add Programmable Multibit ECC support for various AT91 SoC
  10  *     (C) Copyright 2012 ATMEL, Hong Xu
  11  */
  12
  13 #include <common.h>
  14 #include <log.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/gpio.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19 #include <linux/bitops.h>
  20 #include <linux/bug.h>
  21 #include <linux/delay.h>
  22
  23 #include <malloc.h>
  24 #include <nand.h>
  25 #include <watchdog.h>
  26 #include <linux/mtd/nand_ecc.h>
  27
  28 #ifdef CONFIG_ATMEL_NAND_HWECC
  29
  30 /* Register access macros */
  31 #define ecc_readl(add, reg)                             \
  32         readl(add + ATMEL_ECC_##reg)
  33 #define ecc_writel(add, reg, value)                     \
  34         writel((value), add + ATMEL_ECC_##reg)
  35
  36 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  37
  38 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  39
  40 #ifdef CONFIG_SPL_BUILD
  41 #undef CONFIG_SYS_NAND_ONFI_DETECTION
  42 #endif
  43
  44 struct atmel_nand_host {
  45         struct pmecc_regs __iomem *pmecc;
  46         struct pmecc_errloc_regs __iomem *pmerrloc;
  47         void __iomem            *pmecc_rom_base;
  48
  49         u8              pmecc_corr_cap;
  50         u16             pmecc_sector_size;
  51         u32             pmecc_index_table_offset;
  52         u32             pmecc_version;
  53
  54         int             pmecc_bytes_per_sector;
  55         int             pmecc_sector_number;
  56         int             pmecc_degree;   /* Degree of remainders */
  57         int             pmecc_cw_len;   /* Length of codeword */
  58
  59         /* lookup table for alpha_to and index_of */
  60         void __iomem    *pmecc_alpha_to;
  61         void __iomem    *pmecc_index_of;
  62
  63         /* data for pmecc computation */
  64         int16_t *pmecc_smu;
  65         int16_t *pmecc_partial_syn;
  66         int16_t *pmecc_si;
  67         int16_t *pmecc_lmu; /* polynomal order */
  68         int     *pmecc_mu;
  69         int     *pmecc_dmu;
  70         int     *pmecc_delta;
  71 };
  72
  73 static struct atmel_nand_host pmecc_host;
  74 static struct nand_ecclayout atmel_pmecc_oobinfo;
  75
  76 /*
  77  * Return number of ecc bytes per sector according to sector size and
  78  * correction capability
  79  *
  80  * Following table shows what at91 PMECC supported:
  81  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  82  * =====================        ================        =================
  83  *                2-bits                 4-bytes                  4-bytes
  84  *                4-bits                 7-bytes                  7-bytes
  85  *                8-bits                13-bytes                 14-bytes
  86  *               12-bits                20-bytes                 21-bytes
  87  *               24-bits                39-bytes                 42-bytes
  88  *               32-bits                52-bytes                 56-bytes
  89  */
  90 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  91 {
  92         int m = 12 + sector_size / 512;
  93         return (m * cap + 7) / 8;
  94 }
  95
  96 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  97         int oobsize, int ecc_len)
  98 {
  99         int i;
 100
 101         layout->eccbytes = ecc_len;
 102
 103         /* ECC will occupy the last ecc_len bytes continuously */
 104         for (i = 0; i < ecc_len; i++)
 105                 layout->eccpos[i] = oobsize - ecc_len + i;
 106
 107         layout->oobfree[0].offset = 2;
 108         layout->oobfree[0].length =
 109                 oobsize - ecc_len - layout->oobfree[0].offset;
 110 }
 111
 112 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 113 {
 114         int table_size;
 115
 116         table_size = host->pmecc_sector_size == 512 ?
 117                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 118
 119         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 120         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 121                         table_size * sizeof(int16_t);
 122 }
 123
 124 static void pmecc_data_free(struct atmel_nand_host *host)
 125 {
 126         free(host->pmecc_partial_syn);
 127         free(host->pmecc_si);
 128         free(host->pmecc_lmu);
 129         free(host->pmecc_smu);
 130         free(host->pmecc_mu);
 131         free(host->pmecc_dmu);
 132         free(host->pmecc_delta);
 133 }
 134
 135 static int pmecc_data_alloc(struct atmel_nand_host *host)
 136 {
 137         const int cap = host->pmecc_corr_cap;
 138         int size;
 139
 140         size = (2 * cap + 1) * sizeof(int16_t);
 141         host->pmecc_partial_syn = malloc(size);
 142         host->pmecc_si = malloc(size);
 143         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 144         host->pmecc_smu = malloc((cap + 2) * size);
 145
 146         size = (cap + 1) * sizeof(int);
 147         host->pmecc_mu = malloc(size);
 148         host->pmecc_dmu = malloc(size);
 149         host->pmecc_delta = malloc(size);
 150
 151         if (host->pmecc_partial_syn &&
 152                         host->pmecc_si &&
 153                         host->pmecc_lmu &&
 154                         host->pmecc_smu &&
 155                         host->pmecc_mu &&
 156                         host->pmecc_dmu &&
 157                         host->pmecc_delta)
 158                 return 0;
 159
 160         /* error happened */
 161         pmecc_data_free(host);
 162         return -ENOMEM;
 163
 164 }
 165
 166 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 167 {
 168         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 169         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 170         int i;
 171         uint32_t value;
 172
 173         /* Fill odd syndromes */
 174         for (i = 0; i < host->pmecc_corr_cap; i++) {
 175                 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
 176                 if (i & 1)
 177                         value >>= 16;
 178                 value &= 0xffff;
 179                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 180         }
 181 }
 182
 183 static void pmecc_substitute(struct mtd_info *mtd)
 184 {
 185         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 186         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 187         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 188         int16_t __iomem *index_of = host->pmecc_index_of;
 189         int16_t *partial_syn = host->pmecc_partial_syn;
 190         const int cap = host->pmecc_corr_cap;
 191         int16_t *si;
 192         int i, j;
 193
 194         /* si[] is a table that holds the current syndrome value,
 195          * an element of that table belongs to the field
 196          */
 197         si = host->pmecc_si;
 198
 199         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 200
 201         /* Computation 2t syndromes based on S(x) */
 202         /* Odd syndromes */
 203         for (i = 1; i < 2 * cap; i += 2) {
 204                 for (j = 0; j < host->pmecc_degree; j++) {
 205                         if (partial_syn[i] & (0x1 << j))
 206                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 207                 }
 208         }
 209         /* Even syndrome = (Odd syndrome) ** 2 */
 210         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 211                 if (si[j] == 0) {
 212                         si[i] = 0;
 213                 } else {
 214                         int16_t tmp;
 215
 216                         tmp = readw(index_of + si[j]);
 217                         tmp = (tmp * 2) % host->pmecc_cw_len;
 218                         si[i] = readw(alpha_to + tmp);
 219                 }
 220         }
 221 }
 222
 223 /*
 224  * This function defines a Berlekamp iterative procedure for
 225  * finding the value of the error location polynomial.
 226  * The input is si[], initialize by pmecc_substitute().
 227  * The output is smu[][].
 228  *
 229  * This function is written according to chip datasheet Chapter:
 230  * Find the Error Location Polynomial Sigma(x) of Section:
 231  * Programmable Multibit ECC Control (PMECC).
 232  */
 233 static void pmecc_get_sigma(struct mtd_info *mtd)
 234 {
 235         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 236         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 237
 238         int16_t *lmu = host->pmecc_lmu;
 239         int16_t *si = host->pmecc_si;
 240         int *mu = host->pmecc_mu;
 241         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 242         int *delta = host->pmecc_delta; /* Delta order */
 243         int cw_len = host->pmecc_cw_len;
 244         const int16_t cap = host->pmecc_corr_cap;
 245         const int num = 2 * cap + 1;
 246         int16_t __iomem *index_of = host->pmecc_index_of;
 247         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 248         int i, j, k;
 249         uint32_t dmu_0_count, tmp;
 250         int16_t *smu = host->pmecc_smu;
 251
 252         /* index of largest delta */
 253         int ro;
 254         int largest;
 255         int diff;
 256
 257         /* Init the Sigma(x) */
 258         memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
 259
 260         dmu_0_count = 0;
 261
 262         /* First Row */
 263
 264         /* Mu */
 265         mu[0] = -1;
 266
 267         smu[0] = 1;
 268
 269         /* discrepancy set to 1 */
 270         dmu[0] = 1;
 271         /* polynom order set to 0 */
 272         lmu[0] = 0;
 273         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 274         delta[0] = -1;
 275
 276         /* Second Row */
 277
 278         /* Mu */
 279         mu[1] = 0;
 280         /* Sigma(x) set to 1 */
 281         smu[num] = 1;
 282
 283         /* discrepancy set to S1 */
 284         dmu[1] = si[1];
 285
 286         /* polynom order set to 0 */
 287         lmu[1] = 0;
 288
 289         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 290         delta[1] = 0;
 291
 292         for (i = 1; i <= cap; i++) {
 293                 mu[i + 1] = i << 1;
 294                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 295                 /* check if discrepancy is set to 0 */
 296                 if (dmu[i] == 0) {
 297                         dmu_0_count++;
 298
 299                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 300                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 301                                 tmp += 2;
 302                         else
 303                                 tmp += 1;
 304
 305                         if (dmu_0_count == tmp) {
 306                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 307                                         smu[(cap + 1) * num + j] =
 308                                                         smu[i * num + j];
 309
 310                                 lmu[cap + 1] = lmu[i];
 311                                 return;
 312                         }
 313
 314                         /* copy polynom */
 315                         for (j = 0; j <= lmu[i] >> 1; j++)
 316                                 smu[(i + 1) * num + j] = smu[i * num + j];
 317
 318                         /* copy previous polynom order to the next */
 319                         lmu[i + 1] = lmu[i];
 320                 } else {
 321                         ro = 0;
 322                         largest = -1;
 323                         /* find largest delta with dmu != 0 */
 324                         for (j = 0; j < i; j++) {
 325                                 if ((dmu[j]) && (delta[j] > largest)) {
 326                                         largest = delta[j];
 327                                         ro = j;
 328                                 }
 329                         }
 330
 331                         /* compute difference */
 332                         diff = (mu[i] - mu[ro]);
 333
 334                         /* Compute degree of the new smu polynomial */
 335                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 336                                 lmu[i + 1] = lmu[i];
 337                         else
 338                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 339
 340                         /* Init smu[i+1] with 0 */
 341                         for (k = 0; k < num; k++)
 342                                 smu[(i + 1) * num + k] = 0;
 343
 344                         /* Compute smu[i+1] */
 345                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 346                                 int16_t a, b, c;
 347
 348                                 if (!(smu[ro * num + k] && dmu[i]))
 349                                         continue;
 350                                 a = readw(index_of + dmu[i]);
 351                                 b = readw(index_of + dmu[ro]);
 352                                 c = readw(index_of + smu[ro * num + k]);
 353                                 tmp = a + (cw_len - b) + c;
 354                                 a = readw(alpha_to + tmp % cw_len);
 355                                 smu[(i + 1) * num + (k + diff)] = a;
 356                         }
 357
 358                         for (k = 0; k <= lmu[i] >> 1; k++)
 359                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 360                 }
 361
 362                 /* End Computing Sigma (Mu+1) and L(mu) */
 363                 /* In either case compute delta */
 364                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 365
 366                 /* Do not compute discrepancy for the last iteration */
 367                 if (i >= cap)
 368                         continue;
 369
 370                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 371                         tmp = 2 * (i - 1);
 372                         if (k == 0) {
 373                                 dmu[i + 1] = si[tmp + 3];
 374                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 375                                 int16_t a, b, c;
 376                                 a = readw(index_of +
 377                                                 smu[(i + 1) * num + k]);
 378                                 b = si[2 * (i - 1) + 3 - k];
 379                                 c = readw(index_of + b);
 380                                 tmp = a + c;
 381                                 tmp %= cw_len;
 382                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 383                                         dmu[i + 1];
 384                         }
 385                 }
 386         }
 387 }
 388
 389 static int pmecc_err_location(struct mtd_info *mtd)
 390 {
 391         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 392         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 393         const int cap = host->pmecc_corr_cap;
 394         const int num = 2 * cap + 1;
 395         int sector_size = host->pmecc_sector_size;
 396         int err_nbr = 0;        /* number of error */
 397         int roots_nbr;          /* number of roots */
 398         int i;
 399         uint32_t val;
 400         int16_t *smu = host->pmecc_smu;
 401         int timeout = PMECC_MAX_TIMEOUT_US;
 402
 403         pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
 404
 405         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 406                 pmecc_writel(host->pmerrloc, sigma[i],
 407                              smu[(cap + 1) * num + i]);
 408                 err_nbr++;
 409         }
 410
 411         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 412         if (sector_size == 1024)
 413                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 414
 415         pmecc_writel(host->pmerrloc, elcfg, val);
 416         pmecc_writel(host->pmerrloc, elen,
 417                      sector_size * 8 + host->pmecc_degree * cap);
 418
 419         while (--timeout) {
 420                 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
 421                         break;
 422                 WATCHDOG_RESET();
 423                 udelay(1);
 424         }
 425
 426         if (!timeout) {
 427                 dev_err(mtd->dev,
 428                         "Timeout to calculate PMECC error location\n");
 429                 return -1;
 430         }
 431
 432         roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
 433                         >> 8;
 434         /* Number of roots == degree of smu hence <= cap */
 435         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 436                 return err_nbr - 1;
 437
 438         /* Number of roots does not match the degree of smu
 439          * unable to correct error */
 440         return -1;
 441 }
 442
 443 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 444                 int sector_num, int extra_bytes, int err_nbr)
 445 {
 446         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 447         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 448         int i = 0;
 449         int byte_pos, bit_pos, sector_size, pos;
 450         uint32_t tmp;
 451         uint8_t err_byte;
 452
 453         sector_size = host->pmecc_sector_size;
 454
 455         while (err_nbr) {
 456                 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
 457                 byte_pos = tmp / 8;
 458                 bit_pos  = tmp % 8;
 459
 460                 if (byte_pos >= (sector_size + extra_bytes))
 461                         BUG();  /* should never happen */
 462
 463                 if (byte_pos < sector_size) {
 464                         err_byte = *(buf + byte_pos);
 465                         *(buf + byte_pos) ^= (1 << bit_pos);
 466
 467                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 468                         dev_dbg(mtd->dev,
 469                                 "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 470                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 471                 } else {
 472                         /* Bit flip in OOB area */
 473                         tmp = sector_num * host->pmecc_bytes_per_sector
 474                                         + (byte_pos - sector_size);
 475                         err_byte = ecc[tmp];
 476                         ecc[tmp] ^= (1 << bit_pos);
 477
 478                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 479                         dev_dbg(mtd->dev,
 480                                 "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 481                                 pos, bit_pos, err_byte, ecc[tmp]);
 482                 }
 483
 484                 i++;
 485                 err_nbr--;
 486         }
 487
 488         return;
 489 }
 490
 491 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 492         u8 *ecc)
 493 {
 494         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 495         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 496         int i, err_nbr, eccbytes;
 497         uint8_t *buf_pos;
 498
 499         /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
 500         if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
 501                 goto normal_check;
 502
 503         eccbytes = nand_chip->ecc.bytes;
 504         for (i = 0; i < eccbytes; i++)
 505                 if (ecc[i] != 0xff)
 506                         goto normal_check;
 507         /* Erased page, return OK */
 508         return 0;
 509
 510 normal_check:
 511         for (i = 0; i < host->pmecc_sector_number; i++) {
 512                 err_nbr = 0;
 513                 if (pmecc_stat & 0x1) {
 514                         buf_pos = buf + i * host->pmecc_sector_size;
 515
 516                         pmecc_gen_syndrome(mtd, i);
 517                         pmecc_substitute(mtd);
 518                         pmecc_get_sigma(mtd);
 519
 520                         err_nbr = pmecc_err_location(mtd);
 521                         if (err_nbr == -1) {
 522                                 dev_err(mtd->dev, "PMECC: Too many errors\n");
 523                                 mtd->ecc_stats.failed++;
 524                                 return -EBADMSG;
 525                         } else {
 526                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 527                                         host->pmecc_bytes_per_sector, err_nbr);
 528                                 mtd->ecc_stats.corrected += err_nbr;
 529                         }
 530                 }
 531                 pmecc_stat >>= 1;
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 538         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 539 {
 540         struct atmel_nand_host *host = nand_get_controller_data(chip);
 541         int eccsize = chip->ecc.size;
 542         uint8_t *oob = chip->oob_poi;
 543         uint32_t *eccpos = chip->ecc.layout->eccpos;
 544         uint32_t stat;
 545         int timeout = PMECC_MAX_TIMEOUT_US;
 546
 547         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 548         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 549         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 550                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 551
 552         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 553         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 554
 555         chip->read_buf(mtd, buf, eccsize);
 556         chip->read_buf(mtd, oob, mtd->oobsize);
 557
 558         while (--timeout) {
 559                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 560                         break;
 561                 WATCHDOG_RESET();
 562                 udelay(1);
 563         }
 564
 565         if (!timeout) {
 566                 dev_err(mtd->dev, "Timeout to read PMECC page\n");
 567                 return -1;
 568         }
 569
 570         stat = pmecc_readl(host->pmecc, isr);
 571         if (stat != 0)
 572                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 573                         return -EBADMSG;
 574
 575         return 0;
 576 }
 577
 578 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 579                 struct nand_chip *chip, const uint8_t *buf,
 580                 int oob_required, int page)
 581 {
 582         struct atmel_nand_host *host = nand_get_controller_data(chip);
 583         uint32_t *eccpos = chip->ecc.layout->eccpos;
 584         int i, j;
 585         int timeout = PMECC_MAX_TIMEOUT_US;
 586
 587         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 588         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 589
 590         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 591                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 592
 593         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 594         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 595
 596         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 597
 598         while (--timeout) {
 599                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 600                         break;
 601                 WATCHDOG_RESET();
 602                 udelay(1);
 603         }
 604
 605         if (!timeout) {
 606                 dev_err(mtd->dev,
 607                         "Timeout to read PMECC status, fail to write PMECC in oob\n");
 608                 goto out;
 609         }
 610
 611         for (i = 0; i < host->pmecc_sector_number; i++) {
 612                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 613                         int pos;
 614
 615                         pos = i * host->pmecc_bytes_per_sector + j;
 616                         chip->oob_poi[eccpos[pos]] =
 617                                 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
 618                 }
 619         }
 620         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 621 out:
 622         return 0;
 623 }
 624
 625 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 626 {
 627         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 628         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 629         uint32_t val = 0;
 630         struct nand_ecclayout *ecc_layout;
 631
 632         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 633         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 634
 635         switch (host->pmecc_corr_cap) {
 636         case 2:
 637                 val = PMECC_CFG_BCH_ERR2;
 638                 break;
 639         case 4:
 640                 val = PMECC_CFG_BCH_ERR4;
 641                 break;
 642         case 8:
 643                 val = PMECC_CFG_BCH_ERR8;
 644                 break;
 645         case 12:
 646                 val = PMECC_CFG_BCH_ERR12;
 647                 break;
 648         case 24:
 649                 val = PMECC_CFG_BCH_ERR24;
 650                 break;
 651         case 32:
 652                 val = PMECC_CFG_BCH_ERR32;
 653                 break;
 654         }
 655
 656         if (host->pmecc_sector_size == 512)
 657                 val |= PMECC_CFG_SECTOR512;
 658         else if (host->pmecc_sector_size == 1024)
 659                 val |= PMECC_CFG_SECTOR1024;
 660
 661         switch (host->pmecc_sector_number) {
 662         case 1:
 663                 val |= PMECC_CFG_PAGE_1SECTOR;
 664                 break;
 665         case 2:
 666                 val |= PMECC_CFG_PAGE_2SECTORS;
 667                 break;
 668         case 4:
 669                 val |= PMECC_CFG_PAGE_4SECTORS;
 670                 break;
 671         case 8:
 672                 val |= PMECC_CFG_PAGE_8SECTORS;
 673                 break;
 674         }
 675
 676         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 677                 | PMECC_CFG_AUTO_DISABLE);
 678         pmecc_writel(host->pmecc, cfg, val);
 679
 680         ecc_layout = nand_chip->ecc.layout;
 681         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 682         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 683         pmecc_writel(host->pmecc, eaddr,
 684                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 685         /* See datasheet about PMECC Clock Control Register */
 686         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 687         pmecc_writel(host->pmecc, idr, 0xff);
 688         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 689 }
 690
 691 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 692 /*
 693  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
 694  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
 695  *                    ONFI ECC parameters.
 696  * @host: point to an atmel_nand_host structure.
 697  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
 698  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
 699  * @chip: point to an nand_chip structure.
 700  * @cap: store the ONFI ECC correct bits capbility
 701  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 702  *
 703  * Return 0 if success. otherwise return the error code.
 704  */
 705 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 706                 struct nand_chip *chip,
 707                 int *cap, int *sector_size)
 708 {
 709         /* Get ECC requirement from ONFI parameters */
 710         *cap = *sector_size = 0;
 711         if (chip->onfi_version) {
 712                 *cap = chip->ecc_strength_ds;
 713                 *sector_size = chip->ecc_step_ds;
 714                 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
 715                          *cap, *sector_size);
 716         }
 717
 718         if (*cap == 0 && *sector_size == 0) {
 719                 /* Non-ONFI compliant */
 720                 dev_info(chip->mtd.dev,
 721                          "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
 722                 *cap = 2;
 723                 *sector_size = 512;
 724         }
 725
 726         /* If head file doesn't specify then use the one in ONFI parameters */
 727         if (host->pmecc_corr_cap == 0) {
 728                 /* use the most fitable ecc bits (the near bigger one ) */
 729                 if (*cap <= 2)
 730                         host->pmecc_corr_cap = 2;
 731                 else if (*cap <= 4)
 732                         host->pmecc_corr_cap = 4;
 733                 else if (*cap <= 8)
 734                         host->pmecc_corr_cap = 8;
 735                 else if (*cap <= 12)
 736                         host->pmecc_corr_cap = 12;
 737                 else if (*cap <= 24)
 738                         host->pmecc_corr_cap = 24;
 739                 else
 740 #ifdef CONFIG_SAMA5D2
 741                         host->pmecc_corr_cap = 32;
 742 #else
 743                         host->pmecc_corr_cap = 24;
 744 #endif
 745         }
 746         if (host->pmecc_sector_size == 0) {
 747                 /* use the most fitable sector size (the near smaller one ) */
 748                 if (*sector_size >= 1024)
 749                         host->pmecc_sector_size = 1024;
 750                 else if (*sector_size >= 512)
 751                         host->pmecc_sector_size = 512;
 752                 else
 753                         return -EINVAL;
 754         }
 755         return 0;
 756 }
 757 #endif
 758
 759 #if defined(NO_GALOIS_TABLE_IN_ROM)
 760 static uint16_t *pmecc_galois_table;
 761 static inline int deg(unsigned int poly)
 762 {
 763         /* polynomial degree is the most-significant bit index */
 764         return fls(poly) - 1;
 765 }
 766
 767 static int build_gf_tables(int mm, unsigned int poly,
 768                            int16_t *index_of, int16_t *alpha_to)
 769 {
 770         unsigned int i, x = 1;
 771         const unsigned int k = 1 << deg(poly);
 772         unsigned int nn = (1 << mm) - 1;
 773
 774         /* primitive polynomial must be of degree m */
 775         if (k != (1u << mm))
 776                 return -EINVAL;
 777
 778         for (i = 0; i < nn; i++) {
 779                 alpha_to[i] = x;
 780                 index_of[x] = i;
 781                 if (i && (x == 1))
 782                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
 783                         return -EINVAL;
 784                 x <<= 1;
 785                 if (x & k)
 786                         x ^= poly;
 787         }
 788
 789         alpha_to[nn] = 1;
 790         index_of[0] = 0;
 791
 792         return 0;
 793 }
 794
 795 static uint16_t *create_lookup_table(int sector_size)
 796 {
 797         int degree = (sector_size == 512) ?
 798                         PMECC_GF_DIMENSION_13 :
 799                         PMECC_GF_DIMENSION_14;
 800         unsigned int poly = (sector_size == 512) ?
 801                         PMECC_GF_13_PRIMITIVE_POLY :
 802                         PMECC_GF_14_PRIMITIVE_POLY;
 803         int table_size = (sector_size == 512) ?
 804                         PMECC_INDEX_TABLE_SIZE_512 :
 805                         PMECC_INDEX_TABLE_SIZE_1024;
 806
 807         int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
 808         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
 809                 return NULL;
 810
 811         return (uint16_t *)addr;
 812 }
 813 #endif
 814
 815 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 816                 struct mtd_info *mtd)
 817 {
 818         struct atmel_nand_host *host;
 819         int cap, sector_size;
 820
 821         host = &pmecc_host;
 822         nand_set_controller_data(nand, host);
 823
 824         nand->ecc.mode = NAND_ECC_HW;
 825         nand->ecc.calculate = NULL;
 826         nand->ecc.correct = NULL;
 827         nand->ecc.hwctl = NULL;
 828
 829 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 830         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
 831
 832 #ifdef CONFIG_PMECC_CAP
 833         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 834 #endif
 835 #ifdef CONFIG_PMECC_SECTOR_SIZE
 836         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 837 #endif
 838         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
 839          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
 840          * from ONFI.
 841          */
 842         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
 843                 dev_err(mtd->dev,
 844                         "Required ECC %d bits in %d bytes not supported!\n",
 845                         cap, sector_size);
 846                 return -EINVAL;
 847         }
 848
 849         if (cap > host->pmecc_corr_cap)
 850                 dev_info(mtd->dev,
 851                          "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
 852                          host->pmecc_corr_cap, cap);
 853         if (sector_size < host->pmecc_sector_size)
 854                 dev_info(mtd->dev,
 855                          "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
 856                          host->pmecc_sector_size, sector_size);
 857 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
 858         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 859         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 860 #endif
 861
 862         cap = host->pmecc_corr_cap;
 863         sector_size = host->pmecc_sector_size;
 864
 865         /* TODO: need check whether cap & sector_size is validate */
 866 #if defined(NO_GALOIS_TABLE_IN_ROM)
 867         /*
 868          * As pmecc_rom_base is the begin of the gallois field table, So the
 869          * index offset just set as 0.
 870          */
 871         host->pmecc_index_table_offset = 0;
 872 #else
 873         if (host->pmecc_sector_size == 512)
 874                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 875         else
 876                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 877 #endif
 878
 879         pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
 880                  cap, sector_size);
 881
 882         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 883         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 884                         ATMEL_BASE_PMERRLOC;
 885 #if defined(NO_GALOIS_TABLE_IN_ROM)
 886         pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
 887         if (!pmecc_galois_table) {
 888                 dev_err(mtd->dev, "out of memory\n");
 889                 return -ENOMEM;
 890         }
 891
 892         host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
 893 #else
 894         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 895 #endif
 896
 897         /* ECC is calculated for the whole page (1 step) */
 898         nand->ecc.size = mtd->writesize;
 899
 900         /* set ECC page size and oob layout */
 901         switch (mtd->writesize) {
 902         case 2048:
 903         case 4096:
 904         case 8192:
 905                 host->pmecc_degree = (sector_size == 512) ?
 906                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 907                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 908                 host->pmecc_sector_number = mtd->writesize / sector_size;
 909                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 910                         cap, sector_size);
 911                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 912                 host->pmecc_index_of = host->pmecc_rom_base +
 913                         host->pmecc_index_table_offset;
 914
 915                 nand->ecc.steps = 1;
 916                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 917                                        host->pmecc_sector_number;
 918
 919                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
 920                         dev_err(mtd->dev,
 921                                 "too large eccpos entries. max support ecc.bytes is %d\n",
 922                                 MTD_MAX_ECCPOS_ENTRIES_LARGE);
 923                         return -EINVAL;
 924                 }
 925
 926                 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
 927                         dev_err(mtd->dev, "No room for ECC bytes\n");
 928                         return -EINVAL;
 929                 }
 930                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 931                                         mtd->oobsize,
 932                                         nand->ecc.bytes);
 933                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 934                 break;
 935         case 512:
 936         case 1024:
 937                 /* TODO */
 938                 dev_err(mtd->dev,
 939                         "Unsupported page size for PMECC, use Software ECC\n");
 940         default:
 941                 /* page size not handled by HW ECC */
 942                 /* switching back to soft ECC */
 943                 nand->ecc.mode = NAND_ECC_SOFT;
 944                 nand->ecc.read_page = NULL;
 945                 nand->ecc.postpad = 0;
 946                 nand->ecc.prepad = 0;
 947                 nand->ecc.bytes = 0;
 948                 return 0;
 949         }
 950
 951         /* Allocate data for PMECC computation */
 952         if (pmecc_data_alloc(host)) {
 953                 dev_err(mtd->dev,
 954                         "Cannot allocate memory for PMECC computation!\n");
 955                 return -ENOMEM;
 956         }
 957
 958         nand->options |= NAND_NO_SUBPAGE_WRITE;
 959         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 960         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 961         nand->ecc.strength = cap;
 962
 963         /* Check the PMECC ip version */
 964         host->pmecc_version = pmecc_readl(host->pmerrloc, version);
 965         dev_dbg(mtd->dev, "PMECC IP version is: %x\n", host->pmecc_version);
 966
 967         atmel_pmecc_core_init(mtd);
 968
 969         return 0;
 970 }
 971
 972 #else
 973
 974 /* oob layout for large page size
 975  * bad block info is on bytes 0 and 1
 976  * the bytes have to be consecutives to avoid
 977  * several NAND_CMD_RNDOUT during read
 978  */
 979 static struct nand_ecclayout atmel_oobinfo_large = {
 980         .eccbytes = 4,
 981         .eccpos = {60, 61, 62, 63},
 982         .oobfree = {
 983                 {2, 58}
 984         },
 985 };
 986
 987 /* oob layout for small page size
 988  * bad block info is on bytes 4 and 5
 989  * the bytes have to be consecutives to avoid
 990  * several NAND_CMD_RNDOUT during read
 991  */
 992 static struct nand_ecclayout atmel_oobinfo_small = {
 993         .eccbytes = 4,
 994         .eccpos = {0, 1, 2, 3},
 995         .oobfree = {
 996                 {6, 10}
 997         },
 998 };
 999
1000 /*
1001  * Calculate HW ECC
1002  *
1003  * function called after a write
1004  *
1005  * mtd:        MTD block structure
1006  * dat:        raw data (unused)
1007  * ecc_code:   buffer for ECC
1008  */
1009 static int atmel_nand_calculate(struct mtd_info *mtd,
1010                 const u_char *dat, unsigned char *ecc_code)
1011 {
1012         unsigned int ecc_value;
1013
1014         /* get the first 2 ECC bytes */
1015         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1016
1017         ecc_code[0] = ecc_value & 0xFF;
1018         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1019
1020         /* get the last 2 ECC bytes */
1021         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1022
1023         ecc_code[2] = ecc_value & 0xFF;
1024         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1025
1026         return 0;
1027 }
1028
1029 /*
1030  * HW ECC read page function
1031  *
1032  * mtd:        mtd info structure
1033  * chip:       nand chip info structure
1034  * buf:        buffer to store read data
1035  * oob_required:    caller expects OOB data read to chip->oob_poi
1036  */
1037 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1038                                 uint8_t *buf, int oob_required, int page)
1039 {
1040         int eccsize = chip->ecc.size;
1041         int eccbytes = chip->ecc.bytes;
1042         uint32_t *eccpos = chip->ecc.layout->eccpos;
1043         uint8_t *p = buf;
1044         uint8_t *oob = chip->oob_poi;
1045         uint8_t *ecc_pos;
1046         int stat;
1047
1048         /* read the page */
1049         chip->read_buf(mtd, p, eccsize);
1050
1051         /* move to ECC position if needed */
1052         if (eccpos[0] != 0) {
1053                 /* This only works on large pages
1054                  * because the ECC controller waits for
1055                  * NAND_CMD_RNDOUTSTART after the
1056                  * NAND_CMD_RNDOUT.
1057                  * anyway, for small pages, the eccpos[0] == 0
1058                  */
1059                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1060                                 mtd->writesize + eccpos[0], -1);
1061         }
1062
1063         /* the ECC controller needs to read the ECC just after the data */
1064         ecc_pos = oob + eccpos[0];
1065         chip->read_buf(mtd, ecc_pos, eccbytes);
1066
1067         /* check if there's an error */
1068         stat = chip->ecc.correct(mtd, p, oob, NULL);
1069
1070         if (stat < 0)
1071                 mtd->ecc_stats.failed++;
1072         else
1073                 mtd->ecc_stats.corrected += stat;
1074
1075         /* get back to oob start (end of page) */
1076         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1077
1078         /* read the oob */
1079         chip->read_buf(mtd, oob, mtd->oobsize);
1080
1081         return 0;
1082 }
1083
1084 /*
1085  * HW ECC Correction
1086  *
1087  * function called after a read
1088  *
1089  * mtd:        MTD block structure
1090  * dat:        raw data read from the chip
1091  * read_ecc:   ECC from the chip (unused)
1092  * isnull:     unused
1093  *
1094  * Detect and correct a 1 bit error for a page
1095  */
1096 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1097                 u_char *read_ecc, u_char *isnull)
1098 {
1099         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1100         unsigned int ecc_status;
1101         unsigned int ecc_word, ecc_bit;
1102
1103         /* get the status from the Status Register */
1104         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1105
1106         /* if there's no error */
1107         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1108                 return 0;
1109
1110         /* get error bit offset (4 bits) */
1111         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1112         /* get word address (12 bits) */
1113         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1114         ecc_word >>= 4;
1115
1116         /* if there are multiple errors */
1117         if (ecc_status & ATMEL_ECC_MULERR) {
1118                 /* check if it is a freshly erased block
1119                  * (filled with 0xff) */
1120                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1121                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1122                         /* the block has just been erased, return OK */
1123                         return 0;
1124                 }
1125                 /* it doesn't seems to be a freshly
1126                  * erased block.
1127                  * We can't correct so many errors */
1128                 dev_warn(mtd->dev,
1129                          "multiple errors detected. Unable to correct.\n");
1130                 return -EBADMSG;
1131         }
1132
1133         /* if there's a single bit error : we can correct it */
1134         if (ecc_status & ATMEL_ECC_ECCERR) {
1135                 /* there's nothing much to do here.
1136                  * the bit error is on the ECC itself.
1137                  */
1138                 dev_warn(mtd->dev,
1139                          "one bit error on ECC code. Nothing to correct\n");
1140                 return 0;
1141         }
1142
1143         dev_warn(mtd->dev,
1144                  "one bit error on data. (word offset in the page : 0x%x bit offset : 0x%x)\n",
1145                  ecc_word, ecc_bit);
1146         /* correct the error */
1147         if (nand_chip->options & NAND_BUSWIDTH_16) {
1148                 /* 16 bits words */
1149                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1150         } else {
1151                 /* 8 bits words */
1152                 dat[ecc_word] ^= (1 << ecc_bit);
1153         }
1154         dev_warn(mtd->dev, "error corrected\n");
1155         return 1;
1156 }
1157
1158 /*
1159  * Enable HW ECC : unused on most chips
1160  */
1161 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1162 {
1163 }
1164
1165 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1166 {
1167         nand->ecc.mode = NAND_ECC_HW;
1168         nand->ecc.calculate = atmel_nand_calculate;
1169         nand->ecc.correct = atmel_nand_correct;
1170         nand->ecc.hwctl = atmel_nand_hwctl;
1171         nand->ecc.read_page = atmel_nand_read_page;
1172         nand->ecc.bytes = 4;
1173         nand->ecc.strength = 4;
1174
1175         if (nand->ecc.mode == NAND_ECC_HW) {
1176                 /* ECC is calculated for the whole page (1 step) */
1177                 nand->ecc.size = mtd->writesize;
1178
1179                 /* set ECC page size and oob layout */
1180                 switch (mtd->writesize) {
1181                 case 512:
1182                         nand->ecc.layout = &atmel_oobinfo_small;
1183                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1184                                         ATMEL_ECC_PAGESIZE_528);
1185                         break;
1186                 case 1024:
1187                         nand->ecc.layout = &atmel_oobinfo_large;
1188                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1189                                         ATMEL_ECC_PAGESIZE_1056);
1190                         break;
1191                 case 2048:
1192                         nand->ecc.layout = &atmel_oobinfo_large;
1193                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1194                                         ATMEL_ECC_PAGESIZE_2112);
1195                         break;
1196                 case 4096:
1197                         nand->ecc.layout = &atmel_oobinfo_large;
1198                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1199                                         ATMEL_ECC_PAGESIZE_4224);
1200                         break;
1201                 default:
1202                         /* page size not handled by HW ECC */
1203                         /* switching back to soft ECC */
1204                         nand->ecc.mode = NAND_ECC_SOFT;
1205                         nand->ecc.calculate = NULL;
1206                         nand->ecc.correct = NULL;
1207                         nand->ecc.hwctl = NULL;
1208                         nand->ecc.read_page = NULL;
1209                         nand->ecc.postpad = 0;
1210                         nand->ecc.prepad = 0;
1211                         nand->ecc.bytes = 0;
1212                         break;
1213                 }
1214         }
1215
1216         return 0;
1217 }
1218
1219 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1220
1221 #endif /* CONFIG_ATMEL_NAND_HWECC */
1222
1223 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1224                                          int cmd, unsigned int ctrl)
1225 {
1226         struct nand_chip *this = mtd_to_nand(mtd);
1227
1228         if (ctrl & NAND_CTRL_CHANGE) {
1229                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1230                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1231                              | CONFIG_SYS_NAND_MASK_CLE);
1232
1233                 if (ctrl & NAND_CLE)
1234                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1235                 if (ctrl & NAND_ALE)
1236                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1237
1238 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1239                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1240                                     !(ctrl & NAND_NCE));
1241 #endif
1242                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1243         }
1244
1245         if (cmd != NAND_CMD_NONE)
1246                 writeb(cmd, this->IO_ADDR_W);
1247 }
1248
1249 #ifdef CONFIG_SYS_NAND_READY_PIN
1250 static int at91_nand_ready(struct mtd_info *mtd)
1251 {
1252         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1253 }
1254 #endif
1255
1256 #ifdef CONFIG_SPL_BUILD
1257 /* The following code is for SPL */
1258 static struct mtd_info *mtd;
1259 static struct nand_chip nand_chip;
1260
1261 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1262 {
1263         struct nand_chip *this = mtd_to_nand(mtd);
1264         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1265         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1266                         unsigned int ctrl) = this->cmd_ctrl;
1267
1268         while (!this->dev_ready(mtd))
1269                 ;
1270
1271         if (cmd == NAND_CMD_READOOB) {
1272                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1273                 cmd = NAND_CMD_READ0;
1274         }
1275
1276         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1277
1278         if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1279                 offs >>= 1;
1280
1281         hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1282         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1283         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1284         hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1285 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1286         hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1287 #endif
1288         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1289
1290         hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1291         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1292
1293         while (!this->dev_ready(mtd))
1294                 ;
1295
1296         return 0;
1297 }
1298
1299 static int nand_is_bad_block(int block)
1300 {
1301         struct nand_chip *this = mtd_to_nand(mtd);
1302
1303         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1304
1305         if (this->options & NAND_BUSWIDTH_16) {
1306                 if (readw(this->IO_ADDR_R) != 0xffff)
1307                         return 1;
1308         } else {
1309                 if (readb(this->IO_ADDR_R) != 0xff)
1310                         return 1;
1311         }
1312
1313         return 0;
1314 }
1315
1316 #ifdef CONFIG_SPL_NAND_ECC
1317 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1318 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1319                   CONFIG_SYS_NAND_ECCSIZE)
1320 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1321
1322 static int nand_read_page(int block, int page, void *dst)
1323 {
1324         struct nand_chip *this = mtd_to_nand(mtd);
1325         u_char ecc_calc[ECCTOTAL];
1326         u_char ecc_code[ECCTOTAL];
1327         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1328         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1329         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1330         int eccsteps = ECCSTEPS;
1331         int i;
1332         uint8_t *p = dst;
1333         nand_command(block, page, 0, NAND_CMD_READ0);
1334
1335         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1336                 if (this->ecc.mode != NAND_ECC_SOFT)
1337                         this->ecc.hwctl(mtd, NAND_ECC_READ);
1338                 this->read_buf(mtd, p, eccsize);
1339                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
1340         }
1341         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1342
1343         for (i = 0; i < ECCTOTAL; i++)
1344                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1345
1346         eccsteps = ECCSTEPS;
1347         p = dst;
1348
1349         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1350                 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1351
1352         return 0;
1353 }
1354
1355 int spl_nand_erase_one(int block, int page)
1356 {
1357         struct nand_chip *this = mtd_to_nand(mtd);
1358         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1359                         unsigned int ctrl) = this->cmd_ctrl;
1360         int page_addr;
1361
1362         if (nand_chip.select_chip)
1363                 nand_chip.select_chip(mtd, 0);
1364
1365         page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1366         hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1367         /* Row address */
1368         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1369         hwctrl(mtd, ((page_addr >> 8) & 0xff),
1370                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1371 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1372         /* One more address cycle for devices > 128MiB */
1373         hwctrl(mtd, (page_addr >> 16) & 0x0f,
1374                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1375 #endif
1376         hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1377
1378         while (!this->dev_ready(mtd))
1379                 ;
1380
1381         nand_deselect();
1382
1383         return 0;
1384 }
1385 #else
1386 static int nand_read_page(int block, int page, void *dst)
1387 {
1388         struct nand_chip *this = mtd_to_nand(mtd);
1389
1390         nand_command(block, page, 0, NAND_CMD_READ0);
1391         atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1392
1393         return 0;
1394 }
1395 #endif /* CONFIG_SPL_NAND_ECC */
1396
1397 int at91_nand_wait_ready(struct mtd_info *mtd)
1398 {
1399         struct nand_chip *this = mtd_to_nand(mtd);
1400
1401         udelay(this->chip_delay);
1402
1403         return 1;
1404 }
1405
1406 int board_nand_init(struct nand_chip *nand)
1407 {
1408         int ret = 0;
1409
1410         nand->ecc.mode = NAND_ECC_SOFT;
1411 #ifdef CONFIG_SYS_NAND_DBW_16
1412         nand->options = NAND_BUSWIDTH_16;
1413         nand->read_buf = nand_read_buf16;
1414 #else
1415         nand->read_buf = nand_read_buf;
1416 #endif
1417         nand->cmd_ctrl = at91_nand_hwcontrol;
1418 #ifdef CONFIG_SYS_NAND_READY_PIN
1419         nand->dev_ready = at91_nand_ready;
1420 #else
1421         nand->dev_ready = at91_nand_wait_ready;
1422 #endif
1423         nand->chip_delay = 20;
1424 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1425         nand->bbt_options |= NAND_BBT_USE_FLASH;
1426 #endif
1427
1428 #ifdef CONFIG_ATMEL_NAND_HWECC
1429 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1430         ret = atmel_pmecc_nand_init_params(nand, mtd);
1431 #endif
1432 #endif
1433
1434         return ret;
1435 }
1436
1437 void nand_init(void)
1438 {
1439         mtd = nand_to_mtd(&nand_chip);
1440         mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1441         mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1442         nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1443         nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1444         board_nand_init(&nand_chip);
1445
1446 #ifdef CONFIG_SPL_NAND_ECC
1447         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1448                 nand_chip.ecc.calculate = nand_calculate_ecc;
1449                 nand_chip.ecc.correct = nand_correct_data;
1450         }
1451 #endif
1452
1453         if (nand_chip.select_chip)
1454                 nand_chip.select_chip(mtd, 0);
1455 }
1456
1457 void nand_deselect(void)
1458 {
1459         if (nand_chip.select_chip)
1460                 nand_chip.select_chip(mtd, -1);
1461 }
1462
1463 #include "nand_spl_loaders.c"
1464
1465 #else
1466
1467 #ifndef CONFIG_SYS_NAND_BASE_LIST
1468 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1469 #endif
1470 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1471 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1472
1473 int atmel_nand_chip_init(int devnum, ulong base_addr)
1474 {
1475         int ret;
1476         struct nand_chip *nand = &nand_chip[devnum];
1477         struct mtd_info *mtd = nand_to_mtd(nand);
1478
1479         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1480
1481 #ifdef CONFIG_NAND_ECC_BCH
1482         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1483 #else
1484         nand->ecc.mode = NAND_ECC_SOFT;
1485 #endif
1486 #ifdef CONFIG_SYS_NAND_DBW_16
1487         nand->options = NAND_BUSWIDTH_16;
1488 #endif
1489         nand->cmd_ctrl = at91_nand_hwcontrol;
1490 #ifdef CONFIG_SYS_NAND_READY_PIN
1491         nand->dev_ready = at91_nand_ready;
1492 #endif
1493         nand->chip_delay = 75;
1494 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1495         nand->bbt_options |= NAND_BBT_USE_FLASH;
1496 #endif
1497
1498         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1499         if (ret)
1500                 return ret;
1501
1502 #ifdef CONFIG_ATMEL_NAND_HWECC
1503 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1504         ret = atmel_pmecc_nand_init_params(nand, mtd);
1505 #else
1506         ret = atmel_hwecc_nand_init_param(nand, mtd);
1507 #endif
1508         if (ret)
1509                 return ret;
1510 #endif
1511
1512         ret = nand_scan_tail(mtd);
1513         if (!ret)
1514                 nand_register(devnum, mtd);
1515
1516         return ret;
1517 }
1518
1519 void board_nand_init(void)
1520 {
1521         int i;
1522         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1523                 if (atmel_nand_chip_init(i, base_addr[i]))
1524                         log_err("atmel_nand: Fail to initialize #%d chip", i);
1525 }
1526 #endif /* CONFIG_SPL_BUILD */