drivers/mtd/nand/raw/atmel/nand-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2017 ATMEL
   4  * Copyright 2017 Free Electrons
   5  *
   6  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   7  *
   8  * Derived from the atmel_nand.c driver which contained the following
   9  * copyrights:
  10  *
  11  *   Copyright 2003 Rick Bronson
  12  *
  13  *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
  14  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
  15  *
  16  *   Derived from drivers/mtd/spia.c (removed in v3.8)
  17  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
  18  *
  19  *
  20  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  21  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
  22  *
  23  *   Derived from Das U-Boot source code
  24  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  25  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  26  *
  27  *   Add Programmable Multibit ECC support for various AT91 SoC
  28  *      Copyright 2012 ATMEL, Hong Xu
  29  *
  30  *   Add Nand Flash Controller support for SAMA5 SoC
  31  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  32  *
  33  * A few words about the naming convention in this file. This convention
  34  * applies to structure and function names.
  35  *
  36  * Prefixes:
  37  *
  38  * - atmel_nand_: all generic structures/functions
  39  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  40  *                    (at91sam9 and avr32 SoCs)
  41  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  42  *                     (sama5 SoCs and later)
  43  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  44  *               that is available in the HSMC block
  45  * - <soc>_nand_: all SoC specific structures/functions
  46  */
  47
  48 #include <linux/clk.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/genalloc.h>
  52 #include <linux/gpio/consumer.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/mfd/syscon.h>
  55 #include <linux/mfd/syscon/atmel-matrix.h>
  56 #include <linux/mfd/syscon/atmel-smc.h>
  57 #include <linux/module.h>
  58 #include <linux/mtd/rawnand.h>
  59 #include <linux/of_address.h>
  60 #include <linux/of_irq.h>
  61 #include <linux/of_platform.h>
  62 #include <linux/iopoll.h>
  63 #include <linux/platform_device.h>
  64 #include <linux/regmap.h>
  65 #include <soc/at91/atmel-sfr.h>
  66
  67 #include "pmecc.h"
  68
  69 #define ATMEL_HSMC_NFC_CFG                      0x0
  70 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  71 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  72 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  73 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  74 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  75 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  76 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  77 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  78 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  80
  81 #define ATMEL_HSMC_NFC_CTRL                     0x4
  82 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  83 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  84
  85 #define ATMEL_HSMC_NFC_SR                       0x8
  86 #define ATMEL_HSMC_NFC_IER                      0xc
  87 #define ATMEL_HSMC_NFC_IDR                      0x10
  88 #define ATMEL_HSMC_NFC_IMR                      0x14
  89 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  90 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  91 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  92 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  93 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
  94 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
  95 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
  96 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
  97 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
  98 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
  99 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 100 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 101 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 102                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 103                                                  ATMEL_HSMC_NFC_SR_AWB | \
 104                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 105 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 106
 107 #define ATMEL_HSMC_NFC_ADDR                     0x18
 108 #define ATMEL_HSMC_NFC_BANK                     0x1c
 109
 110 #define ATMEL_NFC_MAX_RB_ID                     7
 111
 112 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 113
 114 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 115 #define ATMEL_NFC_VCMD2                         BIT(18)
 116 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 117 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 118 #define ATMEL_NFC_DATAEN                        BIT(25)
 119 #define ATMEL_NFC_NFCWR                         BIT(26)
 120
 121 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 122
 123 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 124 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 125
 126 #define DEFAULT_TIMEOUT_MS                      1000
 127 #define MIN_DMA_LEN                             128
 128
 129 static bool atmel_nand_avoid_dma __read_mostly;
 130
 131 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
 132 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
 133
 134 enum atmel_nand_rb_type {
 135         ATMEL_NAND_NO_RB,
 136         ATMEL_NAND_NATIVE_RB,
 137         ATMEL_NAND_GPIO_RB,
 138 };
 139
 140 struct atmel_nand_rb {
 141         enum atmel_nand_rb_type type;
 142         union {
 143                 struct gpio_desc *gpio;
 144                 int id;
 145         };
 146 };
 147
 148 struct atmel_nand_cs {
 149         int id;
 150         struct atmel_nand_rb rb;
 151         struct gpio_desc *csgpio;
 152         struct {
 153                 void __iomem *virt;
 154                 dma_addr_t dma;
 155         } io;
 156
 157         struct atmel_smc_cs_conf smcconf;
 158 };
 159
 160 struct atmel_nand {
 161         struct list_head node;
 162         struct device *dev;
 163         struct nand_chip base;
 164         struct atmel_nand_cs *activecs;
 165         struct atmel_pmecc_user *pmecc;
 166         struct gpio_desc *cdgpio;
 167         int numcs;
 168         struct atmel_nand_cs cs[];
 169 };
 170
 171 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 172 {
 173         return container_of(chip, struct atmel_nand, base);
 174 }
 175
 176 enum atmel_nfc_data_xfer {
 177         ATMEL_NFC_NO_DATA,
 178         ATMEL_NFC_READ_DATA,
 179         ATMEL_NFC_WRITE_DATA,
 180 };
 181
 182 struct atmel_nfc_op {
 183         u8 cs;
 184         u8 ncmds;
 185         u8 cmds[2];
 186         u8 naddrs;
 187         u8 addrs[5];
 188         enum atmel_nfc_data_xfer data;
 189         u32 wait;
 190         u32 errors;
 191 };
 192
 193 struct atmel_nand_controller;
 194 struct atmel_nand_controller_caps;
 195
 196 struct atmel_nand_controller_ops {
 197         int (*probe)(struct platform_device *pdev,
 198                      const struct atmel_nand_controller_caps *caps);
 199         int (*remove)(struct atmel_nand_controller *nc);
 200         void (*nand_init)(struct atmel_nand_controller *nc,
 201                           struct atmel_nand *nand);
 202         int (*ecc_init)(struct nand_chip *chip);
 203         int (*setup_interface)(struct atmel_nand *nand, int csline,
 204                                const struct nand_interface_config *conf);
 205         int (*exec_op)(struct atmel_nand *nand,
 206                        const struct nand_operation *op, bool check_only);
 207 };
 208
 209 struct atmel_nand_controller_caps {
 210         bool has_dma;
 211         bool legacy_of_bindings;
 212         u32 ale_offs;
 213         u32 cle_offs;
 214         const char *ebi_csa_regmap_name;
 215         const struct atmel_nand_controller_ops *ops;
 216 };
 217
 218 struct atmel_nand_controller {
 219         struct nand_controller base;
 220         const struct atmel_nand_controller_caps *caps;
 221         struct device *dev;
 222         struct regmap *smc;
 223         struct dma_chan *dmac;
 224         struct atmel_pmecc *pmecc;
 225         struct list_head chips;
 226         struct clk *mck;
 227 };
 228
 229 static inline struct atmel_nand_controller *
 230 to_nand_controller(struct nand_controller *ctl)
 231 {
 232         return container_of(ctl, struct atmel_nand_controller, base);
 233 }
 234
 235 struct atmel_smc_nand_ebi_csa_cfg {
 236         u32 offs;
 237         u32 nfd0_on_d16;
 238 };
 239
 240 struct atmel_smc_nand_controller {
 241         struct atmel_nand_controller base;
 242         struct regmap *ebi_csa_regmap;
 243         struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
 244 };
 245
 246 static inline struct atmel_smc_nand_controller *
 247 to_smc_nand_controller(struct nand_controller *ctl)
 248 {
 249         return container_of(to_nand_controller(ctl),
 250                             struct atmel_smc_nand_controller, base);
 251 }
 252
 253 struct atmel_hsmc_nand_controller {
 254         struct atmel_nand_controller base;
 255         struct {
 256                 struct gen_pool *pool;
 257                 void __iomem *virt;
 258                 dma_addr_t dma;
 259         } sram;
 260         const struct atmel_hsmc_reg_layout *hsmc_layout;
 261         struct regmap *io;
 262         struct atmel_nfc_op op;
 263         struct completion complete;
 264         u32 cfg;
 265         int irq;
 266
 267         /* Only used when instantiating from legacy DT bindings. */
 268         struct clk *clk;
 269 };
 270
 271 static inline struct atmel_hsmc_nand_controller *
 272 to_hsmc_nand_controller(struct nand_controller *ctl)
 273 {
 274         return container_of(to_nand_controller(ctl),
 275                             struct atmel_hsmc_nand_controller, base);
 276 }
 277
 278 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 279 {
 280         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 281         op->wait ^= status & op->wait;
 282
 283         return !op->wait || op->errors;
 284 }
 285
 286 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
 287 {
 288         struct atmel_hsmc_nand_controller *nc = data;
 289         u32 sr, rcvd;
 290         bool done;
 291
 292         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
 293
 294         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 295         done = atmel_nfc_op_done(&nc->op, sr);
 296
 297         if (rcvd)
 298                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
 299
 300         if (done)
 301                 complete(&nc->complete);
 302
 303         return rcvd ? IRQ_HANDLED : IRQ_NONE;
 304 }
 305
 306 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 307                           unsigned int timeout_ms)
 308 {
 309         int ret;
 310
 311         if (!timeout_ms)
 312                 timeout_ms = DEFAULT_TIMEOUT_MS;
 313
 314         if (poll) {
 315                 u32 status;
 316
 317                 ret = regmap_read_poll_timeout(nc->base.smc,
 318                                                ATMEL_HSMC_NFC_SR, status,
 319                                                atmel_nfc_op_done(&nc->op,
 320                                                                  status),
 321                                                0, timeout_ms * 1000);
 322         } else {
 323                 init_completion(&nc->complete);
 324                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
 325                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 326                 ret = wait_for_completion_timeout(&nc->complete,
 327                                                 msecs_to_jiffies(timeout_ms));
 328                 if (!ret)
 329                         ret = -ETIMEDOUT;
 330                 else
 331                         ret = 0;
 332
 333                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
 334         }
 335
 336         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 337                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 338                 ret = -ETIMEDOUT;
 339         }
 340
 341         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 342                 dev_err(nc->base.dev, "Access to an undefined area\n");
 343                 ret = -EIO;
 344         }
 345
 346         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 347                 dev_err(nc->base.dev, "Access while busy\n");
 348                 ret = -EIO;
 349         }
 350
 351         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 352                 dev_err(nc->base.dev, "Wrong access size\n");
 353                 ret = -EIO;
 354         }
 355
 356         return ret;
 357 }
 358
 359 static void atmel_nand_dma_transfer_finished(void *data)
 360 {
 361         struct completion *finished = data;
 362
 363         complete(finished);
 364 }
 365
 366 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
 367                                    void *buf, dma_addr_t dev_dma, size_t len,
 368                                    enum dma_data_direction dir)
 369 {
 370         DECLARE_COMPLETION_ONSTACK(finished);
 371         dma_addr_t src_dma, dst_dma, buf_dma;
 372         struct dma_async_tx_descriptor *tx;
 373         dma_cookie_t cookie;
 374
 375         buf_dma = dma_map_single(nc->dev, buf, len, dir);
 376         if (dma_mapping_error(nc->dev, dev_dma)) {
 377                 dev_err(nc->dev,
 378                         "Failed to prepare a buffer for DMA access\n");
 379                 goto err;
 380         }
 381
 382         if (dir == DMA_FROM_DEVICE) {
 383                 src_dma = dev_dma;
 384                 dst_dma = buf_dma;
 385         } else {
 386                 src_dma = buf_dma;
 387                 dst_dma = dev_dma;
 388         }
 389
 390         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
 391                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 392         if (!tx) {
 393                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
 394                 goto err_unmap;
 395         }
 396
 397         tx->callback = atmel_nand_dma_transfer_finished;
 398         tx->callback_param = &finished;
 399
 400         cookie = dmaengine_submit(tx);
 401         if (dma_submit_error(cookie)) {
 402                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
 403                 goto err_unmap;
 404         }
 405
 406         dma_async_issue_pending(nc->dmac);
 407         wait_for_completion(&finished);
 408
 409         return 0;
 410
 411 err_unmap:
 412         dma_unmap_single(nc->dev, buf_dma, len, dir);
 413
 414 err:
 415         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
 416
 417         return -EIO;
 418 }
 419
 420 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 421 {
 422         u8 *addrs = nc->op.addrs;
 423         unsigned int op = 0;
 424         u32 addr, val;
 425         int i, ret;
 426
 427         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 428
 429         for (i = 0; i < nc->op.ncmds; i++)
 430                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 431
 432         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 433                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 434
 435         op |= ATMEL_NFC_CSID(nc->op.cs) |
 436               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 437
 438         if (nc->op.ncmds > 1)
 439                 op |= ATMEL_NFC_VCMD2;
 440
 441         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 442                (addrs[3] << 24);
 443
 444         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 445                 op |= ATMEL_NFC_DATAEN;
 446                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 447
 448                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 449                         op |= ATMEL_NFC_NFCWR;
 450         }
 451
 452         /* Clear all flags. */
 453         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 454
 455         /* Send the command. */
 456         regmap_write(nc->io, op, addr);
 457
 458         ret = atmel_nfc_wait(nc, poll, 0);
 459         if (ret)
 460                 dev_err(nc->base.dev,
 461                         "Failed to send NAND command (err = %d)!",
 462                         ret);
 463
 464         /* Reset the op state. */
 465         memset(&nc->op, 0, sizeof(nc->op));
 466
 467         return ret;
 468 }
 469
 470 static void atmel_nand_data_in(struct atmel_nand *nand, void *buf,
 471                                unsigned int len, bool force_8bit)
 472 {
 473         struct atmel_nand_controller *nc;
 474
 475         nc = to_nand_controller(nand->base.controller);
 476
 477         /*
 478          * If the controller supports DMA, the buffer address is DMA-able and
 479          * len is long enough to make DMA transfers profitable, let's trigger
 480          * a DMA transfer. If it fails, fallback to PIO mode.
 481          */
 482         if (nc->dmac && virt_addr_valid(buf) &&
 483             len >= MIN_DMA_LEN && !force_8bit &&
 484             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
 485                                      DMA_FROM_DEVICE))
 486                 return;
 487
 488         if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
 489                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 490         else
 491                 ioread8_rep(nand->activecs->io.virt, buf, len);
 492 }
 493
 494 static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf,
 495                                 unsigned int len, bool force_8bit)
 496 {
 497         struct atmel_nand_controller *nc;
 498
 499         nc = to_nand_controller(nand->base.controller);
 500
 501         /*
 502          * If the controller supports DMA, the buffer address is DMA-able and
 503          * len is long enough to make DMA transfers profitable, let's trigger
 504          * a DMA transfer. If it fails, fallback to PIO mode.
 505          */
 506         if (nc->dmac && virt_addr_valid(buf) &&
 507             len >= MIN_DMA_LEN && !force_8bit &&
 508             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
 509                                      len, DMA_TO_DEVICE))
 510                 return;
 511
 512         if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
 513                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 514         else
 515                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 516 }
 517
 518 static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms)
 519 {
 520         if (nand->activecs->rb.type == ATMEL_NAND_NO_RB)
 521                 return nand_soft_waitrdy(&nand->base, timeout_ms);
 522
 523         return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio,
 524                                  timeout_ms);
 525 }
 526
 527 static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand,
 528                                    unsigned int timeout_ms)
 529 {
 530         struct atmel_hsmc_nand_controller *nc;
 531         u32 status, mask;
 532
 533         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
 534                 return atmel_nand_waitrdy(nand, timeout_ms);
 535
 536         nc = to_hsmc_nand_controller(nand->base.controller);
 537         mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 538         return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR,
 539                                                status, status & mask,
 540                                                10, timeout_ms * 1000);
 541 }
 542
 543 static void atmel_nand_select_target(struct atmel_nand *nand,
 544                                      unsigned int cs)
 545 {
 546         nand->activecs = &nand->cs[cs];
 547 }
 548
 549 static void atmel_hsmc_nand_select_target(struct atmel_nand *nand,
 550                                           unsigned int cs)
 551 {
 552         struct mtd_info *mtd = nand_to_mtd(&nand->base);
 553         struct atmel_hsmc_nand_controller *nc;
 554         u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 555                   ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 556                   ATMEL_HSMC_NFC_CFG_RSPARE;
 557
 558         nand->activecs = &nand->cs[cs];
 559         nc = to_hsmc_nand_controller(nand->base.controller);
 560         if (nc->cfg == cfg)
 561                 return;
 562
 563         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 564                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 565                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 566                            ATMEL_HSMC_NFC_CFG_RSPARE |
 567                            ATMEL_HSMC_NFC_CFG_WSPARE,
 568                            cfg);
 569         nc->cfg = cfg;
 570 }
 571
 572 static int atmel_smc_nand_exec_instr(struct atmel_nand *nand,
 573                                      const struct nand_op_instr *instr)
 574 {
 575         struct atmel_nand_controller *nc;
 576         unsigned int i;
 577
 578         nc = to_nand_controller(nand->base.controller);
 579         switch (instr->type) {
 580         case NAND_OP_CMD_INSTR:
 581                 writeb(instr->ctx.cmd.opcode,
 582                        nand->activecs->io.virt + nc->caps->cle_offs);
 583                 return 0;
 584         case NAND_OP_ADDR_INSTR:
 585                 for (i = 0; i < instr->ctx.addr.naddrs; i++)
 586                         writeb(instr->ctx.addr.addrs[i],
 587                                nand->activecs->io.virt + nc->caps->ale_offs);
 588                 return 0;
 589         case NAND_OP_DATA_IN_INSTR:
 590                 atmel_nand_data_in(nand, instr->ctx.data.buf.in,
 591                                    instr->ctx.data.len,
 592                                    instr->ctx.data.force_8bit);
 593                 return 0;
 594         case NAND_OP_DATA_OUT_INSTR:
 595                 atmel_nand_data_out(nand, instr->ctx.data.buf.out,
 596                                     instr->ctx.data.len,
 597                                     instr->ctx.data.force_8bit);
 598                 return 0;
 599         case NAND_OP_WAITRDY_INSTR:
 600                 return atmel_nand_waitrdy(nand,
 601                                           instr->ctx.waitrdy.timeout_ms);
 602         default:
 603                 break;
 604         }
 605
 606         return -EINVAL;
 607 }
 608
 609 static int atmel_smc_nand_exec_op(struct atmel_nand *nand,
 610                                   const struct nand_operation *op,
 611                                   bool check_only)
 612 {
 613         unsigned int i;
 614         int ret = 0;
 615
 616         if (check_only)
 617                 return 0;
 618
 619         atmel_nand_select_target(nand, op->cs);
 620         gpiod_set_value(nand->activecs->csgpio, 0);
 621         for (i = 0; i < op->ninstrs; i++) {
 622                 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]);
 623                 if (ret)
 624                         break;
 625         }
 626         gpiod_set_value(nand->activecs->csgpio, 1);
 627
 628         return ret;
 629 }
 630
 631 static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip,
 632                                     const struct nand_subop *subop)
 633 {
 634         struct atmel_nand *nand = to_atmel_nand(chip);
 635         struct atmel_hsmc_nand_controller *nc;
 636         unsigned int i, j;
 637
 638         nc = to_hsmc_nand_controller(chip->controller);
 639
 640         nc->op.cs = nand->activecs->id;
 641         for (i = 0; i < subop->ninstrs; i++) {
 642                 const struct nand_op_instr *instr = &subop->instrs[i];
 643
 644                 if (instr->type == NAND_OP_CMD_INSTR) {
 645                         nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode;
 646                         continue;
 647                 }
 648
 649                 for (j = nand_subop_get_addr_start_off(subop, i);
 650                      j < nand_subop_get_num_addr_cyc(subop, i); j++) {
 651                         nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j];
 652                         nc->op.naddrs++;
 653                 }
 654         }
 655
 656         return atmel_nfc_exec_op(nc, true);
 657 }
 658
 659 static int atmel_hsmc_exec_rw(struct nand_chip *chip,
 660                               const struct nand_subop *subop)
 661 {
 662         const struct nand_op_instr *instr = subop->instrs;
 663         struct atmel_nand *nand = to_atmel_nand(chip);
 664
 665         if (instr->type == NAND_OP_DATA_IN_INSTR)
 666                 atmel_nand_data_in(nand, instr->ctx.data.buf.in,
 667                                    instr->ctx.data.len,
 668                                    instr->ctx.data.force_8bit);
 669         else
 670                 atmel_nand_data_out(nand, instr->ctx.data.buf.out,
 671                                     instr->ctx.data.len,
 672                                     instr->ctx.data.force_8bit);
 673
 674         return 0;
 675 }
 676
 677 static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip,
 678                                    const struct nand_subop *subop)
 679 {
 680         const struct nand_op_instr *instr = subop->instrs;
 681         struct atmel_nand *nand = to_atmel_nand(chip);
 682
 683         return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms);
 684 }
 685
 686 static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER(
 687         NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr,
 688                 NAND_OP_PARSER_PAT_CMD_ELEM(true),
 689                 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
 690                 NAND_OP_PARSER_PAT_CMD_ELEM(true)),
 691         NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
 692                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)),
 693         NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
 694                 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)),
 695         NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy,
 696                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
 697 );
 698
 699 static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand,
 700                                    const struct nand_operation *op,
 701                                    bool check_only)
 702 {
 703         int ret;
 704
 705         if (check_only)
 706                 return nand_op_parser_exec_op(&nand->base,
 707                                               &atmel_hsmc_op_parser, op, true);
 708
 709         atmel_hsmc_nand_select_target(nand, op->cs);
 710         ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op,
 711                                      false);
 712
 713         return ret;
 714 }
 715
 716 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 717                                    bool oob_required)
 718 {
 719         struct mtd_info *mtd = nand_to_mtd(chip);
 720         struct atmel_hsmc_nand_controller *nc;
 721         int ret = -EIO;
 722
 723         nc = to_hsmc_nand_controller(chip->controller);
 724
 725         if (nc->base.dmac)
 726                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
 727                                               nc->sram.dma, mtd->writesize,
 728                                               DMA_TO_DEVICE);
 729
 730         /* Falling back to CPU copy. */
 731         if (ret)
 732                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 733
 734         if (oob_required)
 735                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 736                             mtd->oobsize);
 737 }
 738
 739 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 740                                      bool oob_required)
 741 {
 742         struct mtd_info *mtd = nand_to_mtd(chip);
 743         struct atmel_hsmc_nand_controller *nc;
 744         int ret = -EIO;
 745
 746         nc = to_hsmc_nand_controller(chip->controller);
 747
 748         if (nc->base.dmac)
 749                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
 750                                               mtd->writesize, DMA_FROM_DEVICE);
 751
 752         /* Falling back to CPU copy. */
 753         if (ret)
 754                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 755
 756         if (oob_required)
 757                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 758                               mtd->oobsize);
 759 }
 760
 761 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 762 {
 763         struct mtd_info *mtd = nand_to_mtd(chip);
 764         struct atmel_hsmc_nand_controller *nc;
 765
 766         nc = to_hsmc_nand_controller(chip->controller);
 767
 768         if (column >= 0) {
 769                 nc->op.addrs[nc->op.naddrs++] = column;
 770
 771                 /*
 772                  * 2 address cycles for the column offset on large page NANDs.
 773                  */
 774                 if (mtd->writesize > 512)
 775                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 776         }
 777
 778         if (page >= 0) {
 779                 nc->op.addrs[nc->op.naddrs++] = page;
 780                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 781
 782                 if (chip->options & NAND_ROW_ADDR_3)
 783                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 784         }
 785 }
 786
 787 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 788 {
 789         struct atmel_nand *nand = to_atmel_nand(chip);
 790         struct atmel_nand_controller *nc;
 791         int ret;
 792
 793         nc = to_nand_controller(chip->controller);
 794
 795         if (raw)
 796                 return 0;
 797
 798         ret = atmel_pmecc_enable(nand->pmecc, op);
 799         if (ret)
 800                 dev_err(nc->dev,
 801                         "Failed to enable ECC engine (err = %d)\n", ret);
 802
 803         return ret;
 804 }
 805
 806 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 807 {
 808         struct atmel_nand *nand = to_atmel_nand(chip);
 809
 810         if (!raw)
 811                 atmel_pmecc_disable(nand->pmecc);
 812 }
 813
 814 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 815 {
 816         struct atmel_nand *nand = to_atmel_nand(chip);
 817         struct mtd_info *mtd = nand_to_mtd(chip);
 818         struct atmel_nand_controller *nc;
 819         struct mtd_oob_region oobregion;
 820         void *eccbuf;
 821         int ret, i;
 822
 823         nc = to_nand_controller(chip->controller);
 824
 825         if (raw)
 826                 return 0;
 827
 828         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 829         if (ret) {
 830                 dev_err(nc->dev,
 831                         "Failed to transfer NAND page data (err = %d)\n",
 832                         ret);
 833                 return ret;
 834         }
 835
 836         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 837         eccbuf = chip->oob_poi + oobregion.offset;
 838
 839         for (i = 0; i < chip->ecc.steps; i++) {
 840                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 841                                                    eccbuf);
 842                 eccbuf += chip->ecc.bytes;
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 849                                          bool raw)
 850 {
 851         struct atmel_nand *nand = to_atmel_nand(chip);
 852         struct mtd_info *mtd = nand_to_mtd(chip);
 853         struct atmel_nand_controller *nc;
 854         struct mtd_oob_region oobregion;
 855         int ret, i, max_bitflips = 0;
 856         void *databuf, *eccbuf;
 857
 858         nc = to_nand_controller(chip->controller);
 859
 860         if (raw)
 861                 return 0;
 862
 863         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 864         if (ret) {
 865                 dev_err(nc->dev,
 866                         "Failed to read NAND page data (err = %d)\n",
 867                         ret);
 868                 return ret;
 869         }
 870
 871         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 872         eccbuf = chip->oob_poi + oobregion.offset;
 873         databuf = buf;
 874
 875         for (i = 0; i < chip->ecc.steps; i++) {
 876                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 877                                                  eccbuf);
 878                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 879                         ret = nand_check_erased_ecc_chunk(databuf,
 880                                                           chip->ecc.size,
 881                                                           eccbuf,
 882                                                           chip->ecc.bytes,
 883                                                           NULL, 0,
 884                                                           chip->ecc.strength);
 885
 886                 if (ret >= 0)
 887                         max_bitflips = max(ret, max_bitflips);
 888                 else
 889                         mtd->ecc_stats.failed++;
 890
 891                 databuf += chip->ecc.size;
 892                 eccbuf += chip->ecc.bytes;
 893         }
 894
 895         return max_bitflips;
 896 }
 897
 898 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 899                                      bool oob_required, int page, bool raw)
 900 {
 901         struct mtd_info *mtd = nand_to_mtd(chip);
 902         struct atmel_nand *nand = to_atmel_nand(chip);
 903         int ret;
 904
 905         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 906
 907         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 908         if (ret)
 909                 return ret;
 910
 911         nand_write_data_op(chip, buf, mtd->writesize, false);
 912
 913         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 914         if (ret) {
 915                 atmel_pmecc_disable(nand->pmecc);
 916                 return ret;
 917         }
 918
 919         atmel_nand_pmecc_disable(chip, raw);
 920
 921         nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
 922
 923         return nand_prog_page_end_op(chip);
 924 }
 925
 926 static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
 927                                        int oob_required, int page)
 928 {
 929         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 930 }
 931
 932 static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
 933                                            const u8 *buf, int oob_required,
 934                                            int page)
 935 {
 936         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 937 }
 938
 939 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 940                                     bool oob_required, int page, bool raw)
 941 {
 942         struct mtd_info *mtd = nand_to_mtd(chip);
 943         int ret;
 944
 945         nand_read_page_op(chip, page, 0, NULL, 0);
 946
 947         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 948         if (ret)
 949                 return ret;
 950
 951         ret = nand_read_data_op(chip, buf, mtd->writesize, false, false);
 952         if (ret)
 953                 goto out_disable;
 954
 955         ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false);
 956         if (ret)
 957                 goto out_disable;
 958
 959         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 960
 961 out_disable:
 962         atmel_nand_pmecc_disable(chip, raw);
 963
 964         return ret;
 965 }
 966
 967 static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
 968                                       int oob_required, int page)
 969 {
 970         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 971 }
 972
 973 static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
 974                                           int oob_required, int page)
 975 {
 976         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 977 }
 978
 979 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 980                                           const u8 *buf, bool oob_required,
 981                                           int page, bool raw)
 982 {
 983         struct mtd_info *mtd = nand_to_mtd(chip);
 984         struct atmel_nand *nand = to_atmel_nand(chip);
 985         struct atmel_hsmc_nand_controller *nc;
 986         int ret;
 987
 988         atmel_hsmc_nand_select_target(nand, chip->cur_cs);
 989         nc = to_hsmc_nand_controller(chip->controller);
 990
 991         atmel_nfc_copy_to_sram(chip, buf, false);
 992
 993         nc->op.cmds[0] = NAND_CMD_SEQIN;
 994         nc->op.ncmds = 1;
 995         atmel_nfc_set_op_addr(chip, page, 0x0);
 996         nc->op.cs = nand->activecs->id;
 997         nc->op.data = ATMEL_NFC_WRITE_DATA;
 998
 999         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
1000         if (ret)
1001                 return ret;
1002
1003         ret = atmel_nfc_exec_op(nc, false);
1004         if (ret) {
1005                 atmel_nand_pmecc_disable(chip, raw);
1006                 dev_err(nc->base.dev,
1007                         "Failed to transfer NAND page data (err = %d)\n",
1008                         ret);
1009                 return ret;
1010         }
1011
1012         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
1013
1014         atmel_nand_pmecc_disable(chip, raw);
1015
1016         if (ret)
1017                 return ret;
1018
1019         nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
1020
1021         return nand_prog_page_end_op(chip);
1022 }
1023
1024 static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
1025                                             const u8 *buf, int oob_required,
1026                                             int page)
1027 {
1028         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
1029                                               false);
1030 }
1031
1032 static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
1033                                                 const u8 *buf,
1034                                                 int oob_required, int page)
1035 {
1036         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
1037                                               true);
1038 }
1039
1040 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
1041                                          bool oob_required, int page,
1042                                          bool raw)
1043 {
1044         struct mtd_info *mtd = nand_to_mtd(chip);
1045         struct atmel_nand *nand = to_atmel_nand(chip);
1046         struct atmel_hsmc_nand_controller *nc;
1047         int ret;
1048
1049         atmel_hsmc_nand_select_target(nand, chip->cur_cs);
1050         nc = to_hsmc_nand_controller(chip->controller);
1051
1052         /*
1053          * Optimized read page accessors only work when the NAND R/B pin is
1054          * connected to a native SoC R/B pin. If that's not the case, fallback
1055          * to the non-optimized one.
1056          */
1057         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
1058                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1059                                                 raw);
1060
1061         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1062
1063         if (mtd->writesize > 512)
1064                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1065
1066         atmel_nfc_set_op_addr(chip, page, 0x0);
1067         nc->op.cs = nand->activecs->id;
1068         nc->op.data = ATMEL_NFC_READ_DATA;
1069
1070         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1071         if (ret)
1072                 return ret;
1073
1074         ret = atmel_nfc_exec_op(nc, false);
1075         if (ret) {
1076                 atmel_nand_pmecc_disable(chip, raw);
1077                 dev_err(nc->base.dev,
1078                         "Failed to load NAND page data (err = %d)\n",
1079                         ret);
1080                 return ret;
1081         }
1082
1083         atmel_nfc_copy_from_sram(chip, buf, true);
1084
1085         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1086
1087         atmel_nand_pmecc_disable(chip, raw);
1088
1089         return ret;
1090 }
1091
1092 static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
1093                                            int oob_required, int page)
1094 {
1095         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1096                                              false);
1097 }
1098
1099 static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
1100                                                u8 *buf, int oob_required,
1101                                                int page)
1102 {
1103         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1104                                              true);
1105 }
1106
1107 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1108 {
1109         const struct nand_ecc_props *requirements =
1110                 nanddev_get_ecc_requirements(&chip->base);
1111         struct mtd_info *mtd = nand_to_mtd(chip);
1112         struct nand_device *nanddev = mtd_to_nanddev(mtd);
1113         struct atmel_nand *nand = to_atmel_nand(chip);
1114         struct atmel_nand_controller *nc;
1115         struct atmel_pmecc_user_req req;
1116
1117         nc = to_nand_controller(chip->controller);
1118
1119         if (!nc->pmecc) {
1120                 dev_err(nc->dev, "HW ECC not supported\n");
1121                 return -ENOTSUPP;
1122         }
1123
1124         if (nc->caps->legacy_of_bindings) {
1125                 u32 val;
1126
1127                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1128                                           &val))
1129                         chip->ecc.strength = val;
1130
1131                 if (!of_property_read_u32(nc->dev->of_node,
1132                                           "atmel,pmecc-sector-size",
1133                                           &val))
1134                         chip->ecc.size = val;
1135         }
1136
1137         if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
1138                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1139         else if (chip->ecc.strength)
1140                 req.ecc.strength = chip->ecc.strength;
1141         else if (requirements->strength)
1142                 req.ecc.strength = requirements->strength;
1143         else
1144                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1145
1146         if (chip->ecc.size)
1147                 req.ecc.sectorsize = chip->ecc.size;
1148         else if (requirements->step_size)
1149                 req.ecc.sectorsize = requirements->step_size;
1150         else
1151                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1152
1153         req.pagesize = mtd->writesize;
1154         req.oobsize = mtd->oobsize;
1155
1156         if (mtd->writesize <= 512) {
1157                 req.ecc.bytes = 4;
1158                 req.ecc.ooboffset = 0;
1159         } else {
1160                 req.ecc.bytes = mtd->oobsize - 2;
1161                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1162         }
1163
1164         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1165         if (IS_ERR(nand->pmecc))
1166                 return PTR_ERR(nand->pmecc);
1167
1168         chip->ecc.algo = NAND_ECC_ALGO_BCH;
1169         chip->ecc.size = req.ecc.sectorsize;
1170         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1171         chip->ecc.strength = req.ecc.strength;
1172
1173         chip->options |= NAND_NO_SUBPAGE_WRITE;
1174
1175         mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1176
1177         return 0;
1178 }
1179
1180 static int atmel_nand_ecc_init(struct nand_chip *chip)
1181 {
1182         struct atmel_nand_controller *nc;
1183         int ret;
1184
1185         nc = to_nand_controller(chip->controller);
1186
1187         switch (chip->ecc.engine_type) {
1188         case NAND_ECC_ENGINE_TYPE_NONE:
1189         case NAND_ECC_ENGINE_TYPE_SOFT:
1190                 /*
1191                  * Nothing to do, the core will initialize everything for us.
1192                  */
1193                 break;
1194
1195         case NAND_ECC_ENGINE_TYPE_ON_HOST:
1196                 ret = atmel_nand_pmecc_init(chip);
1197                 if (ret)
1198                         return ret;
1199
1200                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1201                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1202                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1203                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1204                 break;
1205
1206         default:
1207                 /* Other modes are not supported. */
1208                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1209                         chip->ecc.engine_type);
1210                 return -ENOTSUPP;
1211         }
1212
1213         return 0;
1214 }
1215
1216 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1217 {
1218         int ret;
1219
1220         ret = atmel_nand_ecc_init(chip);
1221         if (ret)
1222                 return ret;
1223
1224         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
1225                 return 0;
1226
1227         /* Adjust the ECC operations for the HSMC IP. */
1228         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1229         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1230         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1231         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1232
1233         return 0;
1234 }
1235
1236 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1237                                         const struct nand_interface_config *conf,
1238                                         struct atmel_smc_cs_conf *smcconf)
1239 {
1240         u32 ncycles, totalcycles, timeps, mckperiodps;
1241         struct atmel_nand_controller *nc;
1242         int ret;
1243
1244         nc = to_nand_controller(nand->base.controller);
1245
1246         /* DDR interface not supported. */
1247         if (conf->type != NAND_SDR_IFACE)
1248                 return -ENOTSUPP;
1249
1250         /*
1251          * tRC < 30ns implies EDO mode. This controller does not support this
1252          * mode.
1253          */
1254         if (conf->timings.sdr.tRC_min < 30000)
1255                 return -ENOTSUPP;
1256
1257         atmel_smc_cs_conf_init(smcconf);
1258
1259         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1260         mckperiodps *= 1000;
1261
1262         /*
1263          * Set write pulse timing. This one is easy to extract:
1264          *
1265          * NWE_PULSE = tWP
1266          */
1267         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1268         totalcycles = ncycles;
1269         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1270                                           ncycles);
1271         if (ret)
1272                 return ret;
1273
1274         /*
1275          * The write setup timing depends on the operation done on the NAND.
1276          * All operations goes through the same data bus, but the operation
1277          * type depends on the address we are writing to (ALE/CLE address
1278          * lines).
1279          * Since we have no way to differentiate the different operations at
1280          * the SMC level, we must consider the worst case (the biggest setup
1281          * time among all operation types):
1282          *
1283          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1284          */
1285         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1286                       conf->timings.sdr.tALS_min);
1287         timeps = max(timeps, conf->timings.sdr.tDS_min);
1288         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1289         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1290         totalcycles += ncycles;
1291         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1292                                           ncycles);
1293         if (ret)
1294                 return ret;
1295
1296         /*
1297          * As for the write setup timing, the write hold timing depends on the
1298          * operation done on the NAND:
1299          *
1300          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1301          */
1302         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1303                       conf->timings.sdr.tALH_min);
1304         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1305                       conf->timings.sdr.tWH_min);
1306         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1307         totalcycles += ncycles;
1308
1309         /*
1310          * The write cycle timing is directly matching tWC, but is also
1311          * dependent on the other timings on the setup and hold timings we
1312          * calculated earlier, which gives:
1313          *
1314          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1315          */
1316         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1317         ncycles = max(totalcycles, ncycles);
1318         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1319                                           ncycles);
1320         if (ret)
1321                 return ret;
1322
1323         /*
1324          * We don't want the CS line to be toggled between each byte/word
1325          * transfer to the NAND. The only way to guarantee that is to have the
1326          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1327          *
1328          * NCS_WR_PULSE = NWE_CYCLE
1329          */
1330         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1331                                           ncycles);
1332         if (ret)
1333                 return ret;
1334
1335         /*
1336          * As for the write setup timing, the read hold timing depends on the
1337          * operation done on the NAND:
1338          *
1339          * NRD_HOLD = max(tREH, tRHOH)
1340          */
1341         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1342         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1343         totalcycles = ncycles;
1344
1345         /*
1346          * TDF = tRHZ - NRD_HOLD
1347          */
1348         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1349         ncycles -= totalcycles;
1350
1351         /*
1352          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1353          * we might end up with a config that does not fit in the TDF field.
1354          * Just take the max value in this case and hope that the NAND is more
1355          * tolerant than advertised.
1356          */
1357         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1358                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1359         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1360                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1361
1362         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1363                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1364
1365         /*
1366          * Read pulse timing directly matches tRP:
1367          *
1368          * NRD_PULSE = tRP
1369          */
1370         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1371         totalcycles += ncycles;
1372         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1373                                           ncycles);
1374         if (ret)
1375                 return ret;
1376
1377         /*
1378          * The write cycle timing is directly matching tWC, but is also
1379          * dependent on the setup and hold timings we calculated earlier,
1380          * which gives:
1381          *
1382          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1383          *
1384          * NRD_SETUP is always 0.
1385          */
1386         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1387         ncycles = max(totalcycles, ncycles);
1388         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1389                                           ncycles);
1390         if (ret)
1391                 return ret;
1392
1393         /*
1394          * We don't want the CS line to be toggled between each byte/word
1395          * transfer from the NAND. The only way to guarantee that is to have
1396          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1397          *
1398          * NCS_RD_PULSE = NRD_CYCLE
1399          */
1400         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1401                                           ncycles);
1402         if (ret)
1403                 return ret;
1404
1405         /* Txxx timings are directly matching tXXX ones. */
1406         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1407         ret = atmel_smc_cs_conf_set_timing(smcconf,
1408                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1409                                            ncycles);
1410         if (ret)
1411                 return ret;
1412
1413         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1414         ret = atmel_smc_cs_conf_set_timing(smcconf,
1415                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1416                                            ncycles);
1417         /*
1418          * Version 4 of the ONFI spec mandates that tADL be at least 400
1419          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1420          * fit in the tADL field of the SMC reg. We need to relax the check and
1421          * accept the -ERANGE return code.
1422          *
1423          * Note that previous versions of the ONFI spec had a lower tADL_min
1424          * (100 or 200 ns). It's not clear why this timing constraint got
1425          * increased but it seems most NANDs are fine with values lower than
1426          * 400ns, so we should be safe.
1427          */
1428         if (ret && ret != -ERANGE)
1429                 return ret;
1430
1431         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1432         ret = atmel_smc_cs_conf_set_timing(smcconf,
1433                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1434                                            ncycles);
1435         if (ret)
1436                 return ret;
1437
1438         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1439         ret = atmel_smc_cs_conf_set_timing(smcconf,
1440                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1441                                            ncycles);
1442         if (ret)
1443                 return ret;
1444
1445         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1446         ret = atmel_smc_cs_conf_set_timing(smcconf,
1447                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1448                                            ncycles);
1449         if (ret)
1450                 return ret;
1451
1452         /* Attach the CS line to the NFC logic. */
1453         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1454
1455         /* Set the appropriate data bus width. */
1456         if (nand->base.options & NAND_BUSWIDTH_16)
1457                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1458
1459         /* Operate in NRD/NWE READ/WRITEMODE. */
1460         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1461                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1462
1463         return 0;
1464 }
1465
1466 static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,
1467                                         int csline,
1468                                         const struct nand_interface_config *conf)
1469 {
1470         struct atmel_nand_controller *nc;
1471         struct atmel_smc_cs_conf smcconf;
1472         struct atmel_nand_cs *cs;
1473         int ret;
1474
1475         nc = to_nand_controller(nand->base.controller);
1476
1477         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1478         if (ret)
1479                 return ret;
1480
1481         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1482                 return 0;
1483
1484         cs = &nand->cs[csline];
1485         cs->smcconf = smcconf;
1486         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1487
1488         return 0;
1489 }
1490
1491 static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,
1492                                         int csline,
1493                                         const struct nand_interface_config *conf)
1494 {
1495         struct atmel_hsmc_nand_controller *nc;
1496         struct atmel_smc_cs_conf smcconf;
1497         struct atmel_nand_cs *cs;
1498         int ret;
1499
1500         nc = to_hsmc_nand_controller(nand->base.controller);
1501
1502         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1503         if (ret)
1504                 return ret;
1505
1506         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1507                 return 0;
1508
1509         cs = &nand->cs[csline];
1510         cs->smcconf = smcconf;
1511
1512         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1513                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1514
1515         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1516                                  &cs->smcconf);
1517
1518         return 0;
1519 }
1520
1521 static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
1522                                       const struct nand_interface_config *conf)
1523 {
1524         struct atmel_nand *nand = to_atmel_nand(chip);
1525         struct atmel_nand_controller *nc;
1526
1527         nc = to_nand_controller(nand->base.controller);
1528
1529         if (csline >= nand->numcs ||
1530             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1531                 return -EINVAL;
1532
1533         return nc->caps->ops->setup_interface(nand, csline, conf);
1534 }
1535
1536 static int atmel_nand_exec_op(struct nand_chip *chip,
1537                               const struct nand_operation *op,
1538                               bool check_only)
1539 {
1540         struct atmel_nand *nand = to_atmel_nand(chip);
1541         struct atmel_nand_controller *nc;
1542
1543         nc = to_nand_controller(nand->base.controller);
1544
1545         return nc->caps->ops->exec_op(nand, op, check_only);
1546 }
1547
1548 static void atmel_nand_init(struct atmel_nand_controller *nc,
1549                             struct atmel_nand *nand)
1550 {
1551         struct nand_chip *chip = &nand->base;
1552         struct mtd_info *mtd = nand_to_mtd(chip);
1553
1554         mtd->dev.parent = nc->dev;
1555         nand->base.controller = &nc->base;
1556
1557         if (!nc->mck || !nc->caps->ops->setup_interface)
1558                 chip->options |= NAND_KEEP_TIMINGS;
1559
1560         /*
1561          * Use a bounce buffer when the buffer passed by the MTD user is not
1562          * suitable for DMA.
1563          */
1564         if (nc->dmac)
1565                 chip->options |= NAND_USES_DMA;
1566
1567         /* Default to HW ECC if pmecc is available. */
1568         if (nc->pmecc)
1569                 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1570 }
1571
1572 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1573                                 struct atmel_nand *nand)
1574 {
1575         struct nand_chip *chip = &nand->base;
1576         struct atmel_smc_nand_controller *smc_nc;
1577         int i;
1578
1579         atmel_nand_init(nc, nand);
1580
1581         smc_nc = to_smc_nand_controller(chip->controller);
1582         if (!smc_nc->ebi_csa_regmap)
1583                 return;
1584
1585         /* Attach the CS to the NAND Flash logic. */
1586         for (i = 0; i < nand->numcs; i++)
1587                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1588                                    smc_nc->ebi_csa->offs,
1589                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1590
1591         if (smc_nc->ebi_csa->nfd0_on_d16)
1592                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1593                                    smc_nc->ebi_csa->offs,
1594                                    smc_nc->ebi_csa->nfd0_on_d16,
1595                                    smc_nc->ebi_csa->nfd0_on_d16);
1596 }
1597
1598 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1599 {
1600         struct nand_chip *chip = &nand->base;
1601         struct mtd_info *mtd = nand_to_mtd(chip);
1602         int ret;
1603
1604         ret = mtd_device_unregister(mtd);
1605         if (ret)
1606                 return ret;
1607
1608         nand_cleanup(chip);
1609         list_del(&nand->node);
1610
1611         return 0;
1612 }
1613
1614 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1615                                             struct device_node *np,
1616                                             int reg_cells)
1617 {
1618         struct atmel_nand *nand;
1619         struct gpio_desc *gpio;
1620         int numcs, ret, i;
1621
1622         numcs = of_property_count_elems_of_size(np, "reg",
1623                                                 reg_cells * sizeof(u32));
1624         if (numcs < 1) {
1625                 dev_err(nc->dev, "Missing or invalid reg property\n");
1626                 return ERR_PTR(-EINVAL);
1627         }
1628
1629         nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
1630         if (!nand) {
1631                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1632                 return ERR_PTR(-ENOMEM);
1633         }
1634
1635         nand->numcs = numcs;
1636
1637         gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np),
1638                                      "det", GPIOD_IN, "nand-det");
1639         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1640                 dev_err(nc->dev,
1641                         "Failed to get detect gpio (err = %ld)\n",
1642                         PTR_ERR(gpio));
1643                 return ERR_CAST(gpio);
1644         }
1645
1646         if (!IS_ERR(gpio))
1647                 nand->cdgpio = gpio;
1648
1649         for (i = 0; i < numcs; i++) {
1650                 struct resource res;
1651                 u32 val;
1652
1653                 ret = of_address_to_resource(np, 0, &res);
1654                 if (ret) {
1655                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1656                                 ret);
1657                         return ERR_PTR(ret);
1658                 }
1659
1660                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1661                                                  &val);
1662                 if (ret) {
1663                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1664                                 ret);
1665                         return ERR_PTR(ret);
1666                 }
1667
1668                 nand->cs[i].id = val;
1669
1670                 nand->cs[i].io.dma = res.start;
1671                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1672                 if (IS_ERR(nand->cs[i].io.virt))
1673                         return ERR_CAST(nand->cs[i].io.virt);
1674
1675                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1676                         if (val > ATMEL_NFC_MAX_RB_ID)
1677                                 return ERR_PTR(-EINVAL);
1678
1679                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1680                         nand->cs[i].rb.id = val;
1681                 } else {
1682                         gpio = devm_fwnode_gpiod_get_index(nc->dev,
1683                                                            of_fwnode_handle(np),
1684                                                            "rb", i, GPIOD_IN,
1685                                                            "nand-rb");
1686                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1687                                 dev_err(nc->dev,
1688                                         "Failed to get R/B gpio (err = %ld)\n",
1689                                         PTR_ERR(gpio));
1690                                 return ERR_CAST(gpio);
1691                         }
1692
1693                         if (!IS_ERR(gpio)) {
1694                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1695                                 nand->cs[i].rb.gpio = gpio;
1696                         }
1697                 }
1698
1699                 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1700                                                    of_fwnode_handle(np),
1701                                                    "cs", i, GPIOD_OUT_HIGH,
1702                                                    "nand-cs");
1703                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1704                         dev_err(nc->dev,
1705                                 "Failed to get CS gpio (err = %ld)\n",
1706                                 PTR_ERR(gpio));
1707                         return ERR_CAST(gpio);
1708                 }
1709
1710                 if (!IS_ERR(gpio))
1711                         nand->cs[i].csgpio = gpio;
1712         }
1713
1714         nand_set_flash_node(&nand->base, np);
1715
1716         return nand;
1717 }
1718
1719 static int
1720 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1721                                struct atmel_nand *nand)
1722 {
1723         struct nand_chip *chip = &nand->base;
1724         struct mtd_info *mtd = nand_to_mtd(chip);
1725         int ret;
1726
1727         /* No card inserted, skip this NAND. */
1728         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1729                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1730                 return 0;
1731         }
1732
1733         nc->caps->ops->nand_init(nc, nand);
1734
1735         ret = nand_scan(chip, nand->numcs);
1736         if (ret) {
1737                 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1738                 return ret;
1739         }
1740
1741         ret = mtd_device_register(mtd, NULL, 0);
1742         if (ret) {
1743                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1744                 nand_cleanup(chip);
1745                 return ret;
1746         }
1747
1748         list_add_tail(&nand->node, &nc->chips);
1749
1750         return 0;
1751 }
1752
1753 static int
1754 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1755 {
1756         struct atmel_nand *nand, *tmp;
1757         int ret;
1758
1759         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1760                 ret = atmel_nand_controller_remove_nand(nand);
1761                 if (ret)
1762                         return ret;
1763         }
1764
1765         return 0;
1766 }
1767
1768 static int
1769 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1770 {
1771         struct device *dev = nc->dev;
1772         struct platform_device *pdev = to_platform_device(dev);
1773         struct atmel_nand *nand;
1774         struct gpio_desc *gpio;
1775         struct resource *res;
1776
1777         /*
1778          * Legacy bindings only allow connecting a single NAND with a unique CS
1779          * line to the controller.
1780          */
1781         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1782                             GFP_KERNEL);
1783         if (!nand)
1784                 return -ENOMEM;
1785
1786         nand->numcs = 1;
1787
1788         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1789         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1790         if (IS_ERR(nand->cs[0].io.virt))
1791                 return PTR_ERR(nand->cs[0].io.virt);
1792
1793         nand->cs[0].io.dma = res->start;
1794
1795         /*
1796          * The old driver was hardcoding the CS id to 3 for all sama5
1797          * controllers. Since this id is only meaningful for the sama5
1798          * controller we can safely assign this id to 3 no matter the
1799          * controller.
1800          * If one wants to connect a NAND to a different CS line, he will
1801          * have to use the new bindings.
1802          */
1803         nand->cs[0].id = 3;
1804
1805         /* R/B GPIO. */
1806         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1807         if (IS_ERR(gpio)) {
1808                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1809                         PTR_ERR(gpio));
1810                 return PTR_ERR(gpio);
1811         }
1812
1813         if (gpio) {
1814                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1815                 nand->cs[0].rb.gpio = gpio;
1816         }
1817
1818         /* CS GPIO. */
1819         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1820         if (IS_ERR(gpio)) {
1821                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1822                         PTR_ERR(gpio));
1823                 return PTR_ERR(gpio);
1824         }
1825
1826         nand->cs[0].csgpio = gpio;
1827
1828         /* Card detect GPIO. */
1829         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1830         if (IS_ERR(gpio)) {
1831                 dev_err(dev,
1832                         "Failed to get detect gpio (err = %ld)\n",
1833                         PTR_ERR(gpio));
1834                 return PTR_ERR(gpio);
1835         }
1836
1837         nand->cdgpio = gpio;
1838
1839         nand_set_flash_node(&nand->base, nc->dev->of_node);
1840
1841         return atmel_nand_controller_add_nand(nc, nand);
1842 }
1843
1844 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1845 {
1846         struct device_node *np, *nand_np;
1847         struct device *dev = nc->dev;
1848         int ret, reg_cells;
1849         u32 val;
1850
1851         /* We do not retrieve the SMC syscon when parsing old DTs. */
1852         if (nc->caps->legacy_of_bindings)
1853                 return atmel_nand_controller_legacy_add_nands(nc);
1854
1855         np = dev->of_node;
1856
1857         ret = of_property_read_u32(np, "#address-cells", &val);
1858         if (ret) {
1859                 dev_err(dev, "missing #address-cells property\n");
1860                 return ret;
1861         }
1862
1863         reg_cells = val;
1864
1865         ret = of_property_read_u32(np, "#size-cells", &val);
1866         if (ret) {
1867                 dev_err(dev, "missing #size-cells property\n");
1868                 return ret;
1869         }
1870
1871         reg_cells += val;
1872
1873         for_each_child_of_node(np, nand_np) {
1874                 struct atmel_nand *nand;
1875
1876                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1877                 if (IS_ERR(nand)) {
1878                         ret = PTR_ERR(nand);
1879                         goto err;
1880                 }
1881
1882                 ret = atmel_nand_controller_add_nand(nc, nand);
1883                 if (ret)
1884                         goto err;
1885         }
1886
1887         return 0;
1888
1889 err:
1890         atmel_nand_controller_remove_nands(nc);
1891
1892         return ret;
1893 }
1894
1895 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1896 {
1897         if (nc->dmac)
1898                 dma_release_channel(nc->dmac);
1899
1900         clk_put(nc->mck);
1901 }
1902
1903 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1904         .offs = AT91SAM9260_MATRIX_EBICSA,
1905 };
1906
1907 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1908         .offs = AT91SAM9261_MATRIX_EBICSA,
1909 };
1910
1911 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1912         .offs = AT91SAM9263_MATRIX_EBI0CSA,
1913 };
1914
1915 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1916         .offs = AT91SAM9RL_MATRIX_EBICSA,
1917 };
1918
1919 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1920         .offs = AT91SAM9G45_MATRIX_EBICSA,
1921 };
1922
1923 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1924         .offs = AT91SAM9N12_MATRIX_EBICSA,
1925 };
1926
1927 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1928         .offs = AT91SAM9X5_MATRIX_EBICSA,
1929 };
1930
1931 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1932         .offs = AT91_SFR_CCFG_EBICSA,
1933         .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1934 };
1935
1936 static const struct of_device_id atmel_ebi_csa_regmap_of_ids[] = {
1937         {
1938                 .compatible = "atmel,at91sam9260-matrix",
1939                 .data = &at91sam9260_ebi_csa,
1940         },
1941         {
1942                 .compatible = "atmel,at91sam9261-matrix",
1943                 .data = &at91sam9261_ebi_csa,
1944         },
1945         {
1946                 .compatible = "atmel,at91sam9263-matrix",
1947                 .data = &at91sam9263_ebi_csa,
1948         },
1949         {
1950                 .compatible = "atmel,at91sam9rl-matrix",
1951                 .data = &at91sam9rl_ebi_csa,
1952         },
1953         {
1954                 .compatible = "atmel,at91sam9g45-matrix",
1955                 .data = &at91sam9g45_ebi_csa,
1956         },
1957         {
1958                 .compatible = "atmel,at91sam9n12-matrix",
1959                 .data = &at91sam9n12_ebi_csa,
1960         },
1961         {
1962                 .compatible = "atmel,at91sam9x5-matrix",
1963                 .data = &at91sam9x5_ebi_csa,
1964         },
1965         {
1966                 .compatible = "microchip,sam9x60-sfr",
1967                 .data = &sam9x60_ebi_csa,
1968         },
1969         { /* sentinel */ },
1970 };
1971
1972 static int atmel_nand_attach_chip(struct nand_chip *chip)
1973 {
1974         struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1975         struct atmel_nand *nand = to_atmel_nand(chip);
1976         struct mtd_info *mtd = nand_to_mtd(chip);
1977         int ret;
1978
1979         ret = nc->caps->ops->ecc_init(chip);
1980         if (ret)
1981                 return ret;
1982
1983         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1984                 /*
1985                  * We keep the MTD name unchanged to avoid breaking platforms
1986                  * where the MTD cmdline parser is used and the bootloader
1987                  * has not been updated to use the new naming scheme.
1988                  */
1989                 mtd->name = "atmel_nand";
1990         } else if (!mtd->name) {
1991                 /*
1992                  * If the new bindings are used and the bootloader has not been
1993                  * updated to pass a new mtdparts parameter on the cmdline, you
1994                  * should define the following property in your nand node:
1995                  *
1996                  *      label = "atmel_nand";
1997                  *
1998                  * This way, mtd->name will be set by the core when
1999                  * nand_set_flash_node() is called.
2000                  */
2001                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
2002                                            "%s:nand.%d", dev_name(nc->dev),
2003                                            nand->cs[0].id);
2004                 if (!mtd->name) {
2005                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
2006                         return -ENOMEM;
2007                 }
2008         }
2009
2010         return 0;
2011 }
2012
2013 static const struct nand_controller_ops atmel_nand_controller_ops = {
2014         .attach_chip = atmel_nand_attach_chip,
2015         .setup_interface = atmel_nand_setup_interface,
2016         .exec_op = atmel_nand_exec_op,
2017 };
2018
2019 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
2020                                 struct platform_device *pdev,
2021                                 const struct atmel_nand_controller_caps *caps)
2022 {
2023         struct device *dev = &pdev->dev;
2024         struct device_node *np = dev->of_node;
2025         int ret;
2026
2027         nand_controller_init(&nc->base);
2028         nc->base.ops = &atmel_nand_controller_ops;
2029         INIT_LIST_HEAD(&nc->chips);
2030         nc->dev = dev;
2031         nc->caps = caps;
2032
2033         platform_set_drvdata(pdev, nc);
2034
2035         nc->pmecc = devm_atmel_pmecc_get(dev);
2036         if (IS_ERR(nc->pmecc))
2037                 return dev_err_probe(dev, PTR_ERR(nc->pmecc),
2038                                      "Could not get PMECC object\n");
2039
2040         if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
2041                 dma_cap_mask_t mask;
2042
2043                 dma_cap_zero(mask);
2044                 dma_cap_set(DMA_MEMCPY, mask);
2045
2046                 nc->dmac = dma_request_channel(mask, NULL, NULL);
2047                 if (!nc->dmac)
2048                         dev_err(nc->dev, "Failed to request DMA channel\n");
2049         }
2050
2051         /* We do not retrieve the SMC syscon when parsing old DTs. */
2052         if (nc->caps->legacy_of_bindings)
2053                 return 0;
2054
2055         nc->mck = of_clk_get(dev->parent->of_node, 0);
2056         if (IS_ERR(nc->mck)) {
2057                 dev_err(dev, "Failed to retrieve MCK clk\n");
2058                 return PTR_ERR(nc->mck);
2059         }
2060
2061         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2062         if (!np) {
2063                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2064                 return -EINVAL;
2065         }
2066
2067         nc->smc = syscon_node_to_regmap(np);
2068         of_node_put(np);
2069         if (IS_ERR(nc->smc)) {
2070                 ret = PTR_ERR(nc->smc);
2071                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2072                 return ret;
2073         }
2074
2075         return 0;
2076 }
2077
2078 static int
2079 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2080 {
2081         struct device *dev = nc->base.dev;
2082         const struct of_device_id *match;
2083         struct device_node *np;
2084         int ret;
2085
2086         /* We do not retrieve the EBICSA regmap when parsing old DTs. */
2087         if (nc->base.caps->legacy_of_bindings)
2088                 return 0;
2089
2090         np = of_parse_phandle(dev->parent->of_node,
2091                               nc->base.caps->ebi_csa_regmap_name, 0);
2092         if (!np)
2093                 return 0;
2094
2095         match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);
2096         if (!match) {
2097                 of_node_put(np);
2098                 return 0;
2099         }
2100
2101         nc->ebi_csa_regmap = syscon_node_to_regmap(np);
2102         of_node_put(np);
2103         if (IS_ERR(nc->ebi_csa_regmap)) {
2104                 ret = PTR_ERR(nc->ebi_csa_regmap);
2105                 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
2106                 return ret;
2107         }
2108
2109         nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
2110
2111         /*
2112          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2113          * add 4 to ->ebi_csa->offs.
2114          */
2115         if (of_device_is_compatible(dev->parent->of_node,
2116                                     "atmel,at91sam9263-ebi1"))
2117                 nc->ebi_csa->offs += 4;
2118
2119         return 0;
2120 }
2121
2122 static int
2123 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2124 {
2125         struct regmap_config regmap_conf = {
2126                 .reg_bits = 32,
2127                 .val_bits = 32,
2128                 .reg_stride = 4,
2129         };
2130
2131         struct device *dev = nc->base.dev;
2132         struct device_node *nand_np, *nfc_np;
2133         void __iomem *iomem;
2134         struct resource res;
2135         int ret;
2136
2137         nand_np = dev->of_node;
2138         nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2139         if (!nfc_np) {
2140                 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2141                 return -ENODEV;
2142         }
2143
2144         nc->clk = of_clk_get(nfc_np, 0);
2145         if (IS_ERR(nc->clk)) {
2146                 ret = PTR_ERR(nc->clk);
2147                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2148                         ret);
2149                 goto out;
2150         }
2151
2152         ret = clk_prepare_enable(nc->clk);
2153         if (ret) {
2154                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2155                         ret);
2156                 goto out;
2157         }
2158
2159         nc->irq = of_irq_get(nand_np, 0);
2160         if (nc->irq <= 0) {
2161                 ret = nc->irq ?: -ENXIO;
2162                 if (ret != -EPROBE_DEFER)
2163                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2164                                 ret);
2165                 goto out;
2166         }
2167
2168         ret = of_address_to_resource(nfc_np, 0, &res);
2169         if (ret) {
2170                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2171                         ret);
2172                 goto out;
2173         }
2174
2175         iomem = devm_ioremap_resource(dev, &res);
2176         if (IS_ERR(iomem)) {
2177                 ret = PTR_ERR(iomem);
2178                 goto out;
2179         }
2180
2181         regmap_conf.name = "nfc-io";
2182         regmap_conf.max_register = resource_size(&res) - 4;
2183         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2184         if (IS_ERR(nc->io)) {
2185                 ret = PTR_ERR(nc->io);
2186                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2187                         ret);
2188                 goto out;
2189         }
2190
2191         ret = of_address_to_resource(nfc_np, 1, &res);
2192         if (ret) {
2193                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2194                         ret);
2195                 goto out;
2196         }
2197
2198         iomem = devm_ioremap_resource(dev, &res);
2199         if (IS_ERR(iomem)) {
2200                 ret = PTR_ERR(iomem);
2201                 goto out;
2202         }
2203
2204         regmap_conf.name = "smc";
2205         regmap_conf.max_register = resource_size(&res) - 4;
2206         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2207         if (IS_ERR(nc->base.smc)) {
2208                 ret = PTR_ERR(nc->base.smc);
2209                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2210                         ret);
2211                 goto out;
2212         }
2213
2214         ret = of_address_to_resource(nfc_np, 2, &res);
2215         if (ret) {
2216                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2217                         ret);
2218                 goto out;
2219         }
2220
2221         nc->sram.virt = devm_ioremap_resource(dev, &res);
2222         if (IS_ERR(nc->sram.virt)) {
2223                 ret = PTR_ERR(nc->sram.virt);
2224                 goto out;
2225         }
2226
2227         nc->sram.dma = res.start;
2228
2229 out:
2230         of_node_put(nfc_np);
2231
2232         return ret;
2233 }
2234
2235 static int
2236 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2237 {
2238         struct device *dev = nc->base.dev;
2239         struct device_node *np;
2240         int ret;
2241
2242         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2243         if (!np) {
2244                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2245                 return -EINVAL;
2246         }
2247
2248         nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2249
2250         nc->irq = of_irq_get(np, 0);
2251         of_node_put(np);
2252         if (nc->irq <= 0) {
2253                 ret = nc->irq ?: -ENXIO;
2254                 if (ret != -EPROBE_DEFER)
2255                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2256                                 ret);
2257                 return ret;
2258         }
2259
2260         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2261         if (!np) {
2262                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2263                 return -EINVAL;
2264         }
2265
2266         nc->io = syscon_node_to_regmap(np);
2267         of_node_put(np);
2268         if (IS_ERR(nc->io)) {
2269                 ret = PTR_ERR(nc->io);
2270                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2271                 return ret;
2272         }
2273
2274         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2275                                          "atmel,nfc-sram", 0);
2276         if (!nc->sram.pool) {
2277                 dev_err(nc->base.dev, "Missing SRAM\n");
2278                 return -ENOMEM;
2279         }
2280
2281         nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2282                                                            ATMEL_NFC_SRAM_SIZE,
2283                                                            &nc->sram.dma);
2284         if (!nc->sram.virt) {
2285                 dev_err(nc->base.dev,
2286                         "Could not allocate memory from the NFC SRAM pool\n");
2287                 return -ENOMEM;
2288         }
2289
2290         return 0;
2291 }
2292
2293 static int
2294 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2295 {
2296         struct atmel_hsmc_nand_controller *hsmc_nc;
2297         int ret;
2298
2299         ret = atmel_nand_controller_remove_nands(nc);
2300         if (ret)
2301                 return ret;
2302
2303         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2304         regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2305                      ATMEL_HSMC_NFC_CTRL_DIS);
2306
2307         if (hsmc_nc->sram.pool)
2308                 gen_pool_free(hsmc_nc->sram.pool,
2309                               (unsigned long)hsmc_nc->sram.virt,
2310                               ATMEL_NFC_SRAM_SIZE);
2311
2312         if (hsmc_nc->clk) {
2313                 clk_disable_unprepare(hsmc_nc->clk);
2314                 clk_put(hsmc_nc->clk);
2315         }
2316
2317         atmel_nand_controller_cleanup(nc);
2318
2319         return 0;
2320 }
2321
2322 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2323                                 const struct atmel_nand_controller_caps *caps)
2324 {
2325         struct device *dev = &pdev->dev;
2326         struct atmel_hsmc_nand_controller *nc;
2327         int ret;
2328
2329         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2330         if (!nc)
2331                 return -ENOMEM;
2332
2333         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2334         if (ret)
2335                 return ret;
2336
2337         if (caps->legacy_of_bindings)
2338                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2339         else
2340                 ret = atmel_hsmc_nand_controller_init(nc);
2341
2342         if (ret)
2343                 return ret;
2344
2345         /* Make sure all irqs are masked before registering our IRQ handler. */
2346         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2347         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2348                                IRQF_SHARED, "nfc", nc);
2349         if (ret) {
2350                 dev_err(dev,
2351                         "Could not get register NFC interrupt handler (err = %d)\n",
2352                         ret);
2353                 goto err;
2354         }
2355
2356         /* Initial NFC configuration. */
2357         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2358                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2359         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2360                      ATMEL_HSMC_NFC_CTRL_EN);
2361
2362         ret = atmel_nand_controller_add_nands(&nc->base);
2363         if (ret)
2364                 goto err;
2365
2366         return 0;
2367
2368 err:
2369         atmel_hsmc_nand_controller_remove(&nc->base);
2370
2371         return ret;
2372 }
2373
2374 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2375         .probe = atmel_hsmc_nand_controller_probe,
2376         .remove = atmel_hsmc_nand_controller_remove,
2377         .ecc_init = atmel_hsmc_nand_ecc_init,
2378         .nand_init = atmel_nand_init,
2379         .setup_interface = atmel_hsmc_nand_setup_interface,
2380         .exec_op = atmel_hsmc_nand_exec_op,
2381 };
2382
2383 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2384         .has_dma = true,
2385         .ale_offs = BIT(21),
2386         .cle_offs = BIT(22),
2387         .ops = &atmel_hsmc_nc_ops,
2388 };
2389
2390 /* Only used to parse old bindings. */
2391 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2392         .has_dma = true,
2393         .ale_offs = BIT(21),
2394         .cle_offs = BIT(22),
2395         .ops = &atmel_hsmc_nc_ops,
2396         .legacy_of_bindings = true,
2397 };
2398
2399 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2400                                 const struct atmel_nand_controller_caps *caps)
2401 {
2402         struct device *dev = &pdev->dev;
2403         struct atmel_smc_nand_controller *nc;
2404         int ret;
2405
2406         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2407         if (!nc)
2408                 return -ENOMEM;
2409
2410         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2411         if (ret)
2412                 return ret;
2413
2414         ret = atmel_smc_nand_controller_init(nc);
2415         if (ret)
2416                 return ret;
2417
2418         return atmel_nand_controller_add_nands(&nc->base);
2419 }
2420
2421 static int
2422 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2423 {
2424         int ret;
2425
2426         ret = atmel_nand_controller_remove_nands(nc);
2427         if (ret)
2428                 return ret;
2429
2430         atmel_nand_controller_cleanup(nc);
2431
2432         return 0;
2433 }
2434
2435 /*
2436  * The SMC reg layout of at91rm9200 is completely different which prevents us
2437  * from re-using atmel_smc_nand_setup_interface() for the
2438  * ->setup_interface() hook.
2439  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2440  * ->setup_interface() unassigned.
2441  */
2442 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2443         .probe = atmel_smc_nand_controller_probe,
2444         .remove = atmel_smc_nand_controller_remove,
2445         .ecc_init = atmel_nand_ecc_init,
2446         .nand_init = atmel_smc_nand_init,
2447         .exec_op = atmel_smc_nand_exec_op,
2448 };
2449
2450 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2451         .ale_offs = BIT(21),
2452         .cle_offs = BIT(22),
2453         .ebi_csa_regmap_name = "atmel,matrix",
2454         .ops = &at91rm9200_nc_ops,
2455 };
2456
2457 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2458         .probe = atmel_smc_nand_controller_probe,
2459         .remove = atmel_smc_nand_controller_remove,
2460         .ecc_init = atmel_nand_ecc_init,
2461         .nand_init = atmel_smc_nand_init,
2462         .setup_interface = atmel_smc_nand_setup_interface,
2463         .exec_op = atmel_smc_nand_exec_op,
2464 };
2465
2466 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2467         .ale_offs = BIT(21),
2468         .cle_offs = BIT(22),
2469         .ebi_csa_regmap_name = "atmel,matrix",
2470         .ops = &atmel_smc_nc_ops,
2471 };
2472
2473 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2474         .ale_offs = BIT(22),
2475         .cle_offs = BIT(21),
2476         .ebi_csa_regmap_name = "atmel,matrix",
2477         .ops = &atmel_smc_nc_ops,
2478 };
2479
2480 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2481         .has_dma = true,
2482         .ale_offs = BIT(21),
2483         .cle_offs = BIT(22),
2484         .ebi_csa_regmap_name = "atmel,matrix",
2485         .ops = &atmel_smc_nc_ops,
2486 };
2487
2488 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2489         .has_dma = true,
2490         .ale_offs = BIT(21),
2491         .cle_offs = BIT(22),
2492         .ebi_csa_regmap_name = "microchip,sfr",
2493         .ops = &atmel_smc_nc_ops,
2494 };
2495
2496 /* Only used to parse old bindings. */
2497 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2498         .ale_offs = BIT(21),
2499         .cle_offs = BIT(22),
2500         .ops = &atmel_smc_nc_ops,
2501         .legacy_of_bindings = true,
2502 };
2503
2504 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2505         .ale_offs = BIT(22),
2506         .cle_offs = BIT(21),
2507         .ops = &atmel_smc_nc_ops,
2508         .legacy_of_bindings = true,
2509 };
2510
2511 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2512         .has_dma = true,
2513         .ale_offs = BIT(21),
2514         .cle_offs = BIT(22),
2515         .ops = &atmel_smc_nc_ops,
2516         .legacy_of_bindings = true,
2517 };
2518
2519 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2520         {
2521                 .compatible = "atmel,at91rm9200-nand-controller",
2522                 .data = &atmel_rm9200_nc_caps,
2523         },
2524         {
2525                 .compatible = "atmel,at91sam9260-nand-controller",
2526                 .data = &atmel_sam9260_nc_caps,
2527         },
2528         {
2529                 .compatible = "atmel,at91sam9261-nand-controller",
2530                 .data = &atmel_sam9261_nc_caps,
2531         },
2532         {
2533                 .compatible = "atmel,at91sam9g45-nand-controller",
2534                 .data = &atmel_sam9g45_nc_caps,
2535         },
2536         {
2537                 .compatible = "atmel,sama5d3-nand-controller",
2538                 .data = &atmel_sama5_nc_caps,
2539         },
2540         {
2541                 .compatible = "microchip,sam9x60-nand-controller",
2542                 .data = &microchip_sam9x60_nc_caps,
2543         },
2544         /* Support for old/deprecated bindings: */
2545         {
2546                 .compatible = "atmel,at91rm9200-nand",
2547                 .data = &atmel_rm9200_nand_caps,
2548         },
2549         {
2550                 .compatible = "atmel,sama5d4-nand",
2551                 .data = &atmel_rm9200_nand_caps,
2552         },
2553         {
2554                 .compatible = "atmel,sama5d2-nand",
2555                 .data = &atmel_rm9200_nand_caps,
2556         },
2557         { /* sentinel */ },
2558 };
2559 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2560
2561 static int atmel_nand_controller_probe(struct platform_device *pdev)
2562 {
2563         const struct atmel_nand_controller_caps *caps;
2564
2565         if (pdev->id_entry)
2566                 caps = (void *)pdev->id_entry->driver_data;
2567         else
2568                 caps = of_device_get_match_data(&pdev->dev);
2569
2570         if (!caps) {
2571                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2572                 return -EINVAL;
2573         }
2574
2575         if (caps->legacy_of_bindings) {
2576                 struct device_node *nfc_node;
2577                 u32 ale_offs = 21;
2578
2579                 /*
2580                  * If we are parsing legacy DT props and the DT contains a
2581                  * valid NFC node, forward the request to the sama5 logic.
2582                  */
2583                 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2584                                                    "atmel,sama5d3-nfc");
2585                 if (nfc_node) {
2586                         caps = &atmel_sama5_nand_caps;
2587                         of_node_put(nfc_node);
2588                 }
2589
2590                 /*
2591                  * Even if the compatible says we are dealing with an
2592                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2593                  * this controller supports DMA, which means we are in fact
2594                  * dealing with an at91sam9g45+ controller.
2595                  */
2596                 if (!caps->has_dma &&
2597                     of_property_read_bool(pdev->dev.of_node,
2598                                           "atmel,nand-has-dma"))
2599                         caps = &atmel_sam9g45_nand_caps;
2600
2601                 /*
2602                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2603                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2604                  * actually dealing with an at91sam9261 controller.
2605                  */
2606                 of_property_read_u32(pdev->dev.of_node,
2607                                      "atmel,nand-addr-offset", &ale_offs);
2608                 if (ale_offs != 21)
2609                         caps = &atmel_sam9261_nand_caps;
2610         }
2611
2612         return caps->ops->probe(pdev, caps);
2613 }
2614
2615 static int atmel_nand_controller_remove(struct platform_device *pdev)
2616 {
2617         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2618
2619         return nc->caps->ops->remove(nc);
2620 }
2621
2622 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2623 {
2624         struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2625         struct atmel_nand *nand;
2626
2627         if (nc->pmecc)
2628                 atmel_pmecc_reset(nc->pmecc);
2629
2630         list_for_each_entry(nand, &nc->chips, node) {
2631                 int i;
2632
2633                 for (i = 0; i < nand->numcs; i++)
2634                         nand_reset(&nand->base, i);
2635         }
2636
2637         return 0;
2638 }
2639
2640 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2641                          atmel_nand_controller_resume);
2642
2643 static struct platform_driver atmel_nand_controller_driver = {
2644         .driver = {
2645                 .name = "atmel-nand-controller",
2646                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2647                 .pm = &atmel_nand_controller_pm_ops,
2648         },
2649         .probe = atmel_nand_controller_probe,
2650         .remove = atmel_nand_controller_remove,
2651 };
2652 module_platform_driver(atmel_nand_controller_driver);
2653
2654 MODULE_LICENSE("GPL");
2655 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2656 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2657 MODULE_ALIAS("platform:atmel-nand-controller");