drivers/mtd/nand/raw/atmel/nand-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2022 ATMEL
   4  * Copyright 2017 Free Electrons
   5  *
   6  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   7  *
   8  * Derived from the atmel_nand.c driver which contained the following
   9  * copyrights:
  10  *
  11  *   Copyright 2003 Rick Bronson
  12  *
  13  *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
  14  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
  15  *
  16  *   Derived from drivers/mtd/spia.c (removed in v3.8)
  17  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
  18  *
  19  *
  20  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  21  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
  22  *
  23  *   Derived from Das U-Boot source code
  24  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  25  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  26  *
  27  *   Add Programmable Multibit ECC support for various AT91 SoC
  28  *      Copyright 2012 ATMEL, Hong Xu
  29  *
  30  *   Add Nand Flash Controller support for SAMA5 SoC
  31  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  32  *
  33  *   Port from Linux
  34  *      Balamanikandan Gunasundar(balamanikandan.gunasundar@microchip.com)
  35  *      Copyright (C) 2022 Microchip Technology Inc.
  36  *
  37  * A few words about the naming convention in this file. This convention
  38  * applies to structure and function names.
  39  *
  40  * Prefixes:
  41  *
  42  * - atmel_nand_: all generic structures/functions
  43  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  44  *                    (at91sam9 and avr32 SoCs)
  45  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  46  *                     (sama5 SoCs and later)
  47  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  48  *               that is available in the HSMC block
  49  * - <soc>_nand_: all SoC specific structures/functions
  50  */
  51
  52 #include <asm-generic/gpio.h>
  53 #include <clk.h>
  54 #include <dm/device_compat.h>
  55 #include <dm/devres.h>
  56 #include <dm/of_addr.h>
  57 #include <dm/of_access.h>
  58 #include <dm/uclass.h>
  59 #include <linux/completion.h>
  60 #include <linux/io.h>
  61 #include <linux/iopoll.h>
  62 #include <linux/ioport.h>
  63 #include <linux/mfd/syscon/atmel-matrix.h>
  64 #include <linux/mfd/syscon/atmel-smc.h>
  65 #include <linux/mtd/rawnand.h>
  66 #include <linux/mtd/mtd.h>
  67 #include <mach/at91_sfr.h>
  68 #include <nand.h>
  69 #include <regmap.h>
  70 #include <syscon.h>
  71
  72 #include "pmecc.h"
  73
  74 #define NSEC_PER_SEC    1000000000L
  75
  76 #define ATMEL_HSMC_NFC_CFG                      0x0
  77 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  78 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  79 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  80 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  81 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  82 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  83 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  84 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  85 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  86 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  87
  88 #define ATMEL_HSMC_NFC_CTRL                     0x4
  89 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  90 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  91
  92 #define ATMEL_HSMC_NFC_SR                       0x8
  93 #define ATMEL_HSMC_NFC_IER                      0xc
  94 #define ATMEL_HSMC_NFC_IDR                      0x10
  95 #define ATMEL_HSMC_NFC_IMR                      0x14
  96 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  97 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  98 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  99 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
 100 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
 101 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
 102 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
 103 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
 104 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
 105 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
 106 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 107 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 108 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 109                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 110                                                  ATMEL_HSMC_NFC_SR_AWB | \
 111                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 112 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 113
 114 #define ATMEL_HSMC_NFC_ADDR                     0x18
 115 #define ATMEL_HSMC_NFC_BANK                     0x1c
 116
 117 #define ATMEL_NFC_MAX_RB_ID                     7
 118
 119 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 120
 121 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 122 #define ATMEL_NFC_VCMD2                         BIT(18)
 123 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 124 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 125 #define ATMEL_NFC_DATAEN                        BIT(25)
 126 #define ATMEL_NFC_NFCWR                         BIT(26)
 127
 128 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 129
 130 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 131 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 132
 133 #define DEFAULT_TIMEOUT_MS                      1000
 134 #define MIN_DMA_LEN                             128
 135
 136 static struct nand_ecclayout atmel_pmecc_oobinfo;
 137
 138 struct nand_controller_ops {
 139         int (*attach_chip)(struct nand_chip *chip);
 140         int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
 141                                     const struct nand_data_interface *conf);
 142 };
 143
 144 struct nand_controller {
 145         const struct nand_controller_ops *ops;
 146 };
 147
 148 enum atmel_nand_rb_type {
 149         ATMEL_NAND_NO_RB,
 150         ATMEL_NAND_NATIVE_RB,
 151         ATMEL_NAND_GPIO_RB,
 152 };
 153
 154 struct atmel_nand_rb {
 155         enum atmel_nand_rb_type type;
 156         union {
 157                 struct gpio_desc gpio;
 158                 int id;
 159         };
 160 };
 161
 162 struct atmel_nand_cs {
 163         int id;
 164         struct atmel_nand_rb rb;
 165         struct gpio_desc csgpio;
 166         struct {
 167                 void __iomem *virt;
 168                 dma_addr_t dma;
 169         } io;
 170
 171         struct atmel_smc_cs_conf smcconf;
 172 };
 173
 174 struct atmel_nand {
 175         struct list_head node;
 176         struct udevice *dev;
 177         struct nand_chip base;
 178         struct atmel_nand_cs *activecs;
 179         struct atmel_pmecc_user *pmecc;
 180         struct gpio_desc cdgpio;
 181         int numcs;
 182         struct nand_controller *controller;
 183         struct atmel_nand_cs cs[];
 184 };
 185
 186 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 187 {
 188         return container_of(chip, struct atmel_nand, base);
 189 }
 190
 191 enum atmel_nfc_data_xfer {
 192         ATMEL_NFC_NO_DATA,
 193         ATMEL_NFC_READ_DATA,
 194         ATMEL_NFC_WRITE_DATA,
 195 };
 196
 197 struct atmel_nfc_op {
 198         u8 cs;
 199         u8 ncmds;
 200         u8 cmds[2];
 201         u8 naddrs;
 202         u8 addrs[5];
 203         enum atmel_nfc_data_xfer data;
 204         u32 wait;
 205         u32 errors;
 206 };
 207
 208 struct atmel_nand_controller;
 209 struct atmel_nand_controller_caps;
 210
 211 struct atmel_nand_controller_ops {
 212         int (*probe)(struct udevice *udev,
 213                      const struct atmel_nand_controller_caps *caps);
 214         int (*remove)(struct atmel_nand_controller *nc);
 215         void (*nand_init)(struct atmel_nand_controller *nc,
 216                           struct atmel_nand *nand);
 217         int (*ecc_init)(struct nand_chip *chip);
 218         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
 219                                     const struct nand_data_interface *conf);
 220 };
 221
 222 struct atmel_nand_controller_caps {
 223         bool has_dma;
 224         bool legacy_of_bindings;
 225         u32 ale_offs;
 226         u32 cle_offs;
 227         const char *ebi_csa_regmap_name;
 228         const struct atmel_nand_controller_ops *ops;
 229 };
 230
 231 struct atmel_nand_controller {
 232         struct nand_controller base;
 233         const struct atmel_nand_controller_caps *caps;
 234         struct udevice *dev;
 235         struct regmap *smc;
 236         struct dma_chan *dmac;
 237         struct atmel_pmecc *pmecc;
 238         struct list_head chips;
 239         struct clk *mck;
 240 };
 241
 242 static inline struct atmel_nand_controller *
 243 to_nand_controller(struct nand_controller *ctl)
 244 {
 245         return container_of(ctl, struct atmel_nand_controller, base);
 246 }
 247
 248 struct atmel_smc_nand_ebi_csa_cfg {
 249         u32 offs;
 250         u32 nfd0_on_d16;
 251 };
 252
 253 struct atmel_smc_nand_controller {
 254         struct atmel_nand_controller base;
 255         struct regmap *ebi_csa_regmap;
 256         struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
 257 };
 258
 259 static inline struct atmel_smc_nand_controller *
 260 to_smc_nand_controller(struct nand_controller *ctl)
 261 {
 262         return container_of(to_nand_controller(ctl),
 263                             struct atmel_smc_nand_controller, base);
 264 }
 265
 266 struct atmel_hsmc_nand_controller {
 267         struct atmel_nand_controller base;
 268         struct {
 269                 struct gen_pool *pool;
 270                 void __iomem *virt;
 271                 dma_addr_t dma;
 272         } sram;
 273         const struct atmel_hsmc_reg_layout *hsmc_layout;
 274         struct regmap *io;
 275         struct atmel_nfc_op op;
 276         struct completion complete;
 277         int irq;
 278
 279         /* Only used when instantiating from legacy DT bindings. */
 280         struct clk *clk;
 281 };
 282
 283 static inline struct atmel_hsmc_nand_controller *
 284 to_hsmc_nand_controller(struct nand_controller *ctl)
 285 {
 286         return container_of(to_nand_controller(ctl),
 287                             struct atmel_hsmc_nand_controller, base);
 288 }
 289
 290 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
 291                                     int oobsize, int ecc_len)
 292 {
 293         int i;
 294
 295         layout->eccbytes = ecc_len;
 296
 297         /* ECC will occupy the last ecc_len bytes continuously */
 298         for (i = 0; i < ecc_len; i++)
 299                 layout->eccpos[i] = oobsize - ecc_len + i;
 300
 301         layout->oobfree[0].offset = 2;
 302         layout->oobfree[0].length =
 303                 oobsize - ecc_len - layout->oobfree[0].offset;
 304 }
 305
 306 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 307 {
 308         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 309         op->wait ^= status & op->wait;
 310
 311         return !op->wait || op->errors;
 312 }
 313
 314 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 315                           unsigned int timeout_ms)
 316 {
 317         int ret;
 318         u32 status;
 319
 320         if (!timeout_ms)
 321                 timeout_ms = DEFAULT_TIMEOUT_MS;
 322
 323         if (poll)
 324                 ret = regmap_read_poll_timeout(nc->base.smc,
 325                                                ATMEL_HSMC_NFC_SR, status,
 326                                                atmel_nfc_op_done(&nc->op,
 327                                                                  status),
 328                                                0, timeout_ms);
 329         else
 330                 return -EOPNOTSUPP;
 331
 332         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 333                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 334                 ret = -ETIMEDOUT;
 335         }
 336
 337         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 338                 dev_err(nc->base.dev, "Access to an undefined area\n");
 339                 ret = -EIO;
 340         }
 341
 342         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 343                 dev_err(nc->base.dev, "Access while busy\n");
 344                 ret = -EIO;
 345         }
 346
 347         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 348                 dev_err(nc->base.dev, "Wrong access size\n");
 349                 ret = -EIO;
 350         }
 351
 352         return ret;
 353 }
 354
 355 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
 356 {
 357         int i;
 358
 359         for (i = 0; i < len; i++)
 360                 writeb(buf[i], addr);
 361 }
 362
 363 static void ioread8_rep(void *addr, uint8_t *buf, int len)
 364 {
 365         int i;
 366
 367         for (i = 0; i < len; i++)
 368                 buf[i] = readb(addr);
 369 }
 370
 371 static void ioread16_rep(void *addr, void *buf, int len)
 372 {
 373         int i;
 374         u16 *p = (u16 *)buf;
 375
 376         for (i = 0; i < len; i++)
 377                 p[i] = readw(addr);
 378 }
 379
 380 static void iowrite16_rep(void *addr, const void *buf, int len)
 381 {
 382         int i;
 383         u16 *p = (u16 *)buf;
 384
 385         for (i = 0; i < len; i++)
 386                 writew(p[i], addr);
 387 }
 388
 389 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
 390 {
 391         struct nand_chip *chip = mtd_to_nand(mtd);
 392         struct atmel_nand *nand = to_atmel_nand(chip);
 393
 394         return ioread8(nand->activecs->io.virt);
 395 }
 396
 397 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
 398 {
 399         struct nand_chip *chip = mtd_to_nand(mtd);
 400         struct atmel_nand *nand = to_atmel_nand(chip);
 401
 402         if (chip->options & NAND_BUSWIDTH_16)
 403                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
 404         else
 405                 iowrite8(byte, nand->activecs->io.virt);
 406 }
 407
 408 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 409 {
 410         struct nand_chip *chip = mtd_to_nand(mtd);
 411         struct atmel_nand *nand = to_atmel_nand(chip);
 412
 413         if (chip->options & NAND_BUSWIDTH_16)
 414                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 415         else
 416                 ioread8_rep(nand->activecs->io.virt, buf, len);
 417 }
 418
 419 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 420 {
 421         struct nand_chip *chip = mtd_to_nand(mtd);
 422         struct atmel_nand *nand = to_atmel_nand(chip);
 423
 424         if (chip->options & NAND_BUSWIDTH_16)
 425                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 426         else
 427                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 428 }
 429
 430 static int atmel_nand_dev_ready(struct mtd_info *mtd)
 431 {
 432         struct nand_chip  *chip = mtd_to_nand(mtd);
 433         struct atmel_nand *nand = to_atmel_nand(chip);
 434
 435         return dm_gpio_get_value(&nand->activecs->rb.gpio);
 436 }
 437
 438 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
 439 {
 440         struct nand_chip *chip =  mtd_to_nand(mtd);
 441         struct atmel_nand *nand = to_atmel_nand(chip);
 442
 443         if (cs < 0 || cs >= nand->numcs) {
 444                 nand->activecs = NULL;
 445                 chip->dev_ready = NULL;
 446                 return;
 447         }
 448
 449         nand->activecs = &nand->cs[cs];
 450
 451         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
 452                 chip->dev_ready = atmel_nand_dev_ready;
 453 }
 454
 455 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
 456 {
 457         struct nand_chip *chip = mtd_to_nand(mtd);
 458         struct atmel_nand *nand = to_atmel_nand(chip);
 459         struct atmel_hsmc_nand_controller *nc;
 460         u32 status;
 461
 462         nc = to_hsmc_nand_controller(nand->controller);
 463
 464         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
 465
 466         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 467 }
 468
 469 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
 470 {
 471         struct nand_chip *chip = mtd_to_nand(mtd);
 472         struct atmel_nand *nand = to_atmel_nand(chip);
 473         struct atmel_hsmc_nand_controller *nc;
 474
 475         nc = to_hsmc_nand_controller(nand->controller);
 476
 477         atmel_nand_select_chip(mtd, cs);
 478
 479         if (!nand->activecs) {
 480                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 481                              ATMEL_HSMC_NFC_CTRL_DIS);
 482                 return;
 483         }
 484
 485         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
 486                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
 487
 488         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 489                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 490                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 491                            ATMEL_HSMC_NFC_CFG_RSPARE |
 492                            ATMEL_HSMC_NFC_CFG_WSPARE,
 493                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 494                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 495                            ATMEL_HSMC_NFC_CFG_RSPARE);
 496         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 497                      ATMEL_HSMC_NFC_CTRL_EN);
 498 }
 499
 500 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 501 {
 502         u8 *addrs = nc->op.addrs;
 503         unsigned int op = 0;
 504         u32 addr, val;
 505         int i, ret;
 506
 507         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 508
 509         for (i = 0; i < nc->op.ncmds; i++)
 510                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 511
 512         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 513                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 514
 515         op |= ATMEL_NFC_CSID(nc->op.cs) |
 516               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 517
 518         if (nc->op.ncmds > 1)
 519                 op |= ATMEL_NFC_VCMD2;
 520
 521         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 522                (addrs[3] << 24);
 523
 524         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 525                 op |= ATMEL_NFC_DATAEN;
 526                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 527
 528                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 529                         op |= ATMEL_NFC_NFCWR;
 530         }
 531
 532         /* Clear all flags. */
 533         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 534
 535         /* Send the command. */
 536         regmap_write(nc->io, op, addr);
 537
 538         ret = atmel_nfc_wait(nc, poll, 0);
 539         if (ret)
 540                 dev_err(nc->base.dev,
 541                         "Failed to send NAND command (err = %d)!",
 542                         ret);
 543
 544         /* Reset the op state. */
 545         memset(&nc->op, 0, sizeof(nc->op));
 546
 547         return ret;
 548 }
 549
 550 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
 551                                      unsigned int ctrl)
 552 {
 553         struct nand_chip *chip = mtd_to_nand(mtd);
 554         struct atmel_nand *nand = to_atmel_nand(chip);
 555         struct atmel_hsmc_nand_controller *nc;
 556
 557         nc = to_hsmc_nand_controller(nand->controller);
 558
 559         if (ctrl & NAND_ALE) {
 560                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 561                         return;
 562
 563                 nc->op.addrs[nc->op.naddrs++] = dat;
 564         } else if (ctrl & NAND_CLE) {
 565                 if (nc->op.ncmds > 1)
 566                         return;
 567
 568                 nc->op.cmds[nc->op.ncmds++] = dat;
 569         }
 570
 571         if (dat == NAND_CMD_NONE) {
 572                 nc->op.cs = nand->activecs->id;
 573                 atmel_nfc_exec_op(nc, true);
 574         }
 575 }
 576
 577 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 578                                 unsigned int ctrl)
 579 {
 580         struct nand_chip *chip = mtd_to_nand(mtd);
 581         struct atmel_nand *nand = to_atmel_nand(chip);
 582         struct atmel_nand_controller *nc;
 583
 584         nc = to_nand_controller(nand->controller);
 585
 586         if ((ctrl & NAND_CTRL_CHANGE) &&
 587             dm_gpio_is_valid(&nand->activecs->csgpio)) {
 588                 if (ctrl & NAND_NCE)
 589                         dm_gpio_set_value(&nand->activecs->csgpio, 0);
 590                 else
 591                         dm_gpio_set_value(&nand->activecs->csgpio, 1);
 592         }
 593
 594         if (ctrl & NAND_ALE)
 595                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
 596         else if (ctrl & NAND_CLE)
 597                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
 598 }
 599
 600 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 601                                    bool oob_required)
 602 {
 603         struct mtd_info *mtd = nand_to_mtd(chip);
 604         struct atmel_nand *nand = to_atmel_nand(chip);
 605         struct atmel_hsmc_nand_controller *nc;
 606         int ret = -EIO;
 607
 608         nc = to_hsmc_nand_controller(nand->controller);
 609
 610         if (ret)
 611                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 612
 613         if (oob_required)
 614                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 615                             mtd->oobsize);
 616 }
 617
 618 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 619                                      bool oob_required)
 620 {
 621         struct mtd_info *mtd = nand_to_mtd(chip);
 622         struct atmel_nand *nand = to_atmel_nand(chip);
 623         struct atmel_hsmc_nand_controller *nc;
 624         int ret = -EIO;
 625
 626         nc = to_hsmc_nand_controller(nand->controller);
 627
 628         if (ret)
 629                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 630
 631         if (oob_required)
 632                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 633                               mtd->oobsize);
 634 }
 635
 636 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 637 {
 638         struct mtd_info *mtd = nand_to_mtd(chip);
 639         struct atmel_nand *nand = to_atmel_nand(chip);
 640         struct atmel_hsmc_nand_controller *nc;
 641
 642         nc = to_hsmc_nand_controller(nand->controller);
 643
 644         if (column >= 0) {
 645                 nc->op.addrs[nc->op.naddrs++] = column;
 646
 647                 /*
 648                  * 2 address cycles for the column offset on large page NANDs.
 649                  */
 650                 if (mtd->writesize > 512)
 651                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 652         }
 653
 654         if (page >= 0) {
 655                 nc->op.addrs[nc->op.naddrs++] = page;
 656                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 657
 658                 if (chip->options & NAND_ROW_ADDR_3)
 659                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 660         }
 661 }
 662
 663 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 664 {
 665         struct atmel_nand *nand = to_atmel_nand(chip);
 666         struct atmel_nand_controller *nc;
 667         int ret;
 668
 669         nc = to_nand_controller(nand->controller);
 670
 671         if (raw)
 672                 return 0;
 673
 674         ret = atmel_pmecc_enable(nand->pmecc, op);
 675         if (ret)
 676                 dev_err(nc->dev,
 677                         "Failed to enable ECC engine (err = %d)\n", ret);
 678
 679         return ret;
 680 }
 681
 682 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 683 {
 684         struct atmel_nand *nand = to_atmel_nand(chip);
 685
 686         if (!raw)
 687                 atmel_pmecc_disable(nand->pmecc);
 688 }
 689
 690 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 691 {
 692         struct atmel_nand *nand = to_atmel_nand(chip);
 693         struct mtd_info *mtd = nand_to_mtd(chip);
 694         struct atmel_nand_controller *nc;
 695         struct mtd_oob_region oobregion;
 696         void *eccbuf;
 697         int ret, i;
 698
 699         nc = to_nand_controller(nand->controller);
 700
 701         if (raw)
 702                 return 0;
 703
 704         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 705         if (ret) {
 706                 dev_err(nc->dev,
 707                         "Failed to transfer NAND page data (err = %d)\n",
 708                         ret);
 709                 return ret;
 710         }
 711
 712         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 713         eccbuf = chip->oob_poi + oobregion.offset;
 714
 715         for (i = 0; i < chip->ecc.steps; i++) {
 716                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 717                                                    eccbuf);
 718                 eccbuf += chip->ecc.bytes;
 719         }
 720
 721         return 0;
 722 }
 723
 724 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 725                                          bool raw)
 726 {
 727         struct atmel_nand *nand = to_atmel_nand(chip);
 728         struct mtd_info *mtd = nand_to_mtd(chip);
 729         struct atmel_nand_controller *nc;
 730         struct mtd_oob_region oobregion;
 731         int ret, i, max_bitflips = 0;
 732         void *databuf, *eccbuf;
 733
 734         nc = to_nand_controller(nand->controller);
 735
 736         if (raw)
 737                 return 0;
 738
 739         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 740         if (ret) {
 741                 dev_err(nc->dev,
 742                         "Failed to read NAND page data (err = %d)\n", ret);
 743                 return ret;
 744         }
 745
 746         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 747         eccbuf = chip->oob_poi + oobregion.offset;
 748         databuf = buf;
 749
 750         for (i = 0; i < chip->ecc.steps; i++) {
 751                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 752                                                  eccbuf);
 753                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 754                         ret = nand_check_erased_ecc_chunk(databuf,
 755                                                           chip->ecc.size,
 756                                                           eccbuf,
 757                                                           chip->ecc.bytes,
 758                                                           NULL, 0,
 759                                                           chip->ecc.strength);
 760
 761                 if (ret >= 0)
 762                         max_bitflips = max(ret, max_bitflips);
 763                 else
 764                         mtd->ecc_stats.failed++;
 765
 766                 databuf += chip->ecc.size;
 767                 eccbuf += chip->ecc.bytes;
 768         }
 769
 770         return max_bitflips;
 771 }
 772
 773 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 774                                      bool oob_required, int page, bool raw)
 775 {
 776         struct mtd_info *mtd = nand_to_mtd(chip);
 777         struct atmel_nand *nand = to_atmel_nand(chip);
 778         int ret;
 779
 780         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 781
 782         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 783         if (ret)
 784                 return ret;
 785
 786         atmel_nand_write_buf(mtd, buf, mtd->writesize);
 787
 788         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 789         if (ret) {
 790                 atmel_pmecc_disable(nand->pmecc);
 791                 return ret;
 792         }
 793
 794         atmel_nand_pmecc_disable(chip, raw);
 795
 796         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 797
 798         return nand_prog_page_end_op(chip);
 799 }
 800
 801 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 802                                        struct nand_chip *chip, const u8 *buf,
 803                                        int oob_required, int page)
 804 {
 805         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 806 }
 807
 808 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 809                                            struct nand_chip *chip,
 810                                            const u8 *buf, int oob_required,
 811                                            int page)
 812 {
 813         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 814 }
 815
 816 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 817                                     bool oob_required, int page, bool raw)
 818 {
 819         struct mtd_info *mtd = nand_to_mtd(chip);
 820         int ret;
 821
 822         nand_read_page_op(chip, page, 0, NULL, 0);
 823
 824         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 825         if (ret)
 826                 return ret;
 827
 828         atmel_nand_read_buf(mtd, buf, mtd->writesize);
 829         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 830
 831         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 832
 833         atmel_nand_pmecc_disable(chip, raw);
 834
 835         return ret;
 836 }
 837
 838 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 839                                       struct nand_chip *chip, u8 *buf,
 840                                       int oob_required, int page)
 841 {
 842         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 843 }
 844
 845 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 846                                           struct nand_chip *chip, u8 *buf,
 847                                           int oob_required, int page)
 848 {
 849         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 850 }
 851
 852 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 853                                           const u8 *buf, bool oob_required,
 854                                           int page, bool raw)
 855 {
 856         struct mtd_info *mtd = nand_to_mtd(chip);
 857         struct atmel_nand *nand = to_atmel_nand(chip);
 858         struct atmel_hsmc_nand_controller *nc;
 859         int ret, status;
 860
 861         nc = to_hsmc_nand_controller(nand->controller);
 862
 863         atmel_nfc_copy_to_sram(chip, buf, false);
 864
 865         nc->op.cmds[0] = NAND_CMD_SEQIN;
 866         nc->op.ncmds = 1;
 867         atmel_nfc_set_op_addr(chip, page, 0x0);
 868         nc->op.cs = nand->activecs->id;
 869         nc->op.data = ATMEL_NFC_WRITE_DATA;
 870
 871         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 872         if (ret)
 873                 return ret;
 874
 875         ret = atmel_nfc_exec_op(nc, true);
 876         if (ret) {
 877                 atmel_nand_pmecc_disable(chip, raw);
 878                 dev_err(nc->base.dev,
 879                         "Failed to transfer NAND page data (err = %d)\n",
 880                         ret);
 881                 return ret;
 882         }
 883
 884         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 885
 886         atmel_nand_pmecc_disable(chip, raw);
 887
 888         if (ret)
 889                 return ret;
 890
 891         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 892
 893         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
 894         nc->op.ncmds = 1;
 895         nc->op.cs = nand->activecs->id;
 896         ret = atmel_nfc_exec_op(nc, true);
 897         if (ret)
 898                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
 899                         ret);
 900
 901         status = chip->waitfunc(mtd, chip);
 902         if (status & NAND_STATUS_FAIL)
 903                 return -EIO;
 904
 905         return ret;
 906 }
 907
 908 static int
 909 atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 910                                  const u8 *buf, int oob_required,
 911                                  int page)
 912 {
 913         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 914                                               false);
 915 }
 916
 917 static int
 918 atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 919                                      const u8 *buf,
 920                                      int oob_required, int page)
 921 {
 922         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 923                                               true);
 924 }
 925
 926 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 927                                          bool oob_required, int page,
 928                                          bool raw)
 929 {
 930         struct mtd_info *mtd = nand_to_mtd(chip);
 931         struct atmel_nand *nand = to_atmel_nand(chip);
 932         struct atmel_hsmc_nand_controller *nc;
 933         int ret;
 934
 935         nc = to_hsmc_nand_controller(nand->controller);
 936
 937         /*
 938          * Optimized read page accessors only work when the NAND R/B pin is
 939          * connected to a native SoC R/B pin. If that's not the case, fallback
 940          * to the non-optimized one.
 941          */
 942         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
 943                 nand_read_page_op(chip, page, 0, NULL, 0);
 944
 945                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
 946                                                 raw);
 947         }
 948
 949         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
 950
 951         if (mtd->writesize > 512)
 952                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
 953
 954         atmel_nfc_set_op_addr(chip, page, 0x0);
 955         nc->op.cs = nand->activecs->id;
 956         nc->op.data = ATMEL_NFC_READ_DATA;
 957
 958         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 959         if (ret)
 960                 return ret;
 961
 962         ret = atmel_nfc_exec_op(nc, true);
 963         if (ret) {
 964                 atmel_nand_pmecc_disable(chip, raw);
 965                 dev_err(nc->base.dev,
 966                         "Failed to load NAND page data (err = %d)\n",
 967                         ret);
 968                 return ret;
 969         }
 970
 971         atmel_nfc_copy_from_sram(chip, buf, true);
 972
 973         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 974
 975         atmel_nand_pmecc_disable(chip, raw);
 976
 977         return ret;
 978 }
 979
 980 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
 981                                            struct nand_chip *chip, u8 *buf,
 982                                            int oob_required, int page)
 983 {
 984         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
 985                                              false);
 986 }
 987
 988 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 989                                                struct nand_chip *chip,
 990                                                u8 *buf, int oob_required,
 991                                                int page)
 992 {
 993         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
 994                                              true);
 995 }
 996
 997 static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
 998                                  struct mtd_oob_region *oobregion)
 999 {
1000         struct nand_chip *chip = mtd_to_nand(mtd);
1001         struct nand_ecc_ctrl *ecc = &chip->ecc;
1002
1003         if (section || !ecc->total)
1004                 return -ERANGE;
1005
1006         oobregion->length = ecc->total;
1007         oobregion->offset = mtd->oobsize - oobregion->length;
1008
1009         return 0;
1010 }
1011
1012 static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
1013                                   struct mtd_oob_region *oobregion)
1014 {
1015         struct nand_chip *chip = mtd_to_nand(mtd);
1016         struct nand_ecc_ctrl *ecc = &chip->ecc;
1017
1018         if (section)
1019                 return -ERANGE;
1020
1021         oobregion->length = mtd->oobsize - ecc->total - 2;
1022         oobregion->offset = 2;
1023
1024         return 0;
1025 }
1026
1027 static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
1028         .ecc = nand_ooblayout_ecc_lp,
1029         .rfree = nand_ooblayout_free_lp,
1030 };
1031
1032 const struct mtd_ooblayout_ops *nand_get_large_page_ooblayout(void)
1033 {
1034         return &nand_ooblayout_lp_ops;
1035 }
1036
1037 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1038 {
1039         struct mtd_info *mtd = nand_to_mtd(chip);
1040         struct atmel_nand *nand = to_atmel_nand(chip);
1041         struct atmel_nand_controller *nc;
1042         struct atmel_pmecc_user_req req;
1043
1044         nc = to_nand_controller(nand->controller);
1045
1046         if (!nc->pmecc) {
1047                 dev_err(nc->dev, "HW ECC not supported\n");
1048                 return -EOPNOTSUPP;
1049         }
1050
1051         if (nc->caps->legacy_of_bindings) {
1052                 u32 val;
1053
1054                 if (!ofnode_read_u32(nc->dev->node_, "atmel,pmecc-cap", &val))
1055                         chip->ecc.strength = val;
1056
1057                 if (!ofnode_read_u32(nc->dev->node_,
1058                                      "atmel,pmecc-sector-size",
1059                                      &val))
1060                         chip->ecc.size = val;
1061         }
1062
1063         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1064                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1065         else if (chip->ecc.strength)
1066                 req.ecc.strength = chip->ecc.strength;
1067         else
1068                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1069
1070         if (chip->ecc.size)
1071                 req.ecc.sectorsize = chip->ecc.size;
1072         else
1073                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1074
1075         req.pagesize = mtd->writesize;
1076         req.oobsize = mtd->oobsize;
1077
1078         if (mtd->writesize <= 512) {
1079                 req.ecc.bytes = 4;
1080                 req.ecc.ooboffset = 0;
1081         } else {
1082                 req.ecc.bytes = mtd->oobsize - 2;
1083                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1084         }
1085
1086         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1087         if (IS_ERR(nand->pmecc))
1088                 return PTR_ERR(nand->pmecc);
1089
1090         chip->ecc.algo = NAND_ECC_BCH;
1091         chip->ecc.size = req.ecc.sectorsize;
1092         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1093         chip->ecc.strength = req.ecc.strength;
1094
1095         chip->options |= NAND_NO_SUBPAGE_WRITE;
1096
1097         mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1098         pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1099                                 mtd->oobsize,
1100                                 chip->ecc.bytes);
1101         chip->ecc.layout = &atmel_pmecc_oobinfo;
1102
1103         return 0;
1104 }
1105
1106 static int atmel_nand_ecc_init(struct nand_chip *chip)
1107 {
1108         struct atmel_nand_controller *nc;
1109         struct atmel_nand *nand = to_atmel_nand(chip);
1110         int ret;
1111
1112         nc = to_nand_controller(nand->controller);
1113
1114         switch (chip->ecc.mode) {
1115         case NAND_ECC_NONE:
1116         case NAND_ECC_SOFT:
1117                 /*
1118                  * Nothing to do, the core will initialize everything for us.
1119                  */
1120                 break;
1121
1122         case NAND_ECC_HW:
1123                 ret = atmel_nand_pmecc_init(chip);
1124                 if (ret)
1125                         return ret;
1126
1127                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1128                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1129                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1130                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1131                 break;
1132
1133         default:
1134                 /* Other modes are not supported. */
1135                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1136                         chip->ecc.mode);
1137                 return -EOPNOTSUPP;
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1144 {
1145         int ret;
1146
1147         ret = atmel_nand_ecc_init(chip);
1148         if (ret)
1149                 return ret;
1150
1151         if (chip->ecc.mode != NAND_ECC_HW)
1152                 return 0;
1153
1154         /* Adjust the ECC operations for the HSMC IP. */
1155         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1156         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1157         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1158         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1159
1160         return 0;
1161 }
1162
1163 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1164                                           const struct nand_data_interface *conf,
1165                                           struct atmel_smc_cs_conf *smcconf)
1166 {
1167         u32 ncycles, totalcycles, timeps, mckperiodps;
1168         struct atmel_nand_controller *nc;
1169         int ret;
1170
1171         nc = to_nand_controller(nand->controller);
1172
1173         /* DDR interface not supported. */
1174         if (conf->type != NAND_SDR_IFACE)
1175                 return -EOPNOTSUPP;
1176
1177         /*
1178          * tRC < 30ns implies EDO mode. This controller does not support this
1179          * mode.
1180          */
1181         if (conf->timings.sdr.tRC_min < 30000)
1182                 return -EOPNOTSUPP;
1183
1184         atmel_smc_cs_conf_init(smcconf);
1185
1186         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1187         mckperiodps *= 1000;
1188
1189         /*
1190          * Set write pulse timing. This one is easy to extract:
1191          *
1192          * NWE_PULSE = tWP
1193          */
1194         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1195         totalcycles = ncycles;
1196         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1197                                           ncycles);
1198         if (ret)
1199                 return ret;
1200
1201         /*
1202          * The write setup timing depends on the operation done on the NAND.
1203          * All operations goes through the same data bus, but the operation
1204          * type depends on the address we are writing to (ALE/CLE address
1205          * lines).
1206          * Since we have no way to differentiate the different operations at
1207          * the SMC level, we must consider the worst case (the biggest setup
1208          * time among all operation types):
1209          *
1210          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1211          */
1212         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1213                       conf->timings.sdr.tALS_min);
1214         timeps = max(timeps, conf->timings.sdr.tDS_min);
1215         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1216         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1217         totalcycles += ncycles;
1218         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1219                                           ncycles);
1220         if (ret)
1221                 return ret;
1222
1223         /*
1224          * As for the write setup timing, the write hold timing depends on the
1225          * operation done on the NAND:
1226          *
1227          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1228          */
1229         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1230                       conf->timings.sdr.tALH_min);
1231         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1232                       conf->timings.sdr.tWH_min);
1233         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1234         totalcycles += ncycles;
1235
1236         /*
1237          * The write cycle timing is directly matching tWC, but is also
1238          * dependent on the other timings on the setup and hold timings we
1239          * calculated earlier, which gives:
1240          *
1241          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1242          */
1243         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1244         ncycles = max(totalcycles, ncycles);
1245         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1246                                           ncycles);
1247         if (ret)
1248                 return ret;
1249
1250         /*
1251          * We don't want the CS line to be toggled between each byte/word
1252          * transfer to the NAND. The only way to guarantee that is to have the
1253          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1254          *
1255          * NCS_WR_PULSE = NWE_CYCLE
1256          */
1257         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1258                                           ncycles);
1259         if (ret)
1260                 return ret;
1261
1262         /*
1263          * As for the write setup timing, the read hold timing depends on the
1264          * operation done on the NAND:
1265          *
1266          * NRD_HOLD = max(tREH, tRHOH)
1267          */
1268         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1269         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1270         totalcycles = ncycles;
1271
1272         /*
1273          * TDF = tRHZ - NRD_HOLD
1274          */
1275         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1276         ncycles -= totalcycles;
1277
1278         /*
1279          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1280          * we might end up with a config that does not fit in the TDF field.
1281          * Just take the max value in this case and hope that the NAND is more
1282          * tolerant than advertised.
1283          */
1284         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1285                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1286         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1287                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1288
1289         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1290                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1291
1292         /*
1293          * Read pulse timing directly matches tRP:
1294          *
1295          * NRD_PULSE = tRP
1296          */
1297         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1298         totalcycles += ncycles;
1299         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1300                                           ncycles);
1301         if (ret)
1302                 return ret;
1303
1304         /*
1305          * The write cycle timing is directly matching tWC, but is also
1306          * dependent on the setup and hold timings we calculated earlier,
1307          * which gives:
1308          *
1309          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1310          *
1311          * NRD_SETUP is always 0.
1312          */
1313         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1314         ncycles = max(totalcycles, ncycles);
1315         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1316                                           ncycles);
1317         if (ret)
1318                 return ret;
1319
1320         /*
1321          * We don't want the CS line to be toggled between each byte/word
1322          * transfer from the NAND. The only way to guarantee that is to have
1323          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1324          *
1325          * NCS_RD_PULSE = NRD_CYCLE
1326          */
1327         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1328                                           ncycles);
1329         if (ret)
1330                 return ret;
1331
1332         /* Txxx timings are directly matching tXXX ones. */
1333         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1334         ret = atmel_smc_cs_conf_set_timing(smcconf,
1335                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1336                                            ncycles);
1337         if (ret)
1338                 return ret;
1339
1340         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1341         ret = atmel_smc_cs_conf_set_timing(smcconf,
1342                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1343                                            ncycles);
1344         /*
1345          * Version 4 of the ONFI spec mandates that tADL be at least 400
1346          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1347          * fit in the tADL field of the SMC reg. We need to relax the check and
1348          * accept the -ERANGE return code.
1349          *
1350          * Note that previous versions of the ONFI spec had a lower tADL_min
1351          * (100 or 200 ns). It's not clear why this timing constraint got
1352          * increased but it seems most NANDs are fine with values lower than
1353          * 400ns, so we should be safe.
1354          */
1355         if (ret && ret != -ERANGE)
1356                 return ret;
1357
1358         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1359         ret = atmel_smc_cs_conf_set_timing(smcconf,
1360                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1361                                            ncycles);
1362         if (ret)
1363                 return ret;
1364
1365         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1366         ret = atmel_smc_cs_conf_set_timing(smcconf,
1367                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1368                                            ncycles);
1369         if (ret)
1370                 return ret;
1371
1372         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1373         ret = atmel_smc_cs_conf_set_timing(smcconf,
1374                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1375                                            ncycles);
1376         if (ret)
1377                 return ret;
1378
1379         /* Attach the CS line to the NFC logic. */
1380         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1381
1382         /* Set the appropriate data bus width. */
1383         if (nand->base.options & NAND_BUSWIDTH_16)
1384                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1385
1386         /* Operate in NRD/NWE READ/WRITEMODE. */
1387         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1388                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1389
1390         return 0;
1391 }
1392
1393 static int
1394 atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1395                                     int csline,
1396                                     const struct nand_data_interface *conf)
1397 {
1398         struct atmel_nand_controller *nc;
1399         struct atmel_smc_cs_conf smcconf;
1400         struct atmel_nand_cs *cs;
1401         int ret;
1402
1403         nc = to_nand_controller(nand->controller);
1404
1405         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1406         if (ret)
1407                 return ret;
1408
1409         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1410                 return 0;
1411
1412         cs = &nand->cs[csline];
1413         cs->smcconf = smcconf;
1414
1415         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1416
1417         return 0;
1418 }
1419
1420 static int
1421 atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1422                                      int csline,
1423                                      const struct nand_data_interface *conf)
1424 {
1425         struct atmel_hsmc_nand_controller *nc;
1426         struct atmel_smc_cs_conf smcconf;
1427         struct atmel_nand_cs *cs;
1428         int ret;
1429
1430         nc = to_hsmc_nand_controller(nand->controller);
1431
1432         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1433         if (ret)
1434                 return ret;
1435
1436         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1437                 return 0;
1438
1439         cs = &nand->cs[csline];
1440         cs->smcconf = smcconf;
1441
1442         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1443                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1444
1445         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1446                                  &cs->smcconf);
1447
1448         return 0;
1449 }
1450
1451 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1452                                            const struct nand_data_interface *conf)
1453 {
1454         struct nand_chip *chip = mtd_to_nand(mtd);
1455         struct atmel_nand *nand = to_atmel_nand(chip);
1456         struct atmel_nand_controller *nc;
1457
1458         nc = to_nand_controller(nand->controller);
1459
1460         if (csline >= nand->numcs ||
1461             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1462                 return -EINVAL;
1463
1464         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1465 }
1466
1467 #define NAND_KEEP_TIMINGS       0x00800000
1468
1469 static void atmel_nand_init(struct atmel_nand_controller *nc,
1470                             struct atmel_nand *nand)
1471 {
1472         struct nand_chip *chip = &nand->base;
1473         struct mtd_info *mtd = nand_to_mtd(chip);
1474
1475         mtd->dev->parent = nc->dev;
1476         nand->controller = &nc->base;
1477         nand->controller = &nc->base;
1478
1479         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1480         chip->read_byte = atmel_nand_read_byte;
1481         chip->write_byte = atmel_nand_write_byte;
1482         chip->read_buf = atmel_nand_read_buf;
1483         chip->write_buf = atmel_nand_write_buf;
1484         chip->select_chip = atmel_nand_select_chip;
1485         chip->setup_data_interface = atmel_nand_setup_data_interface;
1486
1487         if (!nc->mck || !nc->caps->ops->setup_data_interface)
1488                 chip->options |= NAND_KEEP_TIMINGS;
1489
1490         /* Some NANDs require a longer delay than the default one (20us). */
1491         chip->chip_delay = 40;
1492
1493         /* Default to HW ECC if pmecc is available. */
1494         if (nc->pmecc)
1495                 chip->ecc.mode = NAND_ECC_HW;
1496 }
1497
1498 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1499                                 struct atmel_nand *nand)
1500 {
1501         struct atmel_smc_nand_controller *smc_nc;
1502         int i;
1503
1504         atmel_nand_init(nc, nand);
1505
1506         smc_nc = to_smc_nand_controller(nand->controller);
1507         if (!smc_nc->ebi_csa_regmap)
1508                 return;
1509
1510         /* Attach the CS to the NAND Flash logic. */
1511         for (i = 0; i < nand->numcs; i++)
1512                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1513                                    smc_nc->ebi_csa->offs,
1514                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1515
1516         if (smc_nc->ebi_csa->nfd0_on_d16)
1517                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1518                                    smc_nc->ebi_csa->offs,
1519                                    smc_nc->ebi_csa->nfd0_on_d16,
1520                                    smc_nc->ebi_csa->nfd0_on_d16);
1521 }
1522
1523 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1524                                  struct atmel_nand *nand)
1525 {
1526         struct nand_chip *chip = &nand->base;
1527
1528         atmel_nand_init(nc, nand);
1529
1530         /* Overload some methods for the HSMC controller. */
1531         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1532         chip->select_chip = atmel_hsmc_nand_select_chip;
1533 }
1534
1535 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1536 {
1537         list_del(&nand->node);
1538
1539         return 0;
1540 }
1541
1542 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1543                                             ofnode np,
1544                                             int reg_cells)
1545 {
1546         struct atmel_nand *nand;
1547         ofnode n;
1548         int numcs = 0;
1549         int ret, i;
1550         u32 val;
1551         fdt32_t faddr;
1552         phys_addr_t base;
1553
1554         /* Count num of nand nodes */
1555         ofnode_for_each_subnode(n, ofnode_get_parent(np))
1556                 numcs++;
1557         if (numcs < 1) {
1558                 dev_err(nc->dev, "Missing or invalid reg property\n");
1559                 return ERR_PTR(-EINVAL);
1560         }
1561
1562         nand = devm_kzalloc(nc->dev,
1563                             sizeof(struct atmel_nand) +
1564                             (numcs * sizeof(struct atmel_nand_cs)),
1565                             GFP_KERNEL);
1566         if (!nand) {
1567                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1568                 return ERR_PTR(-ENOMEM);
1569         }
1570
1571         nand->numcs = numcs;
1572
1573         gpio_request_by_name_nodev(np, "det-gpios", 0, &nand->cdgpio,
1574                                    GPIOD_IS_IN);
1575
1576         for (i = 0; i < numcs; i++) {
1577                 ret = ofnode_read_u32(np, "reg", &val);
1578                 if (ret) {
1579                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1580                                 ret);
1581                         return ERR_PTR(ret);
1582                 }
1583                 nand->cs[i].id = val;
1584
1585                 /* Read base address */
1586                 struct resource res;
1587
1588                 if (ofnode_read_resource(np, 0, &res)) {
1589                         dev_err(nc->dev, "Unable to read resource\n");
1590                         return ERR_PTR(-ENOMEM);
1591                 }
1592
1593                 faddr = cpu_to_fdt32(val);
1594                 base = ofnode_translate_address(np, &faddr);
1595                 nand->cs[i].io.virt = (void *)base;
1596
1597                 if (!ofnode_read_u32(np, "atmel,rb", &val)) {
1598                         if (val > ATMEL_NFC_MAX_RB_ID)
1599                                 return ERR_PTR(-EINVAL);
1600
1601                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1602                         nand->cs[i].rb.id = val;
1603                 } else {
1604                         ret = gpio_request_by_name_nodev(np, "rb-gpios", 0,
1605                                                          &nand->cs[i].rb.gpio,
1606                                                          GPIOD_IS_IN);
1607                         if (ret && ret != -ENOENT)
1608                                 dev_err(nc->dev, "Failed to get R/B gpio (err = %d)\n", ret);
1609                         if (!ret)
1610                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1611                 }
1612
1613                 gpio_request_by_name_nodev(np, "cs-gpios", 0,
1614                                            &nand->cs[i].csgpio,
1615                                            GPIOD_IS_OUT);
1616         }
1617
1618         nand_set_flash_node(&nand->base, np);
1619
1620         return nand;
1621 }
1622
1623 static int nand_attach(struct nand_chip *chip)
1624 {
1625         struct atmel_nand *nand = to_atmel_nand(chip);
1626
1627         if (nand->controller->ops && nand->controller->ops->attach_chip)
1628                 return nand->controller->ops->attach_chip(chip);
1629
1630         return 0;
1631 }
1632
1633 int atmel_nand_scan(struct mtd_info *mtd, int maxchips)
1634 {
1635         int ret;
1636
1637         ret = nand_scan_ident(mtd, maxchips, NULL);
1638         if (ret)
1639                 return ret;
1640
1641         ret = nand_attach(mtd_to_nand(mtd));
1642         if (ret)
1643                 return ret;
1644
1645         ret = nand_scan_tail(mtd);
1646         return ret;
1647 }
1648
1649 static int
1650 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1651                                struct atmel_nand *nand)
1652 {
1653         struct nand_chip *chip = &nand->base;
1654         struct mtd_info *mtd = nand_to_mtd(chip);
1655         int ret;
1656
1657         /* No card inserted, skip this NAND. */
1658         if (dm_gpio_is_valid(&nand->cdgpio) &&
1659             dm_gpio_get_value(&nand->cdgpio)) {
1660                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1661                 return 0;
1662         }
1663
1664         nc->caps->ops->nand_init(nc, nand);
1665
1666         ret = atmel_nand_scan(mtd, nand->numcs);
1667         if (ret) {
1668                 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1669                 return ret;
1670         }
1671
1672         ret = nand_register(0, mtd);
1673         if (ret) {
1674                 dev_err(nc->dev, "nand register failed: %d\n", ret);
1675                 return ret;
1676         }
1677
1678         list_add_tail(&nand->node, &nc->chips);
1679
1680         return 0;
1681 }
1682
1683 static int
1684 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1685 {
1686         struct atmel_nand *nand, *tmp;
1687         int ret;
1688
1689         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1690                 ret = atmel_nand_controller_remove_nand(nand);
1691                 if (ret)
1692                         return ret;
1693         }
1694
1695         return 0;
1696 }
1697
1698 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1699 {
1700         ofnode np;
1701         ofnode nand_np;
1702         int ret, reg_cells;
1703         u32 val;
1704
1705         /* TODO:
1706          * Add support for legacy nands
1707          */
1708
1709         np = nc->dev->node_;
1710
1711         ret = ofnode_read_u32(np, "#address-cells", &val);
1712         if (ret) {
1713                 dev_err(nc->dev, "missing #address-cells property\n");
1714                 return ret;
1715         }
1716
1717         reg_cells = val;
1718
1719         ret = ofnode_read_u32(np, "#size-cells", &val);
1720         if (ret) {
1721                 dev_err(nc->dev, "missing #size-cells property\n");
1722                 return ret;
1723         }
1724
1725         reg_cells += val;
1726
1727         ofnode_for_each_subnode(nand_np, np) {
1728                 struct atmel_nand *nand;
1729
1730                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1731                 if (IS_ERR(nand)) {
1732                         ret = PTR_ERR(nand);
1733                         goto err;
1734                 }
1735
1736                 ret = atmel_nand_controller_add_nand(nc, nand);
1737                 if (ret)
1738                         goto err;
1739         }
1740
1741         return 0;
1742
1743 err:
1744         atmel_nand_controller_remove_nands(nc);
1745
1746         return ret;
1747 }
1748
1749 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1750         .offs = AT91SAM9260_MATRIX_EBICSA,
1751 };
1752
1753 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1754         .offs = AT91SAM9261_MATRIX_EBICSA,
1755 };
1756
1757 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1758         .offs = AT91SAM9263_MATRIX_EBI0CSA,
1759 };
1760
1761 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1762         .offs = AT91SAM9RL_MATRIX_EBICSA,
1763 };
1764
1765 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1766         .offs = AT91SAM9G45_MATRIX_EBICSA,
1767 };
1768
1769 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1770         .offs = AT91SAM9N12_MATRIX_EBICSA,
1771 };
1772
1773 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1774         .offs = AT91SAM9X5_MATRIX_EBICSA,
1775 };
1776
1777 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1778         .offs = AT91_SFR_CCFG_EBICSA,
1779         .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1780 };
1781
1782 static const struct udevice_id atmel_ebi_csa_regmap_of_ids[] = {
1783         {
1784                 .compatible = "atmel,at91sam9260-matrix",
1785                 .data = (ulong)&at91sam9260_ebi_csa,
1786         },
1787         {
1788                 .compatible = "atmel,at91sam9261-matrix",
1789                 .data = (ulong)&at91sam9261_ebi_csa,
1790         },
1791         {
1792                 .compatible = "atmel,at91sam9263-matrix",
1793                 .data = (ulong)&at91sam9263_ebi_csa,
1794         },
1795         {
1796                 .compatible = "atmel,at91sam9rl-matrix",
1797                 .data = (ulong)&at91sam9rl_ebi_csa,
1798         },
1799         {
1800                 .compatible = "atmel,at91sam9g45-matrix",
1801                 .data = (ulong)&at91sam9g45_ebi_csa,
1802         },
1803         {
1804                 .compatible = "atmel,at91sam9n12-matrix",
1805                 .data = (ulong)&at91sam9n12_ebi_csa,
1806         },
1807         {
1808                 .compatible = "atmel,at91sam9x5-matrix",
1809                 .data = (ulong)&at91sam9x5_ebi_csa,
1810         },
1811         {
1812                 .compatible = "microchip,sam9x60-sfr",
1813                 .data = (ulong)&sam9x60_ebi_csa,
1814         },
1815         { /* sentinel */ },
1816 };
1817
1818 static int atmel_nand_attach_chip(struct nand_chip *chip)
1819 {
1820         struct atmel_nand *nand = to_atmel_nand(chip);
1821         struct atmel_nand_controller *nc = to_nand_controller(nand->controller);
1822         struct mtd_info *mtd = nand_to_mtd(chip);
1823         int ret;
1824
1825         ret = nc->caps->ops->ecc_init(chip);
1826         if (ret)
1827                 return ret;
1828
1829         if (nc->caps->legacy_of_bindings || !ofnode_valid(nc->dev->node_)) {
1830                 /*
1831                  * We keep the MTD name unchanged to avoid breaking platforms
1832                  * where the MTD cmdline parser is used and the bootloader
1833                  * has not been updated to use the new naming scheme.
1834                  */
1835                 mtd->name = "atmel_nand";
1836         } else if (!mtd->name) {
1837                 /*
1838                  * If the new bindings are used and the bootloader has not been
1839                  * updated to pass a new mtdparts parameter on the cmdline, you
1840                  * should define the following property in your nand node:
1841                  *
1842                  *      label = "atmel_nand";
1843                  *
1844                  * This way, mtd->name will be set by the core when
1845                  * nand_set_flash_node() is called.
1846                  */
1847                 sprintf(mtd->name, "%s:nand.%d", nc->dev->name, nand->cs[0].id);
1848         }
1849
1850         return 0;
1851 }
1852
1853 static const struct nand_controller_ops atmel_nand_controller_ops = {
1854         .attach_chip = atmel_nand_attach_chip,
1855 };
1856
1857 static int
1858 atmel_nand_controller_init(struct atmel_nand_controller *nc,
1859                            struct udevice *dev,
1860                            const struct atmel_nand_controller_caps *caps)
1861 {
1862         struct ofnode_phandle_args args;
1863         int ret;
1864
1865         nc->base.ops = &atmel_nand_controller_ops;
1866         INIT_LIST_HEAD(&nc->chips);
1867         nc->dev = dev;
1868         nc->caps = caps;
1869
1870         nc->pmecc = devm_atmel_pmecc_get(dev);
1871         if (IS_ERR(nc->pmecc)) {
1872                 ret = PTR_ERR(nc->pmecc);
1873                 if (ret != -EPROBE_DEFER)
1874                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1875                                 ret);
1876                 return ret;
1877         }
1878
1879         /* We do not retrieve the SMC syscon when parsing old DTs. */
1880         if (nc->caps->legacy_of_bindings)
1881                 return 0;
1882
1883         nc->mck = devm_kzalloc(dev, sizeof(nc->mck), GFP_KERNEL);
1884         if (!nc->mck)
1885                 return -ENOMEM;
1886
1887         clk_get_by_index(dev->parent, 0, nc->mck);
1888         if (IS_ERR(nc->mck)) {
1889                 dev_err(dev, "Failed to retrieve MCK clk\n");
1890                 return PTR_ERR(nc->mck);
1891         }
1892
1893         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1894                                              "atmel,smc", NULL, 0, 0, &args);
1895         if (ret) {
1896                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1897                 return -EINVAL;
1898         }
1899
1900         nc->smc = syscon_node_to_regmap(args.node);
1901         if (IS_ERR(nc->smc)) {
1902                 ret = PTR_ERR(nc->smc);
1903                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1904                 return 0;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int
1911 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1912 {
1913         struct udevice *dev = nc->base.dev;
1914         struct ofnode_phandle_args args;
1915         const struct udevice_id *match = NULL;
1916         const char *name;
1917         int ret;
1918         int len;
1919         int i;
1920
1921         /* We do not retrieve the EBICSA regmap when parsing old DTs. */
1922         if (nc->base.caps->legacy_of_bindings)
1923                 return 0;
1924
1925         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1926                                              nc->base.caps->ebi_csa_regmap_name,
1927                                              NULL, 0, 0, &args);
1928         if (ret) {
1929                 dev_err(dev, "Unable to read ebi csa regmap\n");
1930                 return -EINVAL;
1931         }
1932
1933         name = ofnode_get_property(args.node, "compatible", &len);
1934
1935         for (i = 0; i < ARRAY_SIZE(atmel_ebi_csa_regmap_of_ids); i++) {
1936                 if (!strcmp(name, atmel_ebi_csa_regmap_of_ids[i].compatible)) {
1937                         match = &atmel_ebi_csa_regmap_of_ids[i];
1938                         break;
1939                 }
1940         }
1941
1942         if (!match) {
1943                 dev_err(dev, "Unable to find ebi csa conf");
1944                 return -EINVAL;
1945         }
1946         nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
1947
1948         nc->ebi_csa_regmap = syscon_node_to_regmap(args.node);
1949         if (IS_ERR(nc->ebi_csa_regmap)) {
1950                 ret = PTR_ERR(nc->ebi_csa_regmap);
1951                 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
1952                 return ret;
1953         }
1954
1955         /* TODO:
1956          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
1957          * add 4 to ->ebi_csa->offs.
1958          */
1959
1960         return 0;
1961 }
1962
1963 static int atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
1964 {
1965         struct udevice *dev = nc->base.dev;
1966         struct ofnode_phandle_args args;
1967         struct clk smc_clk;
1968         int ret;
1969         u32 addr;
1970
1971         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1972                                              "atmel,smc", NULL, 0, 0, &args);
1973         if (ret) {
1974                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1975                 return -EINVAL;
1976         }
1977
1978         nc->hsmc_layout = atmel_hsmc_get_reg_layout(args.node);
1979         if (IS_ERR(nc->hsmc_layout)) {
1980                 dev_err(dev, "Could not get hsmc layout\n");
1981                 return -EINVAL;
1982         }
1983
1984         /* Enable smc clock */
1985         ret = clk_get_by_index_nodev(args.node, 0, &smc_clk);
1986         if (ret) {
1987                 dev_err(dev, "Unable to get smc clock (err = %d)", ret);
1988                 return ret;
1989         }
1990
1991         ret = clk_prepare_enable(&smc_clk);
1992         if (ret)
1993                 return ret;
1994
1995         ret = ofnode_parse_phandle_with_args(dev->node_,
1996                                              "atmel,nfc-io", NULL, 0, 0, &args);
1997         if (ret) {
1998                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
1999                 return -EINVAL;
2000         }
2001
2002         nc->io = syscon_node_to_regmap(args.node);
2003         if (IS_ERR(nc->io)) {
2004                 ret = PTR_ERR(nc->io);
2005                 dev_err(dev, "Could not get NFC IO regmap\n");
2006                 return ret;
2007         }
2008
2009         ret = ofnode_parse_phandle_with_args(dev->node_,
2010                                              "atmel,nfc-sram", NULL, 0, 0, &args);
2011         if (ret) {
2012                 dev_err(dev, "Missing or invalid atmel,nfc-sram property\n");
2013                 return ret;
2014         }
2015
2016         ret = ofnode_read_u32(args.node, "reg", &addr);
2017         if (ret) {
2018                 dev_err(dev, "Could not read reg addr of nfc sram");
2019                 return ret;
2020         }
2021         nc->sram.virt = (void *)addr;
2022
2023         return 0;
2024 }
2025
2026 static int
2027 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2028 {
2029         struct atmel_hsmc_nand_controller *hsmc_nc;
2030         int ret;
2031
2032         ret = atmel_nand_controller_remove_nands(nc);
2033         if (ret)
2034                 return ret;
2035
2036         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2037
2038         if (hsmc_nc->clk) {
2039                 clk_disable_unprepare(hsmc_nc->clk);
2040                 devm_clk_put(nc->dev, hsmc_nc->clk);
2041         }
2042
2043         return 0;
2044 }
2045
2046 static int
2047 atmel_hsmc_nand_controller_probe(struct udevice *dev,
2048                                  const struct atmel_nand_controller_caps *caps)
2049 {
2050         struct atmel_hsmc_nand_controller *nc;
2051         int ret;
2052
2053         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2054         if (!nc)
2055                 return -ENOMEM;
2056
2057         ret = atmel_nand_controller_init(&nc->base, dev, caps);
2058         if (ret)
2059                 return ret;
2060
2061         ret = atmel_hsmc_nand_controller_init(nc);
2062         if (ret)
2063                 return ret;
2064
2065         /* Make sure all irqs are masked before registering our IRQ handler. */
2066         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2067
2068         /* Initial NFC configuration. */
2069         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2070                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2071
2072         ret = atmel_nand_controller_add_nands(&nc->base);
2073         if (ret)
2074                 goto err;
2075
2076         return 0;
2077
2078 err:
2079         atmel_hsmc_nand_controller_remove(&nc->base);
2080
2081         return ret;
2082 }
2083
2084 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2085         .probe = atmel_hsmc_nand_controller_probe,
2086         .remove = atmel_hsmc_nand_controller_remove,
2087         .ecc_init = atmel_hsmc_nand_ecc_init,
2088         .nand_init = atmel_hsmc_nand_init,
2089         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2090 };
2091
2092 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2093         .has_dma = true,
2094         .ale_offs = BIT(21),
2095         .cle_offs = BIT(22),
2096         .ops = &atmel_hsmc_nc_ops,
2097 };
2098
2099 static int
2100 atmel_smc_nand_controller_probe(struct udevice *dev,
2101                                 const struct atmel_nand_controller_caps *caps)
2102 {
2103         struct atmel_smc_nand_controller *nc;
2104         int ret;
2105
2106         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2107         if (!nc)
2108                 return -ENOMEM;
2109
2110         ret = atmel_nand_controller_init(&nc->base, dev, caps);
2111         if (ret)
2112                 return ret;
2113
2114         ret = atmel_smc_nand_controller_init(nc);
2115         if (ret)
2116                 return ret;
2117
2118         return atmel_nand_controller_add_nands(&nc->base);
2119 }
2120
2121 static int
2122 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2123 {
2124         int ret;
2125
2126         ret = atmel_nand_controller_remove_nands(nc);
2127         if (ret)
2128                 return ret;
2129
2130         return 0;
2131 }
2132
2133 /*
2134  * The SMC reg layout of at91rm9200 is completely different which prevents us
2135  * from re-using atmel_smc_nand_setup_data_interface() for the
2136  * ->setup_data_interface() hook.
2137  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2138  * ->setup_data_interface() unassigned.
2139  */
2140 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2141         .probe = atmel_smc_nand_controller_probe,
2142         .remove = atmel_smc_nand_controller_remove,
2143         .ecc_init = atmel_nand_ecc_init,
2144         .nand_init = atmel_smc_nand_init,
2145 };
2146
2147 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2148         .ale_offs = BIT(21),
2149         .cle_offs = BIT(22),
2150         .ebi_csa_regmap_name = "atmel,matrix",
2151         .ops = &at91rm9200_nc_ops,
2152 };
2153
2154 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2155         .probe = atmel_smc_nand_controller_probe,
2156         .remove = atmel_smc_nand_controller_remove,
2157         .ecc_init = atmel_nand_ecc_init,
2158         .nand_init = atmel_smc_nand_init,
2159         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2160 };
2161
2162 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2163         .ale_offs = BIT(21),
2164         .cle_offs = BIT(22),
2165         .ebi_csa_regmap_name = "atmel,matrix",
2166         .ops = &atmel_smc_nc_ops,
2167 };
2168
2169 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2170         .ale_offs = BIT(22),
2171         .cle_offs = BIT(21),
2172         .ebi_csa_regmap_name = "atmel,matrix",
2173         .ops = &atmel_smc_nc_ops,
2174 };
2175
2176 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2177         .has_dma = true,
2178         .ale_offs = BIT(21),
2179         .cle_offs = BIT(22),
2180         .ebi_csa_regmap_name = "atmel,matrix",
2181         .ops = &atmel_smc_nc_ops,
2182 };
2183
2184 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2185         .has_dma = true,
2186         .ale_offs = BIT(21),
2187         .cle_offs = BIT(22),
2188         .ebi_csa_regmap_name = "microchip,sfr",
2189         .ops = &atmel_smc_nc_ops,
2190 };
2191
2192 /* Only used to parse old bindings. */
2193 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2194         .ale_offs = BIT(21),
2195         .cle_offs = BIT(22),
2196         .ops = &atmel_smc_nc_ops,
2197         .legacy_of_bindings = true,
2198 };
2199
2200 static const struct udevice_id atmel_nand_controller_of_ids[] = {
2201         {
2202                 .compatible = "atmel,at91rm9200-nand-controller",
2203                 .data = (ulong)&atmel_rm9200_nc_caps,
2204         },
2205         {
2206                 .compatible = "atmel,at91sam9260-nand-controller",
2207                 .data = (ulong)&atmel_sam9260_nc_caps,
2208         },
2209         {
2210                 .compatible = "atmel,at91sam9261-nand-controller",
2211                 .data = (ulong)&atmel_sam9261_nc_caps,
2212         },
2213         {
2214                 .compatible = "atmel,at91sam9g45-nand-controller",
2215                 .data = (ulong)&atmel_sam9g45_nc_caps,
2216         },
2217         {
2218                 .compatible = "atmel,sama5d3-nand-controller",
2219                 .data = (ulong)&atmel_sama5_nc_caps,
2220         },
2221         {
2222                 .compatible = "microchip,sam9x60-nand-controller",
2223                 .data = (ulong)&microchip_sam9x60_nc_caps,
2224         },
2225         /* Support for old/deprecated bindings: */
2226         {
2227                 .compatible = "atmel,at91rm9200-nand",
2228                 .data = (ulong)&atmel_rm9200_nand_caps,
2229         },
2230         {
2231                 .compatible = "atmel,sama5d4-nand",
2232                 .data = (ulong)&atmel_rm9200_nand_caps,
2233         },
2234         {
2235                 .compatible = "atmel,sama5d2-nand",
2236                 .data = (ulong)&atmel_rm9200_nand_caps,
2237         },
2238         { /* sentinel */ },
2239 };
2240
2241 static int atmel_nand_controller_probe(struct udevice *dev)
2242 {
2243         const struct atmel_nand_controller_caps *caps;
2244         struct udevice *pmecc_dev;
2245
2246         caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev);
2247         if (!caps) {
2248                 printf("Could not retrieve NFC caps\n");
2249                 return -EINVAL;
2250         }
2251
2252         /* Probe pmecc driver */
2253         if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) {
2254                 printf("%s: get device fail\n", __func__);
2255                 return -EINVAL;
2256         }
2257
2258         return caps->ops->probe(dev, caps);
2259 }
2260
2261 static int atmel_nand_controller_remove(struct udevice *dev)
2262 {
2263         struct atmel_nand_controller *nc;
2264
2265         nc = (struct atmel_nand_controller *)dev_get_driver_data(dev);
2266
2267         return nc->caps->ops->remove(nc);
2268 }
2269
2270 U_BOOT_DRIVER(atmel_nand_controller) = {
2271         .name = "atmel-nand-controller",
2272         .id = UCLASS_MTD,
2273         .of_match = atmel_nand_controller_of_ids,
2274         .probe = atmel_nand_controller_probe,
2275         .remove = atmel_nand_controller_remove,
2276 };
2277
2278 void board_nand_init(void)
2279 {
2280         struct udevice *dev;
2281         int ret;
2282
2283         ret = uclass_get_device_by_driver(UCLASS_MTD,
2284                                           DM_DRIVER_GET(atmel_nand_controller),
2285                                           &dev);
2286         if (ret && ret != -ENODEV)
2287                 printf("Failed to initialize NAND controller. (error %d)\n",
2288                        ret);
2289 }