drivers/mtd/nand/raw/arasan_nfc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Arasan NAND Flash Controller Driver
   4  *
   5  * Copyright (C) 2014 - 2015 Xilinx, Inc.
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <asm/io.h>
  11 #include <linux/errno.h>
  12 #include <linux/mtd/mtd.h>
  13 #include <linux/mtd/rawnand.h>
  14 #include <linux/mtd/partitions.h>
  15 #include <linux/mtd/nand_ecc.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <dm.h>
  19 #include <nand.h>
  20
  21 struct nand_config {
  22         u32 page;
  23         bool on_die_ecc_enabled;
  24 };
  25
  26 struct arasan_nand_info {
  27         struct udevice *dev;
  28         struct nand_chip nand_chip;
  29 };
  30
  31 struct nand_regs {
  32         u32 pkt_reg;
  33         u32 memadr_reg1;
  34         u32 memadr_reg2;
  35         u32 cmd_reg;
  36         u32 pgm_reg;
  37         u32 intsts_enr;
  38         u32 intsig_enr;
  39         u32 intsts_reg;
  40         u32 rdy_busy;
  41         u32 cms_sysadr_reg;
  42         u32 flash_sts_reg;
  43         u32 tmg_reg;
  44         u32 buf_dataport;
  45         u32 ecc_reg;
  46         u32 ecc_errcnt_reg;
  47         u32 ecc_sprcmd_reg;
  48         u32 errcnt_1bitreg;
  49         u32 errcnt_2bitreg;
  50         u32 errcnt_3bitreg;
  51         u32 errcnt_4bitreg;
  52         u32 dma_sysadr0_reg;
  53         u32 dma_bufbdry_reg;
  54         u32 cpu_rls_reg;
  55         u32 errcnt_5bitreg;
  56         u32 errcnt_6bitreg;
  57         u32 errcnt_7bitreg;
  58         u32 errcnt_8bitreg;
  59         u32 data_if_reg;
  60 };
  61
  62 #define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR)
  63
  64 struct arasan_nand_command_format {
  65         u8 cmd1;
  66         u8 cmd2;
  67         u8 addr_cycles;
  68         u32 pgm;
  69 };
  70
  71 #define ONDIE_ECC_FEATURE_ADDR                  0x90
  72 #define ENABLE_ONDIE_ECC                        0x08
  73
  74 #define ARASAN_PROG_RD_MASK                     0x00000001
  75 #define ARASAN_PROG_BLK_ERS_MASK                0x00000004
  76 #define ARASAN_PROG_RD_ID_MASK                  0x00000040
  77 #define ARASAN_PROG_RD_STS_MASK                 0x00000008
  78 #define ARASAN_PROG_PG_PROG_MASK                0x00000010
  79 #define ARASAN_PROG_RD_PARAM_PG_MASK            0x00000080
  80 #define ARASAN_PROG_RST_MASK                    0x00000100
  81 #define ARASAN_PROG_GET_FTRS_MASK               0x00000200
  82 #define ARASAN_PROG_SET_FTRS_MASK               0x00000400
  83 #define ARASAN_PROG_CHNG_ROWADR_END_MASK        0x00400000
  84
  85 #define ARASAN_NAND_CMD_ECC_ON_MASK             0x80000000
  86 #define ARASAN_NAND_CMD_CMD12_MASK              0xFFFF
  87 #define ARASAN_NAND_CMD_PG_SIZE_MASK            0x3800000
  88 #define ARASAN_NAND_CMD_PG_SIZE_SHIFT           23
  89 #define ARASAN_NAND_CMD_CMD2_SHIFT              8
  90 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK          0x70000000
  91 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT         28
  92
  93 #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK         0xFFFF0000
  94 #define ARASAN_NAND_MEM_ADDR1_COL_MASK          0xFFFF
  95 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT        16
  96 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK         0xFF
  97 #define ARASAN_NAND_MEM_ADDR2_CS_MASK           0xC0000000
  98 #define ARASAN_NAND_MEM_ADDR2_CS0_MASK         (0x3 << 30)
  99 #define ARASAN_NAND_MEM_ADDR2_CS1_MASK         (0x1 << 30)
 100 #define ARASAN_NAND_MEM_ADDR2_BCH_MASK          0xE000000
 101 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT         25
 102
 103 #define ARASAN_NAND_INT_STS_ERR_EN_MASK         0x10
 104 #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK    0x08
 105 #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK     0x02
 106 #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK     0x01
 107 #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK      0x04
 108
 109 #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK        0xFFF000
 110 #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK       0x7FF
 111 #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT        12
 112
 113 #define ARASAN_NAND_ROW_ADDR_CYCL_MASK          0x0F
 114 #define ARASAN_NAND_COL_ADDR_CYCL_MASK          0xF0
 115 #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT         4
 116
 117 #define ARASAN_NAND_ECC_SIZE_SHIFT              16
 118 #define ARASAN_NAND_ECC_BCH_SHIFT               27
 119
 120 #define ARASAN_NAND_PKTSIZE_1K                  1024
 121 #define ARASAN_NAND_PKTSIZE_512                 512
 122
 123 #define ARASAN_NAND_POLL_TIMEOUT                1000000
 124 #define ARASAN_NAND_INVALID_ADDR_CYCL           0xFF
 125
 126 #define ERR_ADDR_CYCLE                          -1
 127 #define READ_BUFF_SIZE                          0x4000
 128
 129 static struct arasan_nand_command_format *curr_cmd;
 130
 131 enum addr_cycles {
 132         NAND_ADDR_CYCL_NONE,
 133         NAND_ADDR_CYCL_ONE,
 134         NAND_ADDR_CYCL_ROW,
 135         NAND_ADDR_CYCL_COL,
 136         NAND_ADDR_CYCL_BOTH,
 137 };
 138
 139 static struct arasan_nand_command_format arasan_nand_commands[] = {
 140         {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH,
 141          ARASAN_PROG_RD_MASK},
 142         {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL,
 143          ARASAN_PROG_RD_MASK},
 144         {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
 145          ARASAN_PROG_RD_ID_MASK},
 146         {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
 147          ARASAN_PROG_RD_STS_MASK},
 148         {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH,
 149          ARASAN_PROG_PG_PROG_MASK},
 150         {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL,
 151          ARASAN_PROG_CHNG_ROWADR_END_MASK},
 152         {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW,
 153          ARASAN_PROG_BLK_ERS_MASK},
 154         {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
 155          ARASAN_PROG_RST_MASK},
 156         {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
 157          ARASAN_PROG_RD_PARAM_PG_MASK},
 158         {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
 159          ARASAN_PROG_GET_FTRS_MASK},
 160         {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
 161          ARASAN_PROG_SET_FTRS_MASK},
 162         {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0},
 163 };
 164
 165 struct arasan_ecc_matrix {
 166         u32 pagesize;
 167         u32 ecc_codeword_size;
 168         u8 eccbits;
 169         u8 bch;
 170         u8 bchval;
 171         u16 eccaddr;
 172         u16 eccsize;
 173 };
 174
 175 static const struct arasan_ecc_matrix ecc_matrix[] = {
 176         {512, 512, 1, 0, 0, 0x20D, 0x3},
 177         {512, 512, 4, 1, 3, 0x209, 0x7},
 178         {512, 512, 8, 1, 2, 0x203, 0xD},
 179         /*
 180          * 2K byte page
 181          */
 182         {2048, 512, 1, 0, 0, 0x834, 0xC},
 183         {2048, 512, 4, 1, 3, 0x826, 0x1A},
 184         {2048, 512, 8, 1, 2, 0x80c, 0x34},
 185         {2048, 512, 12, 1, 1, 0x822, 0x4E},
 186         {2048, 512, 16, 1, 0, 0x808, 0x68},
 187         {2048, 1024, 24, 1, 4, 0x81c, 0x54},
 188         /*
 189          * 4K byte page
 190          */
 191         {4096, 512, 1, 0, 0, 0x1068, 0x18},
 192         {4096, 512, 4, 1, 3, 0x104c, 0x34},
 193         {4096, 512, 8, 1, 2, 0x1018, 0x68},
 194         {4096, 512, 12, 1, 1, 0x1044, 0x9C},
 195         {4096, 512, 16, 1, 0, 0x1010, 0xD0},
 196         {4096, 1024, 24, 1, 4, 0x1038, 0xA8},
 197         /*
 198          * 8K byte page
 199          */
 200         {8192, 512, 1, 0, 0, 0x20d0, 0x30},
 201         {8192, 512, 4, 1, 3, 0x2098, 0x68},
 202         {8192, 512, 8, 1, 2, 0x2030, 0xD0},
 203         {8192, 512, 12, 1, 1, 0x2088, 0x138},
 204         {8192, 512, 16, 1, 0, 0x2020, 0x1A0},
 205         {8192, 1024, 24, 1, 4, 0x2070, 0x150},
 206         /*
 207          * 16K byte page
 208          */
 209         {16384, 512, 1, 0, 0, 0x4460, 0x60},
 210         {16384, 512, 4, 1, 3, 0x43f0, 0xD0},
 211         {16384, 512, 8, 1, 2, 0x4320, 0x1A0},
 212         {16384, 512, 12, 1, 1, 0x4250, 0x270},
 213         {16384, 512, 16, 1, 0, 0x4180, 0x340},
 214         {16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
 215 };
 216
 217 static struct nand_ecclayout ondie_nand_oob_64 = {
 218         .eccbytes = 32,
 219
 220         .eccpos = {
 221                 8, 9, 10, 11, 12, 13, 14, 15,
 222                 24, 25, 26, 27, 28, 29, 30, 31,
 223                 40, 41, 42, 43, 44, 45, 46, 47,
 224                 56, 57, 58, 59, 60, 61, 62, 63
 225         },
 226
 227         .oobfree = {
 228                 { .offset = 4, .length = 4 },
 229                 { .offset = 20, .length = 4 },
 230                 { .offset = 36, .length = 4 },
 231                 { .offset = 52, .length = 4 }
 232         }
 233 };
 234
 235 /*
 236  * bbt decriptors for chips with on-die ECC and
 237  * chips with 64-byte OOB
 238  */
 239 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 240 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 241
 242 static struct nand_bbt_descr bbt_main_descr = {
 243         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 244                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 245         .offs = 4,
 246         .len = 4,
 247         .veroffs = 20,
 248         .maxblocks = 4,
 249         .pattern = bbt_pattern
 250 };
 251
 252 static struct nand_bbt_descr bbt_mirror_descr = {
 253         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 254                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 255         .offs = 4,
 256         .len = 4,
 257         .veroffs = 20,
 258         .maxblocks = 4,
 259         .pattern = mirror_pattern
 260 };
 261
 262 static u8 buf_data[READ_BUFF_SIZE];
 263 static u32 buf_index;
 264
 265 static struct nand_ecclayout nand_oob;
 266
 267 static void arasan_nand_select_chip(struct mtd_info *mtd, int chip)
 268 {
 269         u32 reg_val;
 270
 271         reg_val = readl(&arasan_nand_base->memadr_reg2);
 272         if (chip == 0) {
 273                 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK;
 274                 writel(reg_val, &arasan_nand_base->memadr_reg2);
 275         } else if (chip == 1) {
 276                 reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK;
 277                 writel(reg_val, &arasan_nand_base->memadr_reg2);
 278         }
 279 }
 280
 281 static void arasan_nand_enable_ecc(void)
 282 {
 283         u32 reg_val;
 284
 285         reg_val = readl(&arasan_nand_base->cmd_reg);
 286         reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK;
 287
 288         writel(reg_val, &arasan_nand_base->cmd_reg);
 289 }
 290
 291 static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
 292 {
 293         u8 addrcycles;
 294         struct nand_chip *chip = mtd_to_nand(mtd);
 295
 296         switch (curr_cmd->addr_cycles) {
 297         case NAND_ADDR_CYCL_NONE:
 298                 addrcycles = 0;
 299                 break;
 300         case NAND_ADDR_CYCL_ONE:
 301                 addrcycles = 1;
 302                 break;
 303         case NAND_ADDR_CYCL_ROW:
 304                 addrcycles = chip->onfi_params.addr_cycles &
 305                              ARASAN_NAND_ROW_ADDR_CYCL_MASK;
 306                 break;
 307         case NAND_ADDR_CYCL_COL:
 308                 addrcycles = (chip->onfi_params.addr_cycles &
 309                               ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
 310                               ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
 311                 break;
 312         case NAND_ADDR_CYCL_BOTH:
 313                 addrcycles = chip->onfi_params.addr_cycles &
 314                              ARASAN_NAND_ROW_ADDR_CYCL_MASK;
 315                 addrcycles += (chip->onfi_params.addr_cycles &
 316                                ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
 317                                ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
 318                 break;
 319         default:
 320                 addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL;
 321                 break;
 322         }
 323         return addrcycles;
 324 }
 325
 326 static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 327 {
 328         struct nand_chip *chip = mtd_to_nand(mtd);
 329         struct nand_config *nand = nand_get_controller_data(chip);
 330         u32 reg_val, i, pktsize, pktnum;
 331         u32 *bufptr = (u32 *)buf;
 332         u32 timeout;
 333         u32  rdcount = 0;
 334         u8 addr_cycles;
 335
 336         if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
 337                 pktsize = ARASAN_NAND_PKTSIZE_1K;
 338         else
 339                 pktsize = ARASAN_NAND_PKTSIZE_512;
 340
 341         if (size % pktsize)
 342                 pktnum = size/pktsize + 1;
 343         else
 344                 pktnum = size/pktsize;
 345
 346         reg_val = readl(&arasan_nand_base->intsts_enr);
 347         reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK |
 348                    ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK;
 349         writel(reg_val, &arasan_nand_base->intsts_enr);
 350
 351         reg_val = readl(&arasan_nand_base->pkt_reg);
 352         reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 353                      ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 354         reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) |
 355                     pktsize;
 356         writel(reg_val, &arasan_nand_base->pkt_reg);
 357
 358         if (!nand->on_die_ecc_enabled) {
 359                 arasan_nand_enable_ecc();
 360                 addr_cycles = arasan_nand_get_addrcycle(mtd);
 361                 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
 362                         return ERR_ADDR_CYCLE;
 363
 364                 writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
 365                        NAND_CMD_RNDOUT | (addr_cycles <<
 366                        ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
 367                        &arasan_nand_base->ecc_sprcmd_reg);
 368         }
 369         writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
 370
 371         while (rdcount < pktnum) {
 372                 timeout = ARASAN_NAND_POLL_TIMEOUT;
 373                 while (!(readl(&arasan_nand_base->intsts_reg) &
 374                         ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
 375                         udelay(1);
 376                         timeout--;
 377                 }
 378                 if (!timeout) {
 379                         puts("arasan_read_page: timedout:Buff RDY\n");
 380                         return -ETIMEDOUT;
 381                 }
 382
 383                 rdcount++;
 384
 385                 if (pktnum == rdcount) {
 386                         reg_val = readl(&arasan_nand_base->intsts_enr);
 387                         reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
 388                         writel(reg_val, &arasan_nand_base->intsts_enr);
 389                 } else {
 390                         reg_val = readl(&arasan_nand_base->intsts_enr);
 391                         writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
 392                                &arasan_nand_base->intsts_enr);
 393                 }
 394                 reg_val = readl(&arasan_nand_base->intsts_reg);
 395                 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
 396                        &arasan_nand_base->intsts_reg);
 397
 398                 for (i = 0; i < pktsize/4; i++)
 399                         bufptr[i] = readl(&arasan_nand_base->buf_dataport);
 400
 401
 402                 bufptr += pktsize/4;
 403
 404                 if (rdcount >= pktnum)
 405                         break;
 406
 407                 writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
 408                        &arasan_nand_base->intsts_enr);
 409         }
 410
 411         timeout = ARASAN_NAND_POLL_TIMEOUT;
 412
 413         while (!(readl(&arasan_nand_base->intsts_reg) &
 414                 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 415                 udelay(1);
 416                 timeout--;
 417         }
 418         if (!timeout) {
 419                 puts("arasan rd_page timedout:Xfer CMPLT\n");
 420                 return -ETIMEDOUT;
 421         }
 422
 423         reg_val = readl(&arasan_nand_base->intsts_enr);
 424         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 425                &arasan_nand_base->intsts_enr);
 426         reg_val = readl(&arasan_nand_base->intsts_reg);
 427         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 428                &arasan_nand_base->intsts_reg);
 429
 430         if (!nand->on_die_ecc_enabled) {
 431                 if (readl(&arasan_nand_base->intsts_reg) &
 432                     ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
 433                         printf("arasan rd_page:sbiterror\n");
 434                         return -1;
 435                 }
 436
 437                 if (readl(&arasan_nand_base->intsts_reg) &
 438                     ARASAN_NAND_INT_STS_ERR_EN_MASK) {
 439                         mtd->ecc_stats.failed++;
 440                         printf("arasan rd_page:multibiterror\n");
 441                         return -1;
 442                 }
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int arasan_nand_read_page_hwecc(struct mtd_info *mtd,
 449                 struct nand_chip *chip, u8 *buf, int oob_required, int page)
 450 {
 451         int status;
 452
 453         status = arasan_nand_read_page(mtd, buf, (mtd->writesize));
 454
 455         if (oob_required)
 456                 chip->ecc.read_oob(mtd, chip, page);
 457
 458         return status;
 459 }
 460
 461 static void arasan_nand_fill_tx(const u8 *buf, int len)
 462 {
 463         u32 __iomem *nand = &arasan_nand_base->buf_dataport;
 464
 465         if (((unsigned long)buf & 0x3) != 0) {
 466                 if (((unsigned long)buf & 0x1) != 0) {
 467                         if (len) {
 468                                 writeb(*buf, nand);
 469                                 buf += 1;
 470                                 len--;
 471                         }
 472                 }
 473
 474                 if (((unsigned long)buf & 0x3) != 0) {
 475                         if (len >= 2) {
 476                                 writew(*(u16 *)buf, nand);
 477                                 buf += 2;
 478                                 len -= 2;
 479                         }
 480                 }
 481         }
 482
 483         while (len >= 4) {
 484                 writel(*(u32 *)buf, nand);
 485                 buf += 4;
 486                 len -= 4;
 487         }
 488
 489         if (len) {
 490                 if (len >= 2) {
 491                         writew(*(u16 *)buf, nand);
 492                         buf += 2;
 493                         len -= 2;
 494                 }
 495
 496                 if (len)
 497                         writeb(*buf, nand);
 498         }
 499 }
 500
 501 static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
 502                 struct nand_chip *chip, const u8 *buf, int oob_required,
 503                 int page)
 504 {
 505         u32 reg_val, i, pktsize, pktnum;
 506         const u32 *bufptr = (const u32 *)buf;
 507         u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 508         u32 size = mtd->writesize;
 509         u32 rdcount = 0;
 510         u8 column_addr_cycles;
 511         struct nand_config *nand = nand_get_controller_data(chip);
 512
 513         if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
 514                 pktsize = ARASAN_NAND_PKTSIZE_1K;
 515         else
 516                 pktsize = ARASAN_NAND_PKTSIZE_512;
 517
 518         if (size % pktsize)
 519                 pktnum = size/pktsize + 1;
 520         else
 521                 pktnum = size/pktsize;
 522
 523         reg_val = readl(&arasan_nand_base->pkt_reg);
 524         reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 525                      ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 526         reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize;
 527         writel(reg_val, &arasan_nand_base->pkt_reg);
 528
 529         if (!nand->on_die_ecc_enabled) {
 530                 arasan_nand_enable_ecc();
 531                 column_addr_cycles = (chip->onfi_params.addr_cycles &
 532                                       ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
 533                                       ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
 534                 writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
 535                        &arasan_nand_base->ecc_sprcmd_reg);
 536         }
 537         writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
 538
 539         while (rdcount < pktnum) {
 540                 timeout = ARASAN_NAND_POLL_TIMEOUT;
 541                 while (!(readl(&arasan_nand_base->intsts_reg) &
 542                         ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
 543                         udelay(1);
 544                         timeout--;
 545                 }
 546
 547                 if (!timeout) {
 548                         puts("arasan_write_page: timedout:Buff RDY\n");
 549                         return -ETIMEDOUT;
 550                 }
 551
 552                 rdcount++;
 553
 554                 if (pktnum == rdcount) {
 555                         reg_val = readl(&arasan_nand_base->intsts_enr);
 556                         reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
 557                         writel(reg_val, &arasan_nand_base->intsts_enr);
 558                 } else {
 559                         reg_val = readl(&arasan_nand_base->intsts_enr);
 560                         writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
 561                                &arasan_nand_base->intsts_enr);
 562                 }
 563
 564                 reg_val = readl(&arasan_nand_base->intsts_reg);
 565                 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
 566                        &arasan_nand_base->intsts_reg);
 567
 568                 for (i = 0; i < pktsize/4; i++)
 569                         writel(bufptr[i], &arasan_nand_base->buf_dataport);
 570
 571                 bufptr += pktsize/4;
 572
 573                 if (rdcount >= pktnum)
 574                         break;
 575
 576                 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
 577                        &arasan_nand_base->intsts_enr);
 578         }
 579
 580         timeout = ARASAN_NAND_POLL_TIMEOUT;
 581
 582         while (!(readl(&arasan_nand_base->intsts_reg) &
 583                 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 584                 udelay(1);
 585                 timeout--;
 586         }
 587         if (!timeout) {
 588                 puts("arasan write_page timedout:Xfer CMPLT\n");
 589                 return -ETIMEDOUT;
 590         }
 591
 592         reg_val = readl(&arasan_nand_base->intsts_enr);
 593         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 594                &arasan_nand_base->intsts_enr);
 595         reg_val = readl(&arasan_nand_base->intsts_reg);
 596         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 597                &arasan_nand_base->intsts_reg);
 598
 599         if (oob_required)
 600                 chip->ecc.write_oob(mtd, chip, nand->page);
 601
 602         return 0;
 603 }
 604
 605 static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 606                                 int page)
 607 {
 608         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 609         chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize));
 610
 611         return 0;
 612 }
 613
 614 static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 615                                  int page)
 616 {
 617         int status = 0;
 618         const u8 *buf = chip->oob_poi;
 619
 620         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 621         chip->write_buf(mtd, buf, mtd->oobsize);
 622
 623         return status;
 624 }
 625
 626 static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd)
 627 {
 628         u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 629         u32 cmd_reg = 0;
 630
 631         writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 632                &arasan_nand_base->intsts_enr);
 633         cmd_reg = readl(&arasan_nand_base->cmd_reg);
 634         cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK;
 635
 636         cmd_reg |= curr_cmd->cmd1 |
 637                   (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
 638         writel(cmd_reg, &arasan_nand_base->cmd_reg);
 639         writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
 640
 641         while (!(readl(&arasan_nand_base->intsts_reg) &
 642                 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 643                 udelay(1);
 644                 timeout--;
 645         }
 646         if (!timeout) {
 647                 printf("ERROR:%s timedout\n", __func__);
 648                 return -ETIMEDOUT;
 649         }
 650
 651         writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 652                &arasan_nand_base->intsts_enr);
 653
 654         writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 655                &arasan_nand_base->intsts_reg);
 656
 657         return 0;
 658 }
 659
 660 static u8 arasan_nand_page(struct mtd_info *mtd)
 661 {
 662         u8 page_val = 0;
 663
 664         switch (mtd->writesize) {
 665         case 512:
 666                 page_val = 0;
 667                 break;
 668         case 2048:
 669                 page_val = 1;
 670                 break;
 671         case 4096:
 672                 page_val = 2;
 673                 break;
 674         case 8192:
 675                 page_val = 3;
 676                 break;
 677         case 16384:
 678                 page_val = 4;
 679                 break;
 680         case 1024:
 681                 page_val = 5;
 682                 break;
 683         default:
 684                 printf("%s:Pagesize>16K\n", __func__);
 685                 break;
 686         }
 687
 688         return page_val;
 689 }
 690
 691 static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
 692                         int column, int page_addr, struct mtd_info *mtd)
 693 {
 694         u32 reg_val, page;
 695         u8 page_val, addr_cycles;
 696
 697         writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
 698                &arasan_nand_base->intsts_enr);
 699         reg_val = readl(&arasan_nand_base->cmd_reg);
 700         reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
 701         reg_val |= curr_cmd->cmd1 |
 702                    (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
 703         if (curr_cmd->cmd1 == NAND_CMD_SEQIN) {
 704                 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
 705                 page_val = arasan_nand_page(mtd);
 706                 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
 707         }
 708
 709         reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
 710         addr_cycles = arasan_nand_get_addrcycle(mtd);
 711
 712         if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
 713                 return ERR_ADDR_CYCLE;
 714
 715         reg_val |= (addr_cycles <<
 716                    ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
 717         writel(reg_val, &arasan_nand_base->cmd_reg);
 718
 719         if (page_addr == -1)
 720                 page_addr = 0;
 721
 722         page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
 723                 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
 724         column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
 725         writel(page|column, &arasan_nand_base->memadr_reg1);
 726
 727         reg_val = readl(&arasan_nand_base->memadr_reg2);
 728         reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
 729         reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
 730         writel(reg_val, &arasan_nand_base->memadr_reg2);
 731
 732         return 0;
 733 }
 734
 735 static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 736 {
 737         u32 reg_val;
 738         u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 739
 740         reg_val = readl(&arasan_nand_base->pkt_reg);
 741         reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 742                      ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 743
 744         reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len;
 745         writel(reg_val, &arasan_nand_base->pkt_reg);
 746         writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
 747
 748         while (!(readl(&arasan_nand_base->intsts_reg) &
 749                 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
 750                 udelay(1);
 751                 timeout--;
 752         }
 753
 754         if (!timeout)
 755                 puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
 756
 757         reg_val = readl(&arasan_nand_base->intsts_enr);
 758         reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
 759         writel(reg_val, &arasan_nand_base->intsts_enr);
 760         writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
 761                &arasan_nand_base->intsts_enr);
 762         reg_val = readl(&arasan_nand_base->intsts_reg);
 763         writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
 764                &arasan_nand_base->intsts_reg);
 765
 766         arasan_nand_fill_tx(buf, len);
 767
 768         timeout = ARASAN_NAND_POLL_TIMEOUT;
 769         while (!(readl(&arasan_nand_base->intsts_reg) &
 770                 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 771                 udelay(1);
 772                 timeout--;
 773         }
 774         if (!timeout)
 775                 puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
 776
 777         writel(readl(&arasan_nand_base->intsts_enr) |
 778                ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 779                &arasan_nand_base->intsts_enr);
 780         writel(readl(&arasan_nand_base->intsts_reg) |
 781                ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 782                &arasan_nand_base->intsts_reg);
 783 }
 784
 785 static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 786                               int column, int page_addr, struct mtd_info *mtd)
 787 {
 788         u32 reg_val, page;
 789         u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 790         u8 row_addr_cycles;
 791
 792         writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 793                &arasan_nand_base->intsts_enr);
 794         reg_val = readl(&arasan_nand_base->cmd_reg);
 795         reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
 796         reg_val |= curr_cmd->cmd1 |
 797                    (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
 798         row_addr_cycles = arasan_nand_get_addrcycle(mtd);
 799
 800         if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
 801                 return ERR_ADDR_CYCLE;
 802
 803         reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
 804         reg_val |= (row_addr_cycles <<
 805                     ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
 806
 807         writel(reg_val, &arasan_nand_base->cmd_reg);
 808
 809         page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
 810                 ARASAN_NAND_MEM_ADDR1_COL_MASK;
 811         column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
 812         writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
 813                &arasan_nand_base->memadr_reg1);
 814
 815         reg_val = readl(&arasan_nand_base->memadr_reg2);
 816         reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
 817         reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
 818         writel(reg_val, &arasan_nand_base->memadr_reg2);
 819         writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
 820
 821         while (!(readl(&arasan_nand_base->intsts_reg) &
 822                 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 823                 udelay(1);
 824                 timeout--;
 825         }
 826         if (!timeout) {
 827                 printf("ERROR:%s timedout:Xfer CMPLT\n", __func__);
 828                 return -ETIMEDOUT;
 829         }
 830
 831         reg_val = readl(&arasan_nand_base->intsts_enr);
 832         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 833                &arasan_nand_base->intsts_enr);
 834         reg_val = readl(&arasan_nand_base->intsts_reg);
 835         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 836                &arasan_nand_base->intsts_reg);
 837
 838         return 0;
 839 }
 840
 841 static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
 842                                 int column, int page_addr, struct mtd_info *mtd)
 843 {
 844         u32 reg_val;
 845         u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 846         u8 addr_cycles;
 847
 848         writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 849                &arasan_nand_base->intsts_enr);
 850         reg_val = readl(&arasan_nand_base->cmd_reg);
 851         reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
 852         reg_val |= curr_cmd->cmd1 |
 853                    (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
 854         addr_cycles = arasan_nand_get_addrcycle(mtd);
 855
 856         if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
 857                 return ERR_ADDR_CYCLE;
 858
 859         reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
 860         reg_val |= (addr_cycles <<
 861                     ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
 862
 863         writel(reg_val, &arasan_nand_base->cmd_reg);
 864
 865         reg_val = readl(&arasan_nand_base->pkt_reg);
 866         reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 867                      ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 868         reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1;
 869         writel(reg_val, &arasan_nand_base->pkt_reg);
 870
 871         writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
 872         while (!(readl(&arasan_nand_base->intsts_reg) &
 873                 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 874                 udelay(1);
 875                 timeout--;
 876         }
 877
 878         if (!timeout) {
 879                 printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__);
 880                 return -ETIMEDOUT;
 881         }
 882
 883         reg_val = readl(&arasan_nand_base->intsts_enr);
 884         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 885                &arasan_nand_base->intsts_enr);
 886         reg_val = readl(&arasan_nand_base->intsts_reg);
 887         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 888                &arasan_nand_base->intsts_reg);
 889
 890         return 0;
 891 }
 892
 893 static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
 894                                int column, int page_addr, struct mtd_info *mtd)
 895 {
 896         u32 reg_val, addr_cycles, page;
 897         u8 page_val;
 898
 899         reg_val = readl(&arasan_nand_base->intsts_enr);
 900         writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
 901                &arasan_nand_base->intsts_enr);
 902
 903         reg_val = readl(&arasan_nand_base->cmd_reg);
 904         reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
 905         reg_val |= curr_cmd->cmd1 |
 906                    (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
 907
 908         if (curr_cmd->cmd1 == NAND_CMD_RNDOUT ||
 909             curr_cmd->cmd1 == NAND_CMD_READ0) {
 910                 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
 911                 page_val = arasan_nand_page(mtd);
 912                 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
 913         }
 914
 915         reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK;
 916
 917         reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
 918
 919         addr_cycles = arasan_nand_get_addrcycle(mtd);
 920
 921         if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
 922                 return ERR_ADDR_CYCLE;
 923
 924         reg_val |= (addr_cycles << 28);
 925         writel(reg_val, &arasan_nand_base->cmd_reg);
 926
 927         if (page_addr == -1)
 928                 page_addr = 0;
 929
 930         page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
 931                 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
 932         column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
 933         writel(page | column, &arasan_nand_base->memadr_reg1);
 934
 935         reg_val = readl(&arasan_nand_base->memadr_reg2);
 936         reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
 937         reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
 938         writel(reg_val, &arasan_nand_base->memadr_reg2);
 939
 940         buf_index = 0;
 941
 942         return 0;
 943 }
 944
 945 static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
 946 {
 947         u32 reg_val, i;
 948         u32 *bufptr = (u32 *)buf;
 949         u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 950
 951         reg_val = readl(&arasan_nand_base->pkt_reg);
 952         reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 953                      ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 954         reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size;
 955         writel(reg_val, &arasan_nand_base->pkt_reg);
 956
 957         writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
 958
 959         while (!(readl(&arasan_nand_base->intsts_reg) &
 960                 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
 961                 udelay(1);
 962                 timeout--;
 963         }
 964
 965         if (!timeout)
 966                 puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
 967
 968         reg_val = readl(&arasan_nand_base->intsts_enr);
 969         reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
 970         writel(reg_val, &arasan_nand_base->intsts_enr);
 971
 972         writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
 973                &arasan_nand_base->intsts_enr);
 974         reg_val = readl(&arasan_nand_base->intsts_reg);
 975         writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
 976                &arasan_nand_base->intsts_reg);
 977
 978         buf_index = 0;
 979         for (i = 0; i < size / 4; i++)
 980                 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
 981
 982         if (size & 0x03)
 983                 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
 984
 985         timeout = ARASAN_NAND_POLL_TIMEOUT;
 986
 987         while (!(readl(&arasan_nand_base->intsts_reg) &
 988                 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 989                 udelay(1);
 990                 timeout--;
 991         }
 992
 993         if (!timeout)
 994                 puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
 995
 996         reg_val = readl(&arasan_nand_base->intsts_enr);
 997         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
 998                &arasan_nand_base->intsts_enr);
 999         reg_val = readl(&arasan_nand_base->intsts_reg);
1000         writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
1001                &arasan_nand_base->intsts_reg);
1002 }
1003
1004 static u8 arasan_nand_read_byte(struct mtd_info *mtd)
1005 {
1006         struct nand_chip *chip = mtd_to_nand(mtd);
1007         u32 size;
1008         u8 val;
1009         struct nand_onfi_params *p;
1010
1011         if (buf_index == 0) {
1012                 p = &chip->onfi_params;
1013                 if (curr_cmd->cmd1 == NAND_CMD_READID)
1014                         size = 4;
1015                 else if (curr_cmd->cmd1 == NAND_CMD_PARAM)
1016                         size = sizeof(struct nand_onfi_params);
1017                 else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT)
1018                         size = le16_to_cpu(p->ext_param_page_length) * 16;
1019                 else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES)
1020                         size = 4;
1021                 else if (curr_cmd->cmd1 == NAND_CMD_STATUS)
1022                         return readb(&arasan_nand_base->flash_sts_reg);
1023                 else
1024                         size = 8;
1025                 chip->read_buf(mtd, &buf_data[0], size);
1026         }
1027
1028         val = *(&buf_data[0] + buf_index);
1029         buf_index++;
1030
1031         return val;
1032 }
1033
1034 static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
1035                                      int column, int page_addr)
1036 {
1037         u32 i, ret = 0;
1038         struct nand_chip *chip = mtd_to_nand(mtd);
1039         struct nand_config *nand = nand_get_controller_data(chip);
1040
1041         curr_cmd = NULL;
1042         writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
1043                &arasan_nand_base->intsts_enr);
1044
1045         if ((command == NAND_CMD_READOOB) &&
1046             (mtd->writesize > 512)) {
1047                 column += mtd->writesize;
1048                 command = NAND_CMD_READ0;
1049         }
1050
1051         /* Get the command format */
1052         for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE ||
1053                      arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) {
1054                 if (command == arasan_nand_commands[i].cmd1) {
1055                         curr_cmd = &arasan_nand_commands[i];
1056                         break;
1057                 }
1058         }
1059
1060         if (curr_cmd == NULL) {
1061                 printf("Unsupported Command; 0x%x\n", command);
1062                 return;
1063         }
1064
1065         if (curr_cmd->cmd1 == NAND_CMD_RESET)
1066                 ret = arasan_nand_reset(curr_cmd);
1067
1068         if ((curr_cmd->cmd1 == NAND_CMD_READID) ||
1069             (curr_cmd->cmd1 == NAND_CMD_PARAM) ||
1070             (curr_cmd->cmd1 == NAND_CMD_RNDOUT) ||
1071             (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) ||
1072             (curr_cmd->cmd1 == NAND_CMD_READ0))
1073                 ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd);
1074
1075         if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) ||
1076             (curr_cmd->cmd1 == NAND_CMD_SEQIN)) {
1077                 nand->page = page_addr;
1078                 ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd);
1079         }
1080
1081         if (curr_cmd->cmd1 == NAND_CMD_ERASE1)
1082                 ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd);
1083
1084         if (curr_cmd->cmd1 == NAND_CMD_STATUS)
1085                 ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd);
1086
1087         if (ret != 0)
1088                 printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1);
1089 }
1090
1091 static void arasan_check_ondie(struct mtd_info *mtd)
1092 {
1093         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1094         struct nand_config *nand = nand_get_controller_data(nand_chip);
1095         u8 maf_id, dev_id;
1096         u8 get_feature[4];
1097         u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
1098         u32 i;
1099
1100         /* Send the command for reading device ID */
1101         nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1102         nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
1103
1104         /* Read manufacturer and device IDs */
1105         maf_id = nand_chip->read_byte(mtd);
1106         dev_id = nand_chip->read_byte(mtd);
1107
1108         if ((maf_id == NAND_MFR_MICRON) &&
1109             ((dev_id == 0xf1) || (dev_id == 0xa1) || (dev_id == 0xb1) ||
1110              (dev_id == 0xaa) || (dev_id == 0xba) || (dev_id == 0xda) ||
1111              (dev_id == 0xca) || (dev_id == 0xac) || (dev_id == 0xbc) ||
1112              (dev_id == 0xdc) || (dev_id == 0xcc) || (dev_id == 0xa3) ||
1113              (dev_id == 0xb3) || (dev_id == 0xd3) || (dev_id == 0xc3))) {
1114                 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1115                                    ONDIE_ECC_FEATURE_ADDR, -1);
1116
1117                 nand_chip->write_buf(mtd, &set_feature[0], 4);
1118                 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1119                                    ONDIE_ECC_FEATURE_ADDR, -1);
1120
1121                 for (i = 0; i < 4; i++)
1122                         get_feature[i] = nand_chip->read_byte(mtd);
1123
1124                 if (get_feature[0] & ENABLE_ONDIE_ECC)
1125                         nand->on_die_ecc_enabled = true;
1126                 else
1127                         printf("%s: Unable to enable OnDie ECC\n", __func__);
1128
1129                 /* Use the BBT pattern descriptors */
1130                 nand_chip->bbt_td = &bbt_main_descr;
1131                 nand_chip->bbt_md = &bbt_mirror_descr;
1132         }
1133 }
1134
1135 static int arasan_nand_ecc_init(struct mtd_info *mtd)
1136 {
1137         int found = -1;
1138         u32 regval, eccpos_start, i, eccaddr;
1139         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1140
1141         for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) {
1142                 if ((ecc_matrix[i].pagesize == mtd->writesize) &&
1143                     (ecc_matrix[i].ecc_codeword_size >=
1144                      nand_chip->ecc_step_ds)) {
1145                         if (ecc_matrix[i].eccbits >=
1146                             nand_chip->ecc_strength_ds) {
1147                                 found = i;
1148                                 break;
1149                         }
1150                         found = i;
1151                 }
1152         }
1153
1154         if (found < 0)
1155                 return 1;
1156
1157         eccaddr = mtd->writesize + mtd->oobsize -
1158                   ecc_matrix[found].eccsize;
1159
1160         regval = eccaddr |
1161                  (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
1162                  (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
1163         writel(regval, &arasan_nand_base->ecc_reg);
1164
1165         if (ecc_matrix[found].bch) {
1166                 regval = readl(&arasan_nand_base->memadr_reg2);
1167                 regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
1168                 regval |= (ecc_matrix[found].bchval <<
1169                            ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
1170                 writel(regval, &arasan_nand_base->memadr_reg2);
1171         }
1172
1173         nand_oob.eccbytes = ecc_matrix[found].eccsize;
1174         eccpos_start = mtd->oobsize - nand_oob.eccbytes;
1175
1176         for (i = 0; i < nand_oob.eccbytes; i++)
1177                 nand_oob.eccpos[i] = eccpos_start + i;
1178
1179         nand_oob.oobfree[0].offset = 2;
1180         nand_oob.oobfree[0].length = eccpos_start - 2;
1181
1182         nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
1183         nand_chip->ecc.strength = ecc_matrix[found].eccbits;
1184         nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
1185         nand_chip->ecc.layout = &nand_oob;
1186
1187         return 0;
1188 }
1189
1190 static int arasan_probe(struct udevice *dev)
1191 {
1192         struct arasan_nand_info *arasan = dev_get_priv(dev);
1193         struct nand_chip *nand_chip = &arasan->nand_chip;
1194         struct nand_config *nand;
1195         struct mtd_info *mtd;
1196         int err = -1;
1197
1198         nand = calloc(1, sizeof(struct nand_config));
1199         if (!nand) {
1200                 printf("%s: failed to allocate\n", __func__);
1201                 return err;
1202         }
1203
1204         mtd = nand_to_mtd(nand_chip);
1205         nand_set_controller_data(nand_chip, nand);
1206
1207 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
1208         nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1209 #endif
1210
1211         /* Set the driver entry points for MTD */
1212         nand_chip->cmdfunc = arasan_nand_cmd_function;
1213         nand_chip->select_chip = arasan_nand_select_chip;
1214         nand_chip->read_byte = arasan_nand_read_byte;
1215
1216         /* Buffer read/write routines */
1217         nand_chip->read_buf = arasan_nand_read_buf;
1218         nand_chip->write_buf = arasan_nand_write_buf;
1219         nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1220
1221         writel(0x0, &arasan_nand_base->cmd_reg);
1222         writel(0x0, &arasan_nand_base->pgm_reg);
1223
1224         /* first scan to find the device and get the page size */
1225         if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) {
1226                 printf("%s: nand_scan_ident failed\n", __func__);
1227                 goto fail;
1228         }
1229
1230         nand_chip->ecc.mode = NAND_ECC_HW;
1231         nand_chip->ecc.hwctl = NULL;
1232         nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
1233         nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
1234         nand_chip->ecc.read_oob = arasan_nand_read_oob;
1235         nand_chip->ecc.write_oob = arasan_nand_write_oob;
1236
1237         arasan_check_ondie(mtd);
1238
1239         /*
1240          * If on die supported, then give priority to on-die ecc and use
1241          * it instead of controller ecc.
1242          */
1243         if (nand->on_die_ecc_enabled) {
1244                 nand_chip->ecc.strength = 1;
1245                 nand_chip->ecc.size = mtd->writesize;
1246                 nand_chip->ecc.bytes = 0;
1247                 nand_chip->ecc.layout = &ondie_nand_oob_64;
1248         } else {
1249                 if (arasan_nand_ecc_init(mtd)) {
1250                         printf("%s: nand_ecc_init failed\n", __func__);
1251                         goto fail;
1252                 }
1253         }
1254
1255         if (nand_scan_tail(mtd)) {
1256                 printf("%s: nand_scan_tail failed\n", __func__);
1257                 goto fail;
1258         }
1259
1260         if (nand_register(0, mtd)) {
1261                 printf("Nand Register Fail\n");
1262                 goto fail;
1263         }
1264
1265         return 0;
1266 fail:
1267         free(nand);
1268         return err;
1269 }
1270
1271 static const struct udevice_id arasan_nand_dt_ids[] = {
1272         {.compatible = "arasan,nfc-v3p10",},
1273         { /* sentinel */ }
1274 };
1275
1276 U_BOOT_DRIVER(arasan_nand) = {
1277         .name = "arasan-nand",
1278         .id = UCLASS_MTD,
1279         .of_match = arasan_nand_dt_ids,
1280         .probe = arasan_probe,
1281         .priv_auto_alloc_size = sizeof(struct arasan_nand_info),
1282 };
1283
1284 void board_nand_init(void)
1285 {
1286         struct udevice *dev;
1287         int ret;
1288
1289         ret = uclass_get_device_by_driver(UCLASS_MTD,
1290                                           DM_GET_DRIVER(arasan_nand), &dev);
1291         if (ret && ret != -ENODEV)
1292                 pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
1293 }