2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SPL_SYS_NAND_SELF_INIT
14 depends on !SPL_NAND_SIMPLE
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
19 config TPL_SYS_NAND_SELF_INIT
21 depends on TPL_NAND_SUPPORT
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
29 config SYS_MAX_NAND_DEVICE
30 int "Maximum number of NAND devices to support"
33 config SYS_NAND_DRIVER_ECC_LAYOUT
34 bool "Omit standard ECC layouts to save space"
36 Omit standard ECC layouts to save space. Select this if your driver
37 is known to provide its own ECC layout.
39 config SYS_NAND_USE_FLASH_BBT
40 bool "Enable BBT (Bad Block Table) support"
42 Enable the BBT (Bad Block Table) usage.
45 bool "Support Atmel NAND controller"
46 select SYS_NAND_SELF_INIT
47 imply SYS_NAND_USE_FLASH_BBT
49 Enable this driver for NAND flash platforms using an Atmel NAND
54 config ATMEL_NAND_HWECC
55 bool "Atmel Hardware ECC"
57 config ATMEL_NAND_HW_PMECC
58 bool "Atmel Programmable Multibit ECC (PMECC)"
59 select ATMEL_NAND_HWECC
61 The Programmable Multibit ECC (PMECC) controller is a programmable
62 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
65 int "PMECC Correctable ECC Bits"
66 depends on ATMEL_NAND_HW_PMECC
69 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
71 config PMECC_SECTOR_SIZE
72 int "PMECC Sector Size"
73 depends on ATMEL_NAND_HW_PMECC
76 Sector size, in bytes, can be 512 or 1024.
78 config SPL_GENERATE_ATMEL_PMECC_HEADER
79 bool "Atmel PMECC Header Generation"
81 select ATMEL_NAND_HWECC
82 select ATMEL_NAND_HW_PMECC
84 Generate Programmable Multibit ECC (PMECC) header for SPL image.
89 bool "Support Broadcom NAND controller"
90 depends on OF_CONTROL && DM && DM_MTD
91 select SYS_NAND_SELF_INIT
93 Enable the driver for NAND flash on platforms using a Broadcom NAND
96 config NAND_BRCMNAND_6368
97 bool "Support Broadcom NAND controller on bcm6368"
98 depends on NAND_BRCMNAND && ARCH_BMIPS
100 Enable support for broadcom nand driver on bcm6368.
102 config NAND_BRCMNAND_6753
103 bool "Support Broadcom NAND controller on bcm6753"
104 depends on NAND_BRCMNAND && BCM6855
106 Enable support for broadcom nand driver on bcm6753.
108 config NAND_BRCMNAND_68360
109 bool "Support Broadcom NAND controller on bcm68360"
110 depends on NAND_BRCMNAND && BCM6856
112 Enable support for broadcom nand driver on bcm68360.
114 config NAND_BRCMNAND_6838
115 bool "Support Broadcom NAND controller on bcm6838"
116 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
118 Enable support for broadcom nand driver on bcm6838.
120 config NAND_BRCMNAND_6858
121 bool "Support Broadcom NAND controller on bcm6858"
122 depends on NAND_BRCMNAND && BCM6858
124 Enable support for broadcom nand driver on bcm6858.
126 config NAND_BRCMNAND_63158
127 bool "Support Broadcom NAND controller on bcm63158"
128 depends on NAND_BRCMNAND && BCM63158
130 Enable support for broadcom nand driver on bcm63158.
133 bool "Support TI Davinci NAND controller"
134 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
136 Enable this driver for NAND flash controllers available in TI Davinci
137 and Keystone2 platforms
139 config SYS_NAND_4BIT_HW_ECC_OOBFIRST
140 bool "Use 4-bit HW ECC with OOB at the front"
141 depends on NAND_DAVINCI
143 config KEYSTONE_RBL_NAND
144 depends on ARCH_KEYSTONE
149 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
153 select SYS_NAND_SELF_INIT
156 config NAND_DENALI_DT
157 bool "Support Denali NAND controller as a DT device"
159 depends on OF_CONTROL && DM_MTD
161 Enable the driver for NAND flash on platforms using a Denali NAND
162 controller as a DT device.
165 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
166 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
167 select SPL_SYS_NAND_SELF_INIT
168 select SYS_NAND_SELF_INIT
171 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
173 config NAND_FSL_ELBC_DT
174 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
175 depends on NAND_FSL_ELBC
178 bool "Support Freescale Integrated Flash Controller NAND driver"
179 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
180 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
181 select SPL_SYS_NAND_SELF_INIT
182 select SYS_NAND_SELF_INIT
185 Enable the Freescale Integrated Flash Controller NAND driver.
187 config NAND_LPC32XX_MLC
188 bool "Support LPC32XX_MLC controller"
189 select SYS_NAND_SELF_INIT
191 Enable the LPC32XX MLC NAND controller.
193 config NAND_LPC32XX_SLC
194 bool "Support LPC32XX_SLC controller"
196 Enable the LPC32XX SLC NAND controller.
198 config NAND_OMAP_GPMC
199 bool "Support OMAP GPMC NAND controller"
200 depends on ARCH_OMAP2PLUS
202 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
203 GPMC controller is used for parallel NAND flash devices, and can
204 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
205 and BCH16 ECC algorithms.
209 config NAND_OMAP_GPMC_PREFETCH
210 bool "Enable GPMC Prefetch"
213 On OMAP platforms that use the GPMC controller
214 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
215 uses the prefetch mode to speed up read operations.
218 bool "Enable ELM driver for OMAPxx and AMxx platforms."
221 ELM controller is used for ECC error detection (not ECC calculation)
222 of BCH4, BCH8 and BCH16 ECC algorithms.
223 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
224 thus such SoC platforms need to depend on software library for ECC error
225 detection. However ECC calculation on such plaforms would still be
226 done by GPMC controller.
230 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
232 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
233 It can take following values:
234 OMAP_ECC_HAM1_CODE_SW
235 1-bit Hamming code using software lib.
236 (for legacy devices only)
237 OMAP_ECC_HAM1_CODE_HW
238 1-bit Hamming code using GPMC hardware.
239 (for legacy devices only)
240 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
241 4-bit BCH code (unsupported)
242 OMAP_ECC_BCH4_CODE_HW
243 4-bit BCH code (unsupported)
244 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
246 - ecc calculation using GPMC hardware engine,
247 - error detection using software library.
248 - requires CONFIG_BCH to enable software BCH library
249 (For legacy device which do not have ELM h/w engine)
250 OMAP_ECC_BCH8_CODE_HW
252 - ecc calculation using GPMC hardware engine,
253 - error detection using ELM hardware engine.
254 OMAP_ECC_BCH16_CODE_HW
256 - ecc calculation using GPMC hardware engine,
257 - error detection using ELM hardware engine.
259 How to select ECC scheme on OMAP and AMxx platforms ?
260 -----------------------------------------------------
261 Though higher ECC schemes have more capability to detect and correct
262 bit-flips, but still selection of ECC scheme is dependent on following
263 - hardware engines present in SoC.
264 Some legacy OMAP SoC do not have ELM h/w engine thus such
265 SoC cannot support BCHx_HW ECC schemes.
266 - size of OOB/Spare region
267 With higher ECC schemes, more OOB/Spare area is required to
268 store ECC. So choice of ECC scheme is limited by NAND oobsize.
270 In general following expression can help:
271 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
273 NAND_OOBSIZE = number of bytes available in
274 OOB/spare area per NAND page.
275 NAND_PAGESIZE = bytes in main-area of NAND page.
276 ECC_BYTES = number of ECC bytes generated to
277 protect 512 bytes of data, which is:
278 3 for HAM1_xx ecc schemes
279 7 for BCH4_xx ecc schemes
280 14 for BCH8_xx ecc schemes
281 26 for BCH16_xx ecc schemes
283 example to check for BCH16 on 2K page NAND
286 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
287 Thus BCH16 cannot be supported on 2K page NAND.
289 However, for 4K pagesize NAND
293 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
294 Thus BCH16 can be supported on 4K page NAND.
296 config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
297 bool "1-bit Hamming code using software lib"
299 config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
300 bool "1-bit Hamming code using GPMC hardware"
302 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
303 bool "8-bit BCH code with HW calculation SW error detection"
305 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
306 bool "8-bit BCH code with HW calculation and error detection"
308 config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
309 bool "16-bit BCH code with HW calculation and error detection"
313 config NAND_OMAP_ECCSCHEME
315 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
316 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
317 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
318 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
319 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
321 This must be kept in sync with the enum in
322 include/linux/mtd/omap_gpmc.h
326 config NAND_VF610_NFC
327 bool "Support for Freescale NFC for VF610"
328 select SYS_NAND_SELF_INIT
329 select SYS_NAND_DRIVER_ECC_LAYOUT
332 Enables support for NAND Flash Controller on some Freescale
333 processors like the VF610, MCF54418 or Kinetis K70.
334 The driver supports a maximum 2k page size. The driver
335 currently does not support hardware ECC.
339 config NAND_VF610_NFC_DT
340 bool "Support Vybrid's vf610 NAND controller as a DT device"
341 depends on OF_CONTROL && DM_MTD
343 Enable the driver for Vybrid's vf610 NAND flash on platforms
347 prompt "Hardware ECC strength"
348 depends on NAND_VF610_NFC
349 default SYS_NAND_VF610_NFC_45_ECC_BYTES
351 Select the ECC strength used in the hardware BCH ECC block.
353 config SYS_NAND_VF610_NFC_45_ECC_BYTES
354 bool "24-error correction (45 ECC bytes)"
356 config SYS_NAND_VF610_NFC_60_ECC_BYTES
357 bool "32-error correction (60 ECC bytes)"
364 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
365 select SYS_NAND_SELF_INIT
371 This enables the driver for the NAND flash device found on
372 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
375 bool "Support for NAND on Allwinner SoCs"
377 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
378 select SYS_NAND_SELF_INIT
379 select SYS_NAND_U_BOOT_LOCATIONS
380 select SPL_NAND_SUPPORT
381 select SPL_SYS_NAND_SELF_INIT
384 Enable support for NAND. This option enables the standard and
386 The SPL driver only supports reading from the NAND using DMA
391 config NAND_SUNXI_SPL_ECC_STRENGTH
392 int "Allwinner NAND SPL ECC Strength"
395 config NAND_SUNXI_SPL_ECC_SIZE
396 int "Allwinner NAND SPL ECC Step Size"
399 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
400 int "Allwinner NAND SPL Usable Page Size"
406 bool "Configure Arasan Nand"
407 select SYS_NAND_SELF_INIT
411 This enables Nand driver support for Arasan nand flash
412 controller. This uses the hardware ECC for read and
416 bool "MXC NAND support"
417 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
420 This enables the NAND driver for the NAND flash controller on the
421 i.MX27 / i.MX31 / i.MX5 processors.
424 bool "MXS NAND support"
425 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
426 select SPL_SYS_NAND_SELF_INIT
427 select SYS_NAND_SELF_INIT
430 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
431 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
433 This enables NAND driver for the NAND flash controller on the
439 bool "Support MXS NAND controller as a DT device"
440 depends on OF_CONTROL && DM_MTD
442 Enable the driver for MXS NAND flash on platforms using
445 config NAND_MXS_USE_MINIMUM_ECC
446 bool "Use minimum ECC strength supported by the controller"
452 bool "Macronix raw NAND controller"
453 select SYS_NAND_SELF_INIT
455 This selects the Macronix raw NAND controller driver.
458 bool "Support for Zynq Nand controller"
459 select SPL_SYS_NAND_SELF_INIT
460 select SYS_NAND_SELF_INIT
464 This enables Nand driver support for Nand flash controller
467 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
468 bool "Enable use of 1st stage bootloader timing for NAND"
471 This flag prevent U-boot reconfigure NAND flash controller and reuse
472 the NAND timing from 1st stage bootloader.
475 bool "Support for OcteonTX NAND controller"
476 select SYS_NAND_SELF_INIT
479 This enables Nand flash controller hardware found on the OcteonTX
482 config NAND_OCTEONTX_HW_ECC
483 bool "Support Hardware ECC for OcteonTX NAND controller"
484 depends on NAND_OCTEONTX
487 This enables Hardware BCH engine found on the OcteonTX processors to
488 support ECC for NAND flash controller.
490 config NAND_STM32_FMC2
491 bool "Support for NAND controller on STM32MP SoCs"
492 depends on ARCH_STM32MP
493 select SYS_NAND_SELF_INIT
496 Enables support for NAND Flash chips on SoCs containing the FMC2
497 NAND controller. This controller is found on STM32MP SoCs.
498 The controller supports a maximum 8k page size and supports
499 a maximum 8-bit correction error per sector of 512 bytes.
502 bool "Support for NAND controller on Cortina-Access SoCs"
503 depends on CORTINA_PLATFORM
504 select SYS_NAND_SELF_INIT
508 Enables support for NAND Flash chips on Coartina-Access SoCs platform
509 This controller is found on Presidio/Venus SoCs.
510 The controller supports a maximum 8k page size and supports
511 a maximum 40-bit error correction per sector of 1024 bytes.
514 bool "Support for NAND controller on Rockchip SoCs"
515 depends on ARCH_ROCKCHIP
516 select SYS_NAND_SELF_INIT
520 Enables support for NAND Flash chips on Rockchip SoCs platform.
521 This controller is found on Rockchip SoCs.
522 There are four different versions of NAND FLASH Controllers,
524 NFC v600: RK2928, RK3066, RK3188
525 NFC v622: RK3036, RK3128
526 NFC v800: RK3308, RV1108
527 NFC v900: PX30, RK3326
530 bool "Support for NAND controller on Tegra SoCs"
531 depends on ARCH_TEGRA
532 select SYS_NAND_SELF_INIT
535 Enables support for NAND Flash chips on Tegra SoCs platforms.
538 bool "Support for MediaTek MT7621 NAND flash controller"
539 depends on SOC_MT7621
540 select SYS_NAND_SELF_INIT
541 select SPL_SYS_NAND_SELF_INIT
544 This enables NAND driver for the NAND flash controller on MediaTek
546 The controller supports 4~12 bits correction per 512 bytes with a
547 maximum 4KB page size.
549 comment "Generic NAND options"
551 config SYS_NAND_BLOCK_SIZE
552 hex "NAND chip eraseblock size"
553 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
554 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
555 !NAND_FSL_IFC && !NAND_MT7621
557 Number of data bytes in one eraseblock for the NAND chip on the
558 board. This is the multiple of NAND_PAGE_SIZE and the number of
561 config SYS_NAND_ONFI_DETECTION
562 bool "Enable detection of ONFI compliant devices during probe"
564 Enables detection of ONFI compliant devices during probe.
565 And fetching device parameters flashed on device, by parsing
568 config SYS_NAND_PAGE_COUNT
569 hex "NAND chip page count"
570 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
571 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
573 Number of pages in the NAND chip.
575 config SYS_NAND_PAGE_SIZE
576 hex "NAND chip page size"
577 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
578 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
579 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
580 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
582 Number of data bytes in one page for the NAND chip on the
583 board, not including the OOB area.
585 config SYS_NAND_OOBSIZE
586 hex "NAND chip OOB size"
587 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
588 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
589 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
590 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
592 Number of bytes in the Out-Of-Band area for the NAND chip on
595 # Enhance depends when converting drivers to Kconfig which use this config
596 # option (mxc_nand, ndfc, omap_gpmc).
597 config SYS_NAND_BUSWIDTH_16BIT
598 bool "Use 16-bit NAND interface"
599 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
601 Indicates that NAND device has 16-bit wide data-bus. In absence of this
602 config, bus-width of NAND device is assumed to be either 8-bit and later
603 determined by reading ONFI params.
604 Above config is useful when NAND device's bus-width information cannot
605 be determined from on-chip ONFI params, like in following scenarios:
606 - SPL boot does not support reading of ONFI parameters. This is done to
607 keep SPL code foot-print small.
608 - In current U-Boot flow using nand_init(), driver initialization
609 happens in board_nand_init() which is called before any device probe
610 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
611 not available while configuring controller. So a static CONFIG_NAND_xx
612 is needed to know the device's bus-width in advance.
616 config SYS_NAND_5_ADDR_CYCLE
617 bool "Wait 5 address cycles during NAND commands"
618 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
619 (SPL_NAND_SUPPORT && NAND_ATMEL)
622 Some controllers require waiting for 5 address cycles when issuing
623 some commands, on NAND chips larger than 128MiB.
626 prompt "NAND bad block marker/indicator position in the OOB"
627 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
628 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
629 default HAS_NAND_LARGE_BADBLOCK_POS
631 In the OOB, which position contains the badblock information.
633 config HAS_NAND_LARGE_BADBLOCK_POS
634 bool "Set the bad block marker/indicator to the 'large' position"
636 config HAS_NAND_SMALL_BADBLOCK_POS
637 bool "Set the bad block marker/indicator to the 'small' position"
641 config SYS_NAND_BAD_BLOCK_POS
643 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
644 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
646 config SYS_NAND_U_BOOT_LOCATIONS
647 bool "Define U-boot binaries locations in NAND"
649 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
650 This option should not be enabled when compiling U-boot for boards
651 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
654 config SYS_NAND_U_BOOT_OFFS
655 hex "Location in NAND to read U-Boot from"
656 default 0x800000 if NAND_SUNXI
657 depends on SYS_NAND_U_BOOT_LOCATIONS
659 Set the offset from the start of the nand where u-boot should be
662 config SYS_NAND_U_BOOT_OFFS_REDUND
663 hex "Location in NAND to read U-Boot from"
664 default SYS_NAND_U_BOOT_OFFS
665 depends on SYS_NAND_U_BOOT_LOCATIONS
667 Set the offset from the start of the nand where the redundant u-boot
668 should be loaded from.
670 config SPL_NAND_AM33XX_BCH
671 bool "Enables SPL-NAND driver which supports ELM based"
672 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
675 Hardware ECC correction. This is useful for platforms which have ELM
676 hardware engine and use NAND boot mode.
677 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
678 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
679 SPL-NAND driver with software ECC correction support.
681 config SPL_NAND_DENALI
682 bool "Support Denali NAND controller for SPL"
683 depends on SPL_NAND_SUPPORT
685 This is a small implementation of the Denali NAND controller
688 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
689 int "Number of bytes skipped in OOB area"
690 depends on SPL_NAND_DENALI
693 This option specifies the number of bytes to skip from the beginning
694 of OOB area before last ECC sector data starts. This is potentially
695 used to preserve the bad block marker in the OOB area.
697 config SPL_NAND_SIMPLE
698 bool "Use simple SPL NAND driver"
699 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
701 Support for NAND boot using simple NAND drivers that
702 expose the cmd_ctrl() interface.