2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SYS_NAND_DRIVER_ECC_LAYOUT
13 bool "Omit standard ECC layouts to save space"
15 Omit standard ECC layouts to save space. Select this if your driver
16 is known to provide its own ECC layout.
18 config SYS_NAND_USE_FLASH_BBT
19 bool "Enable BBT (Bad Block Table) support"
21 Enable the BBT (Bad Block Table) usage.
24 bool "Support Atmel NAND controller"
25 imply SYS_NAND_USE_FLASH_BBT
27 Enable this driver for NAND flash platforms using an Atmel NAND
32 config ATMEL_NAND_HWECC
33 bool "Atmel Hardware ECC"
35 config ATMEL_NAND_HW_PMECC
36 bool "Atmel Programmable Multibit ECC (PMECC)"
37 select ATMEL_NAND_HWECC
39 The Programmable Multibit ECC (PMECC) controller is a programmable
40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
43 int "PMECC Correctable ECC Bits"
44 depends on ATMEL_NAND_HW_PMECC
47 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
49 config PMECC_SECTOR_SIZE
50 int "PMECC Sector Size"
51 depends on ATMEL_NAND_HW_PMECC
54 Sector size, in bytes, can be 512 or 1024.
56 config SPL_GENERATE_ATMEL_PMECC_HEADER
57 bool "Atmel PMECC Header Generation"
58 select ATMEL_NAND_HWECC
59 select ATMEL_NAND_HW_PMECC
61 Generate Programmable Multibit ECC (PMECC) header for SPL image.
66 bool "Support Broadcom NAND controller"
67 depends on OF_CONTROL && DM && DM_MTD
69 Enable the driver for NAND flash on platforms using a Broadcom NAND
72 config NAND_BRCMNAND_6368
73 bool "Support Broadcom NAND controller on bcm6368"
74 depends on NAND_BRCMNAND && ARCH_BMIPS
76 Enable support for broadcom nand driver on bcm6368.
78 config NAND_BRCMNAND_68360
79 bool "Support Broadcom NAND controller on bcm68360"
80 depends on NAND_BRCMNAND && ARCH_BCM68360
82 Enable support for broadcom nand driver on bcm68360.
84 config NAND_BRCMNAND_6838
85 bool "Support Broadcom NAND controller on bcm6838"
86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
88 Enable support for broadcom nand driver on bcm6838.
90 config NAND_BRCMNAND_6858
91 bool "Support Broadcom NAND controller on bcm6858"
92 depends on NAND_BRCMNAND && ARCH_BCM6858
94 Enable support for broadcom nand driver on bcm6858.
96 config NAND_BRCMNAND_63158
97 bool "Support Broadcom NAND controller on bcm63158"
98 depends on NAND_BRCMNAND && ARCH_BCM63158
100 Enable support for broadcom nand driver on bcm63158.
103 bool "Support TI Davinci NAND controller"
105 Enable this driver for NAND flash controllers available in TI Davinci
106 and Keystone2 platforms
108 config KEYSTONE_RBL_NAND
109 depends on ARCH_KEYSTONE
114 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
118 select SYS_NAND_SELF_INIT
121 config NAND_DENALI_DT
122 bool "Support Denali NAND controller as a DT device"
124 depends on OF_CONTROL && DM_MTD
126 Enable the driver for NAND flash on platforms using a Denali NAND
127 controller as a DT device.
130 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
133 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
136 bool "Support Freescale Integrated Flash Controller NAND driver"
139 Enable the Freescale Integrated Flash Controller NAND driver.
141 config NAND_LPC32XX_MLC
142 bool "Support LPC32XX_MLC controller"
144 Enable the LPC32XX MLC NAND controller.
146 config NAND_LPC32XX_SLC
147 bool "Support LPC32XX_SLC controller"
149 Enable the LPC32XX SLC NAND controller.
151 config NAND_OMAP_GPMC
152 bool "Support OMAP GPMC NAND controller"
153 depends on ARCH_OMAP2PLUS
155 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
156 GPMC controller is used for parallel NAND flash devices, and can
157 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
158 and BCH16 ECC algorithms.
162 config NAND_OMAP_GPMC_PREFETCH
163 bool "Enable GPMC Prefetch"
166 On OMAP platforms that use the GPMC controller
167 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
168 uses the prefetch mode to speed up read operations.
171 bool "Enable ELM driver for OMAPxx and AMxx platforms."
174 ELM controller is used for ECC error detection (not ECC calculation)
175 of BCH4, BCH8 and BCH16 ECC algorithms.
176 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
177 thus such SoC platforms need to depend on software library for ECC error
178 detection. However ECC calculation on such plaforms would still be
179 done by GPMC controller.
183 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
185 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
186 It can take following values:
187 OMAP_ECC_HAM1_CODE_SW
188 1-bit Hamming code using software lib.
189 (for legacy devices only)
190 OMAP_ECC_HAM1_CODE_HW
191 1-bit Hamming code using GPMC hardware.
192 (for legacy devices only)
193 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
194 4-bit BCH code (unsupported)
195 OMAP_ECC_BCH4_CODE_HW
196 4-bit BCH code (unsupported)
197 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
199 - ecc calculation using GPMC hardware engine,
200 - error detection using software library.
201 - requires CONFIG_BCH to enable software BCH library
202 (For legacy device which do not have ELM h/w engine)
203 OMAP_ECC_BCH8_CODE_HW
205 - ecc calculation using GPMC hardware engine,
206 - error detection using ELM hardware engine.
207 OMAP_ECC_BCH16_CODE_HW
209 - ecc calculation using GPMC hardware engine,
210 - error detection using ELM hardware engine.
212 How to select ECC scheme on OMAP and AMxx platforms ?
213 -----------------------------------------------------
214 Though higher ECC schemes have more capability to detect and correct
215 bit-flips, but still selection of ECC scheme is dependent on following
216 - hardware engines present in SoC.
217 Some legacy OMAP SoC do not have ELM h/w engine thus such
218 SoC cannot support BCHx_HW ECC schemes.
219 - size of OOB/Spare region
220 With higher ECC schemes, more OOB/Spare area is required to
221 store ECC. So choice of ECC scheme is limited by NAND oobsize.
223 In general following expression can help:
224 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
226 NAND_OOBSIZE = number of bytes available in
227 OOB/spare area per NAND page.
228 NAND_PAGESIZE = bytes in main-area of NAND page.
229 ECC_BYTES = number of ECC bytes generated to
230 protect 512 bytes of data, which is:
231 3 for HAM1_xx ecc schemes
232 7 for BCH4_xx ecc schemes
233 14 for BCH8_xx ecc schemes
234 26 for BCH16_xx ecc schemes
236 example to check for BCH16 on 2K page NAND
239 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
240 Thus BCH16 cannot be supported on 2K page NAND.
242 However, for 4K pagesize NAND
246 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
247 Thus BCH16 can be supported on 4K page NAND.
249 config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
250 bool "1-bit Hamming code using software lib"
252 config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
253 bool "1-bit Hamming code using GPMC hardware"
255 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
256 bool "8-bit BCH code with HW calculation SW error detection"
258 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
259 bool "8-bit BCH code with HW calculation and error detection"
261 config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
262 bool "16-bit BCH code with HW calculation and error detection"
266 config NAND_OMAP_ECCSCHEME
268 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
269 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
270 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
271 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
272 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
274 This must be kept in sync with the enum in
275 include/linux/mtd/omap_gpmc.h
279 config NAND_VF610_NFC
280 bool "Support for Freescale NFC for VF610"
281 select SYS_NAND_SELF_INIT
282 select SYS_NAND_DRIVER_ECC_LAYOUT
285 Enables support for NAND Flash Controller on some Freescale
286 processors like the VF610, MCF54418 or Kinetis K70.
287 The driver supports a maximum 2k page size. The driver
288 currently does not support hardware ECC.
292 config NAND_VF610_NFC_DT
293 bool "Support Vybrid's vf610 NAND controller as a DT device"
294 depends on OF_CONTROL && DM_MTD
296 Enable the driver for Vybrid's vf610 NAND flash on platforms
300 prompt "Hardware ECC strength"
301 depends on NAND_VF610_NFC
302 default SYS_NAND_VF610_NFC_45_ECC_BYTES
304 Select the ECC strength used in the hardware BCH ECC block.
306 config SYS_NAND_VF610_NFC_45_ECC_BYTES
307 bool "24-error correction (45 ECC bytes)"
309 config SYS_NAND_VF610_NFC_60_ECC_BYTES
310 bool "32-error correction (60 ECC bytes)"
317 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
318 select SYS_NAND_SELF_INIT
324 This enables the driver for the NAND flash device found on
325 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
328 bool "Support for NAND on Allwinner SoCs"
330 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
331 select SYS_NAND_SELF_INIT
332 select SYS_NAND_U_BOOT_LOCATIONS
333 select SPL_NAND_SUPPORT
336 Enable support for NAND. This option enables the standard and
338 The SPL driver only supports reading from the NAND using DMA
343 config NAND_SUNXI_SPL_ECC_STRENGTH
344 int "Allwinner NAND SPL ECC Strength"
347 config NAND_SUNXI_SPL_ECC_SIZE
348 int "Allwinner NAND SPL ECC Step Size"
351 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
352 int "Allwinner NAND SPL Usable Page Size"
358 bool "Configure Arasan Nand"
359 select SYS_NAND_SELF_INIT
363 This enables Nand driver support for Arasan nand flash
364 controller. This uses the hardware ECC for read and
368 bool "MXC NAND support"
369 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
372 This enables the NAND driver for the NAND flash controller on the
373 i.MX27 / i.MX31 / i.MX5 processors.
376 bool "MXS NAND support"
377 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
378 select SYS_NAND_SELF_INIT
381 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
382 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
384 This enables NAND driver for the NAND flash controller on the
390 bool "Support MXS NAND controller as a DT device"
391 depends on OF_CONTROL && DM_MTD
393 Enable the driver for MXS NAND flash on platforms using
396 config NAND_MXS_USE_MINIMUM_ECC
397 bool "Use minimum ECC strength supported by the controller"
403 bool "Macronix raw NAND controller"
404 select SYS_NAND_SELF_INIT
406 This selects the Macronix raw NAND controller driver.
409 bool "Support for Zynq Nand controller"
410 select SYS_NAND_SELF_INIT
414 This enables Nand driver support for Nand flash controller
417 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
418 bool "Enable use of 1st stage bootloader timing for NAND"
421 This flag prevent U-boot reconfigure NAND flash controller and reuse
422 the NAND timing from 1st stage bootloader.
425 bool "Support for OcteonTX NAND controller"
426 select SYS_NAND_SELF_INIT
429 This enables Nand flash controller hardware found on the OcteonTX
432 config NAND_OCTEONTX_HW_ECC
433 bool "Support Hardware ECC for OcteonTX NAND controller"
434 depends on NAND_OCTEONTX
437 This enables Hardware BCH engine found on the OcteonTX processors to
438 support ECC for NAND flash controller.
440 config NAND_STM32_FMC2
441 bool "Support for NAND controller on STM32MP SoCs"
442 depends on ARCH_STM32MP
443 select SYS_NAND_SELF_INIT
446 Enables support for NAND Flash chips on SoCs containing the FMC2
447 NAND controller. This controller is found on STM32MP SoCs.
448 The controller supports a maximum 8k page size and supports
449 a maximum 8-bit correction error per sector of 512 bytes.
452 bool "Support for NAND controller on Cortina-Access SoCs"
453 depends on CORTINA_PLATFORM
454 select SYS_NAND_SELF_INIT
458 Enables support for NAND Flash chips on Coartina-Access SoCs platform
459 This controller is found on Presidio/Venus SoCs.
460 The controller supports a maximum 8k page size and supports
461 a maximum 40-bit error correction per sector of 1024 bytes.
464 bool "Support for NAND controller on Rockchip SoCs"
465 depends on ARCH_ROCKCHIP
466 select SYS_NAND_SELF_INIT
470 Enables support for NAND Flash chips on Rockchip SoCs platform.
471 This controller is found on Rockchip SoCs.
472 There are four different versions of NAND FLASH Controllers,
474 NFC v600: RK2928, RK3066, RK3188
475 NFC v622: RK3036, RK3128
476 NFC v800: RK3308, RV1108
477 NFC v900: PX30, RK3326
480 bool "Support for NAND controller on Tegra SoCs"
481 depends on ARCH_TEGRA
482 select SYS_NAND_SELF_INIT
485 Enables support for NAND Flash chips on Tegra SoCs platforms.
487 comment "Generic NAND options"
489 config SYS_NAND_BLOCK_SIZE
490 hex "NAND chip eraseblock size"
491 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
492 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_FSL_IFC
494 Number of data bytes in one eraseblock for the NAND chip on the
495 board. This is the multiple of NAND_PAGE_SIZE and the number of
498 config SYS_NAND_ONFI_DETECTION
499 bool "Enable detection of ONFI compliant devices during probe"
501 Enables detection of ONFI compliant devices during probe.
502 And fetching device parameters flashed on device, by parsing
505 config SYS_NAND_PAGE_COUNT
506 hex "NAND chip page count"
507 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
508 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
510 Number of pages in the NAND chip.
512 config SYS_NAND_PAGE_SIZE
513 hex "NAND chip page size"
514 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
515 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
516 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
517 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
519 Number of data bytes in one page for the NAND chip on the
520 board, not including the OOB area.
522 config SYS_NAND_OOBSIZE
523 hex "NAND chip OOB size"
524 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
525 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
526 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
527 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
529 Number of bytes in the Out-Of-Band area for the NAND chip on
532 # Enhance depends when converting drivers to Kconfig which use this config
533 # option (mxc_nand, ndfc, omap_gpmc).
534 config SYS_NAND_BUSWIDTH_16BIT
535 bool "Use 16-bit NAND interface"
536 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
538 Indicates that NAND device has 16-bit wide data-bus. In absence of this
539 config, bus-width of NAND device is assumed to be either 8-bit and later
540 determined by reading ONFI params.
541 Above config is useful when NAND device's bus-width information cannot
542 be determined from on-chip ONFI params, like in following scenarios:
543 - SPL boot does not support reading of ONFI parameters. This is done to
544 keep SPL code foot-print small.
545 - In current U-Boot flow using nand_init(), driver initialization
546 happens in board_nand_init() which is called before any device probe
547 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
548 not available while configuring controller. So a static CONFIG_NAND_xx
549 is needed to know the device's bus-width in advance.
553 config SYS_NAND_5_ADDR_CYCLE
554 bool "Wait 5 address cycles during NAND commands"
555 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
556 (SPL_NAND_SUPPORT && NAND_ATMEL)
559 Some controllers require waiting for 5 address cycles when issuing
560 some commands, on NAND chips larger than 128MiB.
563 prompt "NAND bad block marker/indicator position in the OOB"
564 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
565 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
566 default HAS_NAND_LARGE_BADBLOCK_POS
568 In the OOB, which position contains the badblock information.
570 config HAS_NAND_LARGE_BADBLOCK_POS
571 bool "Set the bad block marker/indicator to the 'large' position"
573 config HAS_NAND_SMALL_BADBLOCK_POS
574 bool "Set the bad block marker/indicator to the 'small' position"
578 config SYS_NAND_BAD_BLOCK_POS
580 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
581 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
583 config SYS_NAND_U_BOOT_LOCATIONS
584 bool "Define U-boot binaries locations in NAND"
586 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
587 This option should not be enabled when compiling U-boot for boards
588 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
591 config SYS_NAND_U_BOOT_OFFS
592 hex "Location in NAND to read U-Boot from"
593 default 0x800000 if NAND_SUNXI
594 depends on SYS_NAND_U_BOOT_LOCATIONS
596 Set the offset from the start of the nand where u-boot should be
599 config SYS_NAND_U_BOOT_OFFS_REDUND
600 hex "Location in NAND to read U-Boot from"
601 default SYS_NAND_U_BOOT_OFFS
602 depends on SYS_NAND_U_BOOT_LOCATIONS
604 Set the offset from the start of the nand where the redundant u-boot
605 should be loaded from.
607 config SPL_NAND_AM33XX_BCH
608 bool "Enables SPL-NAND driver which supports ELM based"
609 depends on NAND_OMAP_GPMC && !OMAP34XX
612 Hardware ECC correction. This is useful for platforms which have ELM
613 hardware engine and use NAND boot mode.
614 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
615 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
616 SPL-NAND driver with software ECC correction support.
618 config SPL_NAND_DENALI
619 bool "Support Denali NAND controller for SPL"
621 This is a small implementation of the Denali NAND controller
624 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
625 int "Number of bytes skipped in OOB area"
626 depends on SPL_NAND_DENALI
629 This option specifies the number of bytes to skip from the beginning
630 of OOB area before last ECC sector data starts. This is potentially
631 used to preserve the bad block marker in the OOB area.
633 config SPL_NAND_SIMPLE
634 bool "Use simple SPL NAND driver"
635 depends on !SPL_NAND_AM33XX_BCH
637 Support for NAND boot using simple NAND drivers that
638 expose the cmd_ctrl() interface.