2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SPL_SYS_NAND_SELF_INIT
14 depends on !SPL_NAND_SIMPLE
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
19 config TPL_SYS_NAND_SELF_INIT
21 depends on TPL_NAND_SUPPORT
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
32 config SYS_MAX_NAND_DEVICE
33 int "Maximum number of NAND devices to support"
36 config SYS_NAND_DRIVER_ECC_LAYOUT
37 bool "Omit standard ECC layouts to save space"
39 Omit standard ECC layouts to save space. Select this if your driver
40 is known to provide its own ECC layout.
42 config SYS_NAND_USE_FLASH_BBT
43 bool "Enable BBT (Bad Block Table) support"
45 Enable the BBT (Bad Block Table) usage.
47 config SYS_NAND_NO_SUBPAGE_WRITE
48 bool "Disable subpage write support"
49 depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
52 bool "Support Atmel NAND controller with DM support"
53 select SYS_NAND_SELF_INIT
54 imply SYS_NAND_USE_FLASH_BBT
56 Enable this driver for NAND flash platforms using an Atmel NAND
60 bool "Support Atmel NAND controller"
61 select SYS_NAND_SELF_INIT
62 imply SYS_NAND_USE_FLASH_BBT
64 Enable this driver for NAND flash platforms using an Atmel NAND
69 config ATMEL_NAND_HWECC
70 bool "Atmel Hardware ECC"
72 config ATMEL_NAND_HW_PMECC
73 bool "Atmel Programmable Multibit ECC (PMECC)"
74 select ATMEL_NAND_HWECC
76 The Programmable Multibit ECC (PMECC) controller is a programmable
77 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
80 int "PMECC Correctable ECC Bits"
81 depends on ATMEL_NAND_HW_PMECC
84 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
86 config PMECC_SECTOR_SIZE
87 int "PMECC Sector Size"
88 depends on ATMEL_NAND_HW_PMECC
91 Sector size, in bytes, can be 512 or 1024.
93 config SPL_GENERATE_ATMEL_PMECC_HEADER
94 bool "Atmel PMECC Header Generation"
96 select ATMEL_NAND_HWECC
97 select ATMEL_NAND_HW_PMECC
99 Generate Programmable Multibit ECC (PMECC) header for SPL image.
102 prompt "NAND bus width (bits)"
103 default SYS_NAND_DBW_8
105 config SYS_NAND_DBW_8
106 bool "NAND bus width is 8 bits"
108 config SYS_NAND_DBW_16
109 bool "NAND bus width is 16 bits"
116 bool "Support Broadcom NAND controller"
117 depends on OF_CONTROL && DM && DM_MTD
118 select SYS_NAND_SELF_INIT
120 Enable the driver for NAND flash on platforms using a Broadcom NAND
123 config NAND_BRCMNAND_6368
124 bool "Support Broadcom NAND controller on bcm6368"
125 depends on NAND_BRCMNAND && ARCH_BMIPS
127 Enable support for broadcom nand driver on bcm6368.
129 config NAND_BRCMNAND_6753
130 bool "Support Broadcom NAND controller on bcm6753"
131 depends on NAND_BRCMNAND && BCM6855
133 Enable support for broadcom nand driver on bcm6753.
135 config NAND_BRCMNAND_68360
136 bool "Support Broadcom NAND controller on bcm68360"
137 depends on NAND_BRCMNAND && BCM6856
139 Enable support for broadcom nand driver on bcm68360.
141 config NAND_BRCMNAND_6838
142 bool "Support Broadcom NAND controller on bcm6838"
143 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
145 Enable support for broadcom nand driver on bcm6838.
147 config NAND_BRCMNAND_6858
148 bool "Support Broadcom NAND controller on bcm6858"
149 depends on NAND_BRCMNAND && BCM6858
151 Enable support for broadcom nand driver on bcm6858.
153 config NAND_BRCMNAND_63158
154 bool "Support Broadcom NAND controller on bcm63158"
155 depends on NAND_BRCMNAND && BCM63158
157 Enable support for broadcom nand driver on bcm63158.
159 config NAND_BRCMNAND_IPROC
160 bool "Support Broadcom NAND controller on the iproc family"
161 depends on NAND_BRCMNAND
163 Enable support for broadcom nand driver on the Broadcom
164 iproc family such as Northstar (BCM5301x, BCM4708...)
167 bool "Support TI Davinci NAND controller"
168 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
170 Enable this driver for NAND flash controllers available in TI Davinci
171 and Keystone2 platforms
174 prompt "Type of ECC used on NAND"
175 default SYS_NAND_4BIT_HW_ECC_OOBFIRST
176 depends on NAND_DAVINCI
178 config SYS_NAND_HW_ECC
179 bool "Use 1-bit HW ECC"
181 config SYS_NAND_4BIT_HW_ECC_OOBFIRST
182 bool "Use 4-bit HW ECC with OOB at the front"
184 config SYS_NAND_SOFT_ECC
185 bool "Use software ECC"
190 prompt "NAND page size"
191 depends on NAND_DAVINCI
192 default SYS_NAND_PAGE_2K
194 config SYS_NAND_PAGE_2K
195 bool "Page size is 2K"
197 config SYS_NAND_PAGE_4K
198 bool "Page size is 4K"
202 config KEYSTONE_RBL_NAND
203 depends on ARCH_KEYSTONE
208 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
212 select SYS_NAND_SELF_INIT
215 config NAND_DENALI_DT
216 bool "Support Denali NAND controller as a DT device"
218 select SPL_SYS_NAND_SELF_INIT
219 depends on OF_CONTROL && DM_MTD
221 Enable the driver for NAND flash on platforms using a Denali NAND
222 controller as a DT device.
225 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
226 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
227 select SPL_SYS_NAND_SELF_INIT
228 select SYS_NAND_SELF_INIT
231 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
233 config NAND_FSL_ELBC_DT
234 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
235 depends on NAND_FSL_ELBC
238 bool "Support Freescale Integrated Flash Controller NAND driver"
239 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
240 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
241 select SPL_SYS_NAND_SELF_INIT
242 select SYS_NAND_SELF_INIT
245 Enable the Freescale Integrated Flash Controller NAND driver.
248 bool "Support for Kirkwood NAND controller"
249 depends on ARCH_KIRKWOOD
256 bool "Support KMETER1 NAND controller"
260 config NAND_LPC32XX_MLC
261 bool "Support LPC32XX_MLC controller"
262 select SYS_NAND_SELF_INIT
264 Enable the LPC32XX MLC NAND controller.
266 config NAND_LPC32XX_SLC
267 bool "Support LPC32XX_SLC controller"
269 Enable the LPC32XX SLC NAND controller.
271 config NAND_OMAP_GPMC
272 bool "Support OMAP GPMC NAND controller"
273 depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
274 select SYS_NAND_SELF_INIT if ARCH_K3
275 select SPL_NAND_INIT if ARCH_K3
276 select SPL_SYS_NAND_SELF_INIT if ARCH_K3
278 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
279 GPMC controller is used for parallel NAND flash devices, and can
280 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
281 and BCH16 ECC algorithms.
285 config NAND_OMAP_GPMC_PREFETCH
286 bool "Enable GPMC Prefetch"
289 On OMAP platforms that use the GPMC controller
290 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
291 uses the prefetch mode to speed up read operations.
294 bool "Enable ELM driver for OMAPxx and AMxx platforms."
297 ELM controller is used for ECC error detection (not ECC calculation)
298 of BCH4, BCH8 and BCH16 ECC algorithms.
299 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
300 thus such SoC platforms need to depend on software library for ECC error
301 detection. However ECC calculation on such plaforms would still be
302 done by GPMC controller.
306 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
308 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
309 It can take following values:
310 OMAP_ECC_HAM1_CODE_SW
311 1-bit Hamming code using software lib.
312 (for legacy devices only)
313 OMAP_ECC_HAM1_CODE_HW
314 1-bit Hamming code using GPMC hardware.
315 (for legacy devices only)
316 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
317 4-bit BCH code (unsupported)
318 OMAP_ECC_BCH4_CODE_HW
319 4-bit BCH code (unsupported)
320 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
322 - ecc calculation using GPMC hardware engine,
323 - error detection using software library.
324 - requires CONFIG_BCH to enable software BCH library
325 (For legacy device which do not have ELM h/w engine)
326 OMAP_ECC_BCH8_CODE_HW
328 - ecc calculation using GPMC hardware engine,
329 - error detection using ELM hardware engine.
330 OMAP_ECC_BCH16_CODE_HW
332 - ecc calculation using GPMC hardware engine,
333 - error detection using ELM hardware engine.
335 How to select ECC scheme on OMAP and AMxx platforms ?
336 -----------------------------------------------------
337 Though higher ECC schemes have more capability to detect and correct
338 bit-flips, but still selection of ECC scheme is dependent on following
339 - hardware engines present in SoC.
340 Some legacy OMAP SoC do not have ELM h/w engine thus such
341 SoC cannot support BCHx_HW ECC schemes.
342 - size of OOB/Spare region
343 With higher ECC schemes, more OOB/Spare area is required to
344 store ECC. So choice of ECC scheme is limited by NAND oobsize.
346 In general following expression can help:
347 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
349 NAND_OOBSIZE = number of bytes available in
350 OOB/spare area per NAND page.
351 NAND_PAGESIZE = bytes in main-area of NAND page.
352 ECC_BYTES = number of ECC bytes generated to
353 protect 512 bytes of data, which is:
354 3 for HAM1_xx ecc schemes
355 7 for BCH4_xx ecc schemes
356 14 for BCH8_xx ecc schemes
357 26 for BCH16_xx ecc schemes
359 example to check for BCH16 on 2K page NAND
362 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
363 Thus BCH16 cannot be supported on 2K page NAND.
365 However, for 4K pagesize NAND
369 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
370 Thus BCH16 can be supported on 4K page NAND.
372 config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
373 bool "1-bit Hamming code using software lib"
375 config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
376 bool "1-bit Hamming code using GPMC hardware"
378 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
379 bool "8-bit BCH code with HW calculation SW error detection"
381 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
382 bool "8-bit BCH code with HW calculation and error detection"
384 config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
385 bool "16-bit BCH code with HW calculation and error detection"
389 config NAND_OMAP_ECCSCHEME
391 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
392 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
393 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
394 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
395 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
397 This must be kept in sync with the enum in
398 include/linux/mtd/omap_gpmc.h
402 config NAND_VF610_NFC
403 bool "Support for Freescale NFC for VF610"
404 select SYS_NAND_SELF_INIT
405 select SYS_NAND_DRIVER_ECC_LAYOUT
408 Enables support for NAND Flash Controller on some Freescale
409 processors like the VF610, MCF54418 or Kinetis K70.
410 The driver supports a maximum 2k page size. The driver
411 currently does not support hardware ECC.
415 config NAND_VF610_NFC_DT
416 bool "Support Vybrid's vf610 NAND controller as a DT device"
417 depends on OF_CONTROL && DM_MTD
419 Enable the driver for Vybrid's vf610 NAND flash on platforms
423 prompt "Hardware ECC strength"
424 depends on NAND_VF610_NFC
425 default SYS_NAND_VF610_NFC_45_ECC_BYTES
427 Select the ECC strength used in the hardware BCH ECC block.
429 config SYS_NAND_VF610_NFC_45_ECC_BYTES
430 bool "24-error correction (45 ECC bytes)"
432 config SYS_NAND_VF610_NFC_60_ECC_BYTES
433 bool "32-error correction (60 ECC bytes)"
440 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
441 select SYS_NAND_SELF_INIT
447 This enables the driver for the NAND flash device found on
448 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
451 bool "Support for NAND on Allwinner SoCs"
453 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
454 select SYS_NAND_SELF_INIT
455 select SYS_NAND_U_BOOT_LOCATIONS
456 select SPL_NAND_SUPPORT
457 select SPL_SYS_NAND_SELF_INIT
460 Enable support for NAND. This option enables the standard and
462 The SPL driver only supports reading from the NAND using DMA
467 config NAND_SUNXI_SPL_ECC_STRENGTH
468 int "Allwinner NAND SPL ECC Strength"
471 config NAND_SUNXI_SPL_ECC_SIZE
472 int "Allwinner NAND SPL ECC Step Size"
475 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
476 int "Allwinner NAND SPL Usable Page Size"
482 bool "Configure Arasan Nand"
483 select SYS_NAND_SELF_INIT
487 This enables Nand driver support for Arasan nand flash
488 controller. This uses the hardware ECC for read and
492 bool "MXC NAND support"
493 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
496 This enables the NAND driver for the NAND flash controller on the
497 i.MX27 / i.MX31 / i.MX5 processors.
500 int "Size of NAND in kilobytes"
501 depends on NAND_MXC && SPL_NAND_SUPPORT
504 config MXC_NAND_HWECC
505 bool "Hardware ECC support in MXC NAND"
509 bool "MXS NAND support"
510 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
511 select SPL_SYS_NAND_SELF_INIT
512 select SYS_NAND_SELF_INIT
515 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
516 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
518 This enables NAND driver for the NAND flash controller on the
524 bool "Support MXS NAND controller as a DT device"
525 depends on OF_CONTROL && DM_MTD
527 Enable the driver for MXS NAND flash on platforms using
530 config NAND_MXS_USE_MINIMUM_ECC
531 bool "Use minimum ECC strength supported by the controller"
537 bool "Macronix raw NAND controller"
538 select SYS_NAND_SELF_INIT
540 This selects the Macronix raw NAND controller driver.
543 bool "Support for Zynq Nand controller"
544 select SPL_SYS_NAND_SELF_INIT
545 select SYS_NAND_SELF_INIT
549 This enables Nand driver support for Nand flash controller
552 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
553 bool "Enable use of 1st stage bootloader timing for NAND"
556 This flag prevent U-Boot reconfigure NAND flash controller and reuse
557 the NAND timing from 1st stage bootloader.
560 bool "Support for OcteonTX NAND controller"
561 select SYS_NAND_SELF_INIT
564 This enables Nand flash controller hardware found on the OcteonTX
567 config NAND_OCTEONTX_HW_ECC
568 bool "Support Hardware ECC for OcteonTX NAND controller"
569 depends on NAND_OCTEONTX
572 This enables Hardware BCH engine found on the OcteonTX processors to
573 support ECC for NAND flash controller.
575 config NAND_STM32_FMC2
576 bool "Support for NAND controller on STM32MP SoCs"
577 depends on ARCH_STM32MP
578 select SYS_NAND_SELF_INIT
581 Enables support for NAND Flash chips on SoCs containing the FMC2
582 NAND controller. This controller is found on STM32MP SoCs.
583 The controller supports a maximum 8k page size and supports
584 a maximum 8-bit correction error per sector of 512 bytes.
587 bool "Support for NAND controller on Cortina-Access SoCs"
588 depends on CORTINA_PLATFORM
589 select SYS_NAND_SELF_INIT
593 Enables support for NAND Flash chips on Coartina-Access SoCs platform
594 This controller is found on Presidio/Venus SoCs.
595 The controller supports a maximum 8k page size and supports
596 a maximum 40-bit error correction per sector of 1024 bytes.
599 bool "Support for NAND controller on Rockchip SoCs"
600 depends on ARCH_ROCKCHIP
601 select SYS_NAND_SELF_INIT
605 Enables support for NAND Flash chips on Rockchip SoCs platform.
606 This controller is found on Rockchip SoCs.
607 There are four different versions of NAND FLASH Controllers,
609 NFC v600: RK2928, RK3066, RK3188
610 NFC v622: RK3036, RK3128
611 NFC v800: RK3308, RV1108
612 NFC v900: PX30, RK3326
615 bool "Support for NAND controller on Tegra SoCs"
616 depends on ARCH_TEGRA
617 select SYS_NAND_SELF_INIT
620 Enables support for NAND Flash chips on Tegra SoCs platforms.
623 bool "Support for MediaTek MT7621 NAND flash controller"
624 depends on SOC_MT7621
625 select SYS_NAND_SELF_INIT
626 select SPL_SYS_NAND_SELF_INIT
629 This enables NAND driver for the NAND flash controller on MediaTek
631 The controller supports 4~12 bits correction per 512 bytes with a
632 maximum 4KB page size.
634 comment "Generic NAND options"
636 config SYS_NAND_BLOCK_SIZE
637 hex "NAND chip eraseblock size"
638 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT || \
639 MVEBU_SPL_BOOT_DEVICE_NAND
640 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
641 !NAND_FSL_IFC && !NAND_MT7621
643 Number of data bytes in one eraseblock for the NAND chip on the
644 board. This is the multiple of NAND_PAGE_SIZE and the number of
647 config SYS_NAND_ONFI_DETECTION
648 bool "Enable detection of ONFI compliant devices during probe"
650 Enables detection of ONFI compliant devices during probe.
651 And fetching device parameters flashed on device, by parsing
654 config SYS_NAND_PAGE_COUNT
655 hex "NAND chip page count"
656 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
657 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \
660 Number of pages in the NAND chip.
662 config SYS_NAND_PAGE_SIZE
663 hex "NAND chip page size"
664 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
665 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
666 MVEBU_SPL_BOOT_DEVICE_NAND || \
667 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
668 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
670 Number of data bytes in one page for the NAND chip on the
671 board, not including the OOB area.
673 config SYS_NAND_OOBSIZE
674 hex "NAND chip OOB size"
675 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
676 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
677 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
678 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
680 Number of bytes in the Out-Of-Band area for the NAND chip on
683 # Enhance depends when converting drivers to Kconfig which use this config
684 # option (mxc_nand, ndfc, omap_gpmc).
685 config SYS_NAND_BUSWIDTH_16BIT
686 bool "Use 16-bit NAND interface"
687 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
689 Indicates that NAND device has 16-bit wide data-bus. In absence of this
690 config, bus-width of NAND device is assumed to be either 8-bit and later
691 determined by reading ONFI params.
692 Above config is useful when NAND device's bus-width information cannot
693 be determined from on-chip ONFI params, like in following scenarios:
694 - SPL boot does not support reading of ONFI parameters. This is done to
695 keep SPL code foot-print small.
696 - In current U-Boot flow using nand_init(), driver initialization
697 happens in board_nand_init() which is called before any device probe
698 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
699 not available while configuring controller. So a static CONFIG_NAND_xx
700 is needed to know the device's bus-width in advance.
704 config SYS_NAND_5_ADDR_CYCLE
705 bool "Wait 5 address cycles during NAND commands"
706 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
707 (SPL_NAND_SUPPORT && NAND_ATMEL)
710 Some controllers require waiting for 5 address cycles when issuing
711 some commands, on NAND chips larger than 128MiB.
714 prompt "NAND bad block marker/indicator position in the OOB"
715 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
716 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
717 default HAS_NAND_LARGE_BADBLOCK_POS
719 In the OOB, which position contains the badblock information.
721 config HAS_NAND_LARGE_BADBLOCK_POS
722 bool "Set the bad block marker/indicator to the 'large' position"
724 config HAS_NAND_SMALL_BADBLOCK_POS
725 bool "Set the bad block marker/indicator to the 'small' position"
729 config SYS_NAND_BAD_BLOCK_POS
731 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
732 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
734 config SYS_NAND_U_BOOT_LOCATIONS
735 bool "Define U-Boot binaries locations in NAND"
737 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
738 This option should not be enabled when compiling U-Boot for boards
739 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
742 config SYS_NAND_U_BOOT_OFFS
743 hex "Location in NAND to read U-Boot from"
744 default 0x800000 if NAND_SUNXI
745 depends on SYS_NAND_U_BOOT_LOCATIONS
747 Set the offset from the start of the nand where u-boot should be
750 config SYS_NAND_U_BOOT_OFFS_REDUND
751 hex "Location in NAND to read U-Boot from"
752 default SYS_NAND_U_BOOT_OFFS
753 depends on SYS_NAND_U_BOOT_LOCATIONS
755 Set the offset from the start of the nand where the redundant u-boot
756 should be loaded from.
758 config SPL_NAND_AM33XX_BCH
759 bool "Enables SPL-NAND driver which supports ELM based"
760 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
763 Hardware ECC correction. This is useful for platforms which have ELM
764 hardware engine and use NAND boot mode.
765 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
766 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
767 SPL-NAND driver with software ECC correction support.
769 config SPL_NAND_DENALI
770 bool "Support Denali NAND controller for SPL"
771 depends on SPL_NAND_SUPPORT
773 This is a small implementation of the Denali NAND controller
776 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
777 int "Number of bytes skipped in OOB area"
778 depends on SPL_NAND_DENALI
781 This option specifies the number of bytes to skip from the beginning
782 of OOB area before last ECC sector data starts. This is potentially
783 used to preserve the bad block marker in the OOB area.
785 config SPL_NAND_SIMPLE
786 bool "Use simple SPL NAND driver"
787 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
789 Support for NAND boot using simple NAND drivers that
790 expose the cmd_ctrl() interface.
792 config SYS_NAND_HW_ECC_OOBFIRST
793 bool "In SPL, read the OOB first and then the data from NAND"
794 depends on SPL_NAND_SIMPLE