2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SPL_SYS_NAND_SELF_INIT
14 depends on !SPL_NAND_SIMPLE
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
19 config TPL_SYS_NAND_SELF_INIT
21 depends on TPL_NAND_SUPPORT
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
29 config SYS_NAND_DRIVER_ECC_LAYOUT
30 bool "Omit standard ECC layouts to save space"
32 Omit standard ECC layouts to save space. Select this if your driver
33 is known to provide its own ECC layout.
35 config SYS_NAND_USE_FLASH_BBT
36 bool "Enable BBT (Bad Block Table) support"
38 Enable the BBT (Bad Block Table) usage.
41 bool "Support Atmel NAND controller"
42 select SYS_NAND_SELF_INIT
43 imply SYS_NAND_USE_FLASH_BBT
45 Enable this driver for NAND flash platforms using an Atmel NAND
50 config ATMEL_NAND_HWECC
51 bool "Atmel Hardware ECC"
53 config ATMEL_NAND_HW_PMECC
54 bool "Atmel Programmable Multibit ECC (PMECC)"
55 select ATMEL_NAND_HWECC
57 The Programmable Multibit ECC (PMECC) controller is a programmable
58 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
61 int "PMECC Correctable ECC Bits"
62 depends on ATMEL_NAND_HW_PMECC
65 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
67 config PMECC_SECTOR_SIZE
68 int "PMECC Sector Size"
69 depends on ATMEL_NAND_HW_PMECC
72 Sector size, in bytes, can be 512 or 1024.
74 config SPL_GENERATE_ATMEL_PMECC_HEADER
75 bool "Atmel PMECC Header Generation"
76 select ATMEL_NAND_HWECC
77 select ATMEL_NAND_HW_PMECC
79 Generate Programmable Multibit ECC (PMECC) header for SPL image.
84 bool "Support Broadcom NAND controller"
85 depends on OF_CONTROL && DM && DM_MTD
86 select SYS_NAND_SELF_INIT
88 Enable the driver for NAND flash on platforms using a Broadcom NAND
91 config NAND_BRCMNAND_6368
92 bool "Support Broadcom NAND controller on bcm6368"
93 depends on NAND_BRCMNAND && ARCH_BMIPS
95 Enable support for broadcom nand driver on bcm6368.
97 config NAND_BRCMNAND_6753
98 bool "Support Broadcom NAND controller on bcm6753"
99 depends on NAND_BRCMNAND && ARCH_BCM6753
101 Enable support for broadcom nand driver on bcm6753.
103 config NAND_BRCMNAND_68360
104 bool "Support Broadcom NAND controller on bcm68360"
105 depends on NAND_BRCMNAND && ARCH_BCM68360
107 Enable support for broadcom nand driver on bcm68360.
109 config NAND_BRCMNAND_6838
110 bool "Support Broadcom NAND controller on bcm6838"
111 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
113 Enable support for broadcom nand driver on bcm6838.
115 config NAND_BRCMNAND_6858
116 bool "Support Broadcom NAND controller on bcm6858"
117 depends on NAND_BRCMNAND && ARCH_BCM6858
119 Enable support for broadcom nand driver on bcm6858.
121 config NAND_BRCMNAND_63158
122 bool "Support Broadcom NAND controller on bcm63158"
123 depends on NAND_BRCMNAND && ARCH_BCM63158
125 Enable support for broadcom nand driver on bcm63158.
128 bool "Support TI Davinci NAND controller"
129 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
131 Enable this driver for NAND flash controllers available in TI Davinci
132 and Keystone2 platforms
134 config KEYSTONE_RBL_NAND
135 depends on ARCH_KEYSTONE
140 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
144 select SYS_NAND_SELF_INIT
147 config NAND_DENALI_DT
148 bool "Support Denali NAND controller as a DT device"
150 depends on OF_CONTROL && DM_MTD
152 Enable the driver for NAND flash on platforms using a Denali NAND
153 controller as a DT device.
156 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
157 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
158 select SPL_SYS_NAND_SELF_INIT
159 select SYS_NAND_SELF_INIT
162 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
164 config NAND_FSL_ELBC_DT
165 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
166 depends on NAND_FSL_ELBC
169 bool "Support Freescale Integrated Flash Controller NAND driver"
170 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
171 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
172 select SPL_SYS_NAND_SELF_INIT
173 select SYS_NAND_SELF_INIT
176 Enable the Freescale Integrated Flash Controller NAND driver.
178 config NAND_LPC32XX_MLC
179 bool "Support LPC32XX_MLC controller"
180 select SYS_NAND_SELF_INIT
182 Enable the LPC32XX MLC NAND controller.
184 config NAND_LPC32XX_SLC
185 bool "Support LPC32XX_SLC controller"
187 Enable the LPC32XX SLC NAND controller.
189 config NAND_OMAP_GPMC
190 bool "Support OMAP GPMC NAND controller"
191 depends on ARCH_OMAP2PLUS
193 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
194 GPMC controller is used for parallel NAND flash devices, and can
195 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
196 and BCH16 ECC algorithms.
200 config NAND_OMAP_GPMC_PREFETCH
201 bool "Enable GPMC Prefetch"
204 On OMAP platforms that use the GPMC controller
205 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
206 uses the prefetch mode to speed up read operations.
209 bool "Enable ELM driver for OMAPxx and AMxx platforms."
212 ELM controller is used for ECC error detection (not ECC calculation)
213 of BCH4, BCH8 and BCH16 ECC algorithms.
214 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
215 thus such SoC platforms need to depend on software library for ECC error
216 detection. However ECC calculation on such plaforms would still be
217 done by GPMC controller.
221 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
223 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
224 It can take following values:
225 OMAP_ECC_HAM1_CODE_SW
226 1-bit Hamming code using software lib.
227 (for legacy devices only)
228 OMAP_ECC_HAM1_CODE_HW
229 1-bit Hamming code using GPMC hardware.
230 (for legacy devices only)
231 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
232 4-bit BCH code (unsupported)
233 OMAP_ECC_BCH4_CODE_HW
234 4-bit BCH code (unsupported)
235 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
237 - ecc calculation using GPMC hardware engine,
238 - error detection using software library.
239 - requires CONFIG_BCH to enable software BCH library
240 (For legacy device which do not have ELM h/w engine)
241 OMAP_ECC_BCH8_CODE_HW
243 - ecc calculation using GPMC hardware engine,
244 - error detection using ELM hardware engine.
245 OMAP_ECC_BCH16_CODE_HW
247 - ecc calculation using GPMC hardware engine,
248 - error detection using ELM hardware engine.
250 How to select ECC scheme on OMAP and AMxx platforms ?
251 -----------------------------------------------------
252 Though higher ECC schemes have more capability to detect and correct
253 bit-flips, but still selection of ECC scheme is dependent on following
254 - hardware engines present in SoC.
255 Some legacy OMAP SoC do not have ELM h/w engine thus such
256 SoC cannot support BCHx_HW ECC schemes.
257 - size of OOB/Spare region
258 With higher ECC schemes, more OOB/Spare area is required to
259 store ECC. So choice of ECC scheme is limited by NAND oobsize.
261 In general following expression can help:
262 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
264 NAND_OOBSIZE = number of bytes available in
265 OOB/spare area per NAND page.
266 NAND_PAGESIZE = bytes in main-area of NAND page.
267 ECC_BYTES = number of ECC bytes generated to
268 protect 512 bytes of data, which is:
269 3 for HAM1_xx ecc schemes
270 7 for BCH4_xx ecc schemes
271 14 for BCH8_xx ecc schemes
272 26 for BCH16_xx ecc schemes
274 example to check for BCH16 on 2K page NAND
277 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
278 Thus BCH16 cannot be supported on 2K page NAND.
280 However, for 4K pagesize NAND
284 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
285 Thus BCH16 can be supported on 4K page NAND.
287 config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
288 bool "1-bit Hamming code using software lib"
290 config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
291 bool "1-bit Hamming code using GPMC hardware"
293 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
294 bool "8-bit BCH code with HW calculation SW error detection"
296 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
297 bool "8-bit BCH code with HW calculation and error detection"
299 config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
300 bool "16-bit BCH code with HW calculation and error detection"
304 config NAND_OMAP_ECCSCHEME
306 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
307 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
308 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
309 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
310 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
312 This must be kept in sync with the enum in
313 include/linux/mtd/omap_gpmc.h
317 config NAND_VF610_NFC
318 bool "Support for Freescale NFC for VF610"
319 select SYS_NAND_SELF_INIT
320 select SYS_NAND_DRIVER_ECC_LAYOUT
323 Enables support for NAND Flash Controller on some Freescale
324 processors like the VF610, MCF54418 or Kinetis K70.
325 The driver supports a maximum 2k page size. The driver
326 currently does not support hardware ECC.
330 config NAND_VF610_NFC_DT
331 bool "Support Vybrid's vf610 NAND controller as a DT device"
332 depends on OF_CONTROL && DM_MTD
334 Enable the driver for Vybrid's vf610 NAND flash on platforms
338 prompt "Hardware ECC strength"
339 depends on NAND_VF610_NFC
340 default SYS_NAND_VF610_NFC_45_ECC_BYTES
342 Select the ECC strength used in the hardware BCH ECC block.
344 config SYS_NAND_VF610_NFC_45_ECC_BYTES
345 bool "24-error correction (45 ECC bytes)"
347 config SYS_NAND_VF610_NFC_60_ECC_BYTES
348 bool "32-error correction (60 ECC bytes)"
355 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
356 select SYS_NAND_SELF_INIT
362 This enables the driver for the NAND flash device found on
363 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
366 bool "Support for NAND on Allwinner SoCs"
368 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
369 select SYS_NAND_SELF_INIT
370 select SYS_NAND_U_BOOT_LOCATIONS
371 select SPL_NAND_SUPPORT
372 select SPL_SYS_NAND_SELF_INIT
375 Enable support for NAND. This option enables the standard and
377 The SPL driver only supports reading from the NAND using DMA
382 config NAND_SUNXI_SPL_ECC_STRENGTH
383 int "Allwinner NAND SPL ECC Strength"
386 config NAND_SUNXI_SPL_ECC_SIZE
387 int "Allwinner NAND SPL ECC Step Size"
390 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
391 int "Allwinner NAND SPL Usable Page Size"
397 bool "Configure Arasan Nand"
398 select SYS_NAND_SELF_INIT
402 This enables Nand driver support for Arasan nand flash
403 controller. This uses the hardware ECC for read and
407 bool "MXC NAND support"
408 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
411 This enables the NAND driver for the NAND flash controller on the
412 i.MX27 / i.MX31 / i.MX5 processors.
415 bool "MXS NAND support"
416 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
417 select SPL_SYS_NAND_SELF_INIT
418 select SYS_NAND_SELF_INIT
421 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
422 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
424 This enables NAND driver for the NAND flash controller on the
430 bool "Support MXS NAND controller as a DT device"
431 depends on OF_CONTROL && DM_MTD
433 Enable the driver for MXS NAND flash on platforms using
436 config NAND_MXS_USE_MINIMUM_ECC
437 bool "Use minimum ECC strength supported by the controller"
443 bool "Macronix raw NAND controller"
444 select SYS_NAND_SELF_INIT
446 This selects the Macronix raw NAND controller driver.
449 bool "Support for Zynq Nand controller"
450 select SPL_SYS_NAND_SELF_INIT
451 select SYS_NAND_SELF_INIT
455 This enables Nand driver support for Nand flash controller
458 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
459 bool "Enable use of 1st stage bootloader timing for NAND"
462 This flag prevent U-boot reconfigure NAND flash controller and reuse
463 the NAND timing from 1st stage bootloader.
466 bool "Support for OcteonTX NAND controller"
467 select SYS_NAND_SELF_INIT
470 This enables Nand flash controller hardware found on the OcteonTX
473 config NAND_OCTEONTX_HW_ECC
474 bool "Support Hardware ECC for OcteonTX NAND controller"
475 depends on NAND_OCTEONTX
478 This enables Hardware BCH engine found on the OcteonTX processors to
479 support ECC for NAND flash controller.
481 config NAND_STM32_FMC2
482 bool "Support for NAND controller on STM32MP SoCs"
483 depends on ARCH_STM32MP
484 select SYS_NAND_SELF_INIT
487 Enables support for NAND Flash chips on SoCs containing the FMC2
488 NAND controller. This controller is found on STM32MP SoCs.
489 The controller supports a maximum 8k page size and supports
490 a maximum 8-bit correction error per sector of 512 bytes.
493 bool "Support for NAND controller on Cortina-Access SoCs"
494 depends on CORTINA_PLATFORM
495 select SYS_NAND_SELF_INIT
499 Enables support for NAND Flash chips on Coartina-Access SoCs platform
500 This controller is found on Presidio/Venus SoCs.
501 The controller supports a maximum 8k page size and supports
502 a maximum 40-bit error correction per sector of 1024 bytes.
505 bool "Support for NAND controller on Rockchip SoCs"
506 depends on ARCH_ROCKCHIP
507 select SYS_NAND_SELF_INIT
511 Enables support for NAND Flash chips on Rockchip SoCs platform.
512 This controller is found on Rockchip SoCs.
513 There are four different versions of NAND FLASH Controllers,
515 NFC v600: RK2928, RK3066, RK3188
516 NFC v622: RK3036, RK3128
517 NFC v800: RK3308, RV1108
518 NFC v900: PX30, RK3326
521 bool "Support for NAND controller on Tegra SoCs"
522 depends on ARCH_TEGRA
523 select SYS_NAND_SELF_INIT
526 Enables support for NAND Flash chips on Tegra SoCs platforms.
528 comment "Generic NAND options"
530 config SYS_NAND_BLOCK_SIZE
531 hex "NAND chip eraseblock size"
532 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
533 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_FSL_IFC
535 Number of data bytes in one eraseblock for the NAND chip on the
536 board. This is the multiple of NAND_PAGE_SIZE and the number of
539 config SYS_NAND_ONFI_DETECTION
540 bool "Enable detection of ONFI compliant devices during probe"
542 Enables detection of ONFI compliant devices during probe.
543 And fetching device parameters flashed on device, by parsing
546 config SYS_NAND_PAGE_COUNT
547 hex "NAND chip page count"
548 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
549 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
551 Number of pages in the NAND chip.
553 config SYS_NAND_PAGE_SIZE
554 hex "NAND chip page size"
555 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
556 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
557 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
558 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
560 Number of data bytes in one page for the NAND chip on the
561 board, not including the OOB area.
563 config SYS_NAND_OOBSIZE
564 hex "NAND chip OOB size"
565 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
566 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
567 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
568 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
570 Number of bytes in the Out-Of-Band area for the NAND chip on
573 # Enhance depends when converting drivers to Kconfig which use this config
574 # option (mxc_nand, ndfc, omap_gpmc).
575 config SYS_NAND_BUSWIDTH_16BIT
576 bool "Use 16-bit NAND interface"
577 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
579 Indicates that NAND device has 16-bit wide data-bus. In absence of this
580 config, bus-width of NAND device is assumed to be either 8-bit and later
581 determined by reading ONFI params.
582 Above config is useful when NAND device's bus-width information cannot
583 be determined from on-chip ONFI params, like in following scenarios:
584 - SPL boot does not support reading of ONFI parameters. This is done to
585 keep SPL code foot-print small.
586 - In current U-Boot flow using nand_init(), driver initialization
587 happens in board_nand_init() which is called before any device probe
588 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
589 not available while configuring controller. So a static CONFIG_NAND_xx
590 is needed to know the device's bus-width in advance.
594 config SYS_NAND_5_ADDR_CYCLE
595 bool "Wait 5 address cycles during NAND commands"
596 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
597 (SPL_NAND_SUPPORT && NAND_ATMEL)
600 Some controllers require waiting for 5 address cycles when issuing
601 some commands, on NAND chips larger than 128MiB.
604 prompt "NAND bad block marker/indicator position in the OOB"
605 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
606 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
607 default HAS_NAND_LARGE_BADBLOCK_POS
609 In the OOB, which position contains the badblock information.
611 config HAS_NAND_LARGE_BADBLOCK_POS
612 bool "Set the bad block marker/indicator to the 'large' position"
614 config HAS_NAND_SMALL_BADBLOCK_POS
615 bool "Set the bad block marker/indicator to the 'small' position"
619 config SYS_NAND_BAD_BLOCK_POS
621 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
622 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
624 config SYS_NAND_U_BOOT_LOCATIONS
625 bool "Define U-boot binaries locations in NAND"
627 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
628 This option should not be enabled when compiling U-boot for boards
629 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
632 config SYS_NAND_U_BOOT_OFFS
633 hex "Location in NAND to read U-Boot from"
634 default 0x800000 if NAND_SUNXI
635 depends on SYS_NAND_U_BOOT_LOCATIONS
637 Set the offset from the start of the nand where u-boot should be
640 config SYS_NAND_U_BOOT_OFFS_REDUND
641 hex "Location in NAND to read U-Boot from"
642 default SYS_NAND_U_BOOT_OFFS
643 depends on SYS_NAND_U_BOOT_LOCATIONS
645 Set the offset from the start of the nand where the redundant u-boot
646 should be loaded from.
648 config SPL_NAND_AM33XX_BCH
649 bool "Enables SPL-NAND driver which supports ELM based"
650 depends on NAND_OMAP_GPMC && !OMAP34XX
653 Hardware ECC correction. This is useful for platforms which have ELM
654 hardware engine and use NAND boot mode.
655 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
656 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
657 SPL-NAND driver with software ECC correction support.
659 config SPL_NAND_DENALI
660 bool "Support Denali NAND controller for SPL"
662 This is a small implementation of the Denali NAND controller
665 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
666 int "Number of bytes skipped in OOB area"
667 depends on SPL_NAND_DENALI
670 This option specifies the number of bytes to skip from the beginning
671 of OOB area before last ECC sector data starts. This is potentially
672 used to preserve the bad block marker in the OOB area.
674 config SPL_NAND_SIMPLE
675 bool "Use simple SPL NAND driver"
676 depends on !SPL_NAND_AM33XX_BCH
678 Support for NAND boot using simple NAND drivers that
679 expose the cmd_ctrl() interface.