2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SYS_NAND_DRIVER_ECC_LAYOUT
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
18 config SYS_NAND_USE_FLASH_BBT
19 bool "Enable BBT (Bad Block Table) support"
21 Enable the BBT (Bad Block Table) usage.
24 bool "Support Atmel NAND controller"
25 imply SYS_NAND_USE_FLASH_BBT
27 Enable this driver for NAND flash platforms using an Atmel NAND
32 config ATMEL_NAND_HWECC
33 bool "Atmel Hardware ECC"
35 config ATMEL_NAND_HW_PMECC
36 bool "Atmel Programmable Multibit ECC (PMECC)"
37 select ATMEL_NAND_HWECC
39 The Programmable Multibit ECC (PMECC) controller is a programmable
40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
43 int "PMECC Correctable ECC Bits"
44 depends on ATMEL_NAND_HW_PMECC
47 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
49 config PMECC_SECTOR_SIZE
50 int "PMECC Sector Size"
51 depends on ATMEL_NAND_HW_PMECC
54 Sector size, in bytes, can be 512 or 1024.
56 config SPL_GENERATE_ATMEL_PMECC_HEADER
57 bool "Atmel PMECC Header Generation"
58 select ATMEL_NAND_HWECC
59 select ATMEL_NAND_HW_PMECC
61 Generate Programmable Multibit ECC (PMECC) header for SPL image.
66 bool "Support Broadcom NAND controller"
67 depends on OF_CONTROL && DM && DM_MTD
69 Enable the driver for NAND flash on platforms using a Broadcom NAND
72 config NAND_BRCMNAND_6368
73 bool "Support Broadcom NAND controller on bcm6368"
74 depends on NAND_BRCMNAND && ARCH_BMIPS
76 Enable support for broadcom nand driver on bcm6368.
78 config NAND_BRCMNAND_68360
79 bool "Support Broadcom NAND controller on bcm68360"
80 depends on NAND_BRCMNAND && ARCH_BCM68360
82 Enable support for broadcom nand driver on bcm68360.
84 config NAND_BRCMNAND_6838
85 bool "Support Broadcom NAND controller on bcm6838"
86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
88 Enable support for broadcom nand driver on bcm6838.
90 config NAND_BRCMNAND_6858
91 bool "Support Broadcom NAND controller on bcm6858"
92 depends on NAND_BRCMNAND && ARCH_BCM6858
94 Enable support for broadcom nand driver on bcm6858.
96 config NAND_BRCMNAND_63158
97 bool "Support Broadcom NAND controller on bcm63158"
98 depends on NAND_BRCMNAND && ARCH_BCM63158
100 Enable support for broadcom nand driver on bcm63158.
103 bool "Support TI Davinci NAND controller"
105 Enable this driver for NAND flash controllers available in TI Davinci
106 and Keystone2 platforms
108 config KEYSTONE_RBL_NAND
109 depends on ARCH_KEYSTONE
114 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
118 select SYS_NAND_SELF_INIT
121 config NAND_DENALI_DT
122 bool "Support Denali NAND controller as a DT device"
124 depends on OF_CONTROL && DM_MTD
126 Enable the driver for NAND flash on platforms using a Denali NAND
127 controller as a DT device.
129 config NAND_LPC32XX_MLC
130 bool "Support LPC32XX_MLC controller"
132 Enable the LPC32XX MLC NAND controller.
134 config NAND_LPC32XX_SLC
135 bool "Support LPC32XX_SLC controller"
137 Enable the LPC32XX SLC NAND controller.
139 config NAND_OMAP_GPMC
140 bool "Support OMAP GPMC NAND controller"
141 depends on ARCH_OMAP2PLUS
143 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
144 GPMC controller is used for parallel NAND flash devices, and can
145 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
146 and BCH16 ECC algorithms.
148 config NAND_OMAP_GPMC_PREFETCH
149 bool "Enable GPMC Prefetch"
150 depends on NAND_OMAP_GPMC
153 On OMAP platforms that use the GPMC controller
154 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
155 uses the prefetch mode to speed up read operations.
158 bool "Enable ELM driver for OMAPxx and AMxx platforms."
159 depends on NAND_OMAP_GPMC && !OMAP34XX
161 ELM controller is used for ECC error detection (not ECC calculation)
162 of BCH4, BCH8 and BCH16 ECC algorithms.
163 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
164 thus such SoC platforms need to depend on software library for ECC error
165 detection. However ECC calculation on such plaforms would still be
166 done by GPMC controller.
168 config NAND_VF610_NFC
169 bool "Support for Freescale NFC for VF610"
170 select SYS_NAND_SELF_INIT
171 select SYS_NAND_DRIVER_ECC_LAYOUT
174 Enables support for NAND Flash Controller on some Freescale
175 processors like the VF610, MCF54418 or Kinetis K70.
176 The driver supports a maximum 2k page size. The driver
177 currently does not support hardware ECC.
181 config NAND_VF610_NFC_DT
182 bool "Support Vybrid's vf610 NAND controller as a DT device"
183 depends on OF_CONTROL && DM_MTD
185 Enable the driver for Vybrid's vf610 NAND flash on platforms
189 prompt "Hardware ECC strength"
190 depends on NAND_VF610_NFC
191 default SYS_NAND_VF610_NFC_45_ECC_BYTES
193 Select the ECC strength used in the hardware BCH ECC block.
195 config SYS_NAND_VF610_NFC_45_ECC_BYTES
196 bool "24-error correction (45 ECC bytes)"
198 config SYS_NAND_VF610_NFC_60_ECC_BYTES
199 bool "32-error correction (60 ECC bytes)"
206 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
207 select SYS_NAND_SELF_INIT
213 This enables the driver for the NAND flash device found on
214 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
217 bool "Support for NAND on Allwinner SoCs"
219 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
220 select SYS_NAND_SELF_INIT
221 select SYS_NAND_U_BOOT_LOCATIONS
222 select SPL_NAND_SUPPORT
225 Enable support for NAND. This option enables the standard and
227 The SPL driver only supports reading from the NAND using DMA
232 config NAND_SUNXI_SPL_ECC_STRENGTH
233 int "Allwinner NAND SPL ECC Strength"
236 config NAND_SUNXI_SPL_ECC_SIZE
237 int "Allwinner NAND SPL ECC Step Size"
240 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
241 int "Allwinner NAND SPL Usable Page Size"
247 bool "Configure Arasan Nand"
248 select SYS_NAND_SELF_INIT
252 This enables Nand driver support for Arasan nand flash
253 controller. This uses the hardware ECC for read and
257 bool "MXC NAND support"
258 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
261 This enables the NAND driver for the NAND flash controller on the
262 i.MX27 / i.MX31 / i.MX5 rocessors.
265 bool "MXS NAND support"
266 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
267 select SYS_NAND_SELF_INIT
270 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
271 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
273 This enables NAND driver for the NAND flash controller on the
279 bool "Support MXS NAND controller as a DT device"
280 depends on OF_CONTROL && DM_MTD
282 Enable the driver for MXS NAND flash on platforms using
285 config NAND_MXS_USE_MINIMUM_ECC
286 bool "Use minimum ECC strength supported by the controller"
292 bool "Support for Zynq Nand controller"
293 select SYS_NAND_SELF_INIT
297 This enables Nand driver support for Nand flash controller
300 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
301 bool "Enable use of 1st stage bootloader timing for NAND"
304 This flag prevent U-boot reconfigure NAND flash controller and reuse
305 the NAND timing from 1st stage bootloader.
308 bool "Support for OcteonTX NAND controller"
309 select SYS_NAND_SELF_INIT
312 This enables Nand flash controller hardware found on the OcteonTX
315 config NAND_OCTEONTX_HW_ECC
316 bool "Support Hardware ECC for OcteonTX NAND controller"
317 depends on NAND_OCTEONTX
320 This enables Hardware BCH engine found on the OcteonTX processors to
321 support ECC for NAND flash controller.
323 config NAND_STM32_FMC2
324 bool "Support for NAND controller on STM32MP SoCs"
325 depends on ARCH_STM32MP
326 select SYS_NAND_SELF_INIT
329 Enables support for NAND Flash chips on SoCs containing the FMC2
330 NAND controller. This controller is found on STM32MP SoCs.
331 The controller supports a maximum 8k page size and supports
332 a maximum 8-bit correction error per sector of 512 bytes.
335 bool "Support for NAND controller on Cortina-Access SoCs"
336 depends on CORTINA_PLATFORM
337 select SYS_NAND_SELF_INIT
341 Enables support for NAND Flash chips on Coartina-Access SoCs platform
342 This controller is found on Presidio/Venus SoCs.
343 The controller supports a maximum 8k page size and supports
344 a maximum 40-bit error correction per sector of 1024 bytes.
347 bool "Support for NAND controller on Rockchip SoCs"
348 depends on ARCH_ROCKCHIP
349 select SYS_NAND_SELF_INIT
353 Enables support for NAND Flash chips on Rockchip SoCs platform.
354 This controller is found on Rockchip SoCs.
355 There are four different versions of NAND FLASH Controllers,
357 NFC v600: RK2928, RK3066, RK3188
358 NFC v622: RK3036, RK3128
359 NFC v800: RK3308, RV1108
360 NFC v900: PX30, RK3326
362 comment "Generic NAND options"
364 config SYS_NAND_BLOCK_SIZE
365 hex "NAND chip eraseblock size"
366 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
367 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
369 Number of data bytes in one eraseblock for the NAND chip on the
370 board. This is the multiple of NAND_PAGE_SIZE and the number of
373 config SYS_NAND_PAGE_COUNT
374 hex "NAND chip page count"
375 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
376 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
378 Number of pages in the NAND chip.
380 config SYS_NAND_PAGE_SIZE
381 hex "NAND chip page size"
382 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
383 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
384 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
385 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
387 Number of data bytes in one page for the NAND chip on the
388 board, not including the OOB area.
390 config SYS_NAND_OOBSIZE
391 hex "NAND chip OOB size"
392 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
393 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
394 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
395 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
397 Number of bytes in the Out-Of-Band area for the NAND chip on
400 # Enhance depends when converting drivers to Kconfig which use this config
401 # option (mxc_nand, ndfc, omap_gpmc).
402 config SYS_NAND_BUSWIDTH_16BIT
403 bool "Use 16-bit NAND interface"
404 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
406 Indicates that NAND device has 16-bit wide data-bus. In absence of this
407 config, bus-width of NAND device is assumed to be either 8-bit and later
408 determined by reading ONFI params.
409 Above config is useful when NAND device's bus-width information cannot
410 be determined from on-chip ONFI params, like in following scenarios:
411 - SPL boot does not support reading of ONFI parameters. This is done to
412 keep SPL code foot-print small.
413 - In current U-Boot flow using nand_init(), driver initialization
414 happens in board_nand_init() which is called before any device probe
415 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
416 not available while configuring controller. So a static CONFIG_NAND_xx
417 is needed to know the device's bus-width in advance.
419 config SYS_NAND_MAX_CHIPS
422 depends on NAND_ARASAN
424 The maximum number of NAND chips per device to be supported.
428 config SYS_NAND_U_BOOT_LOCATIONS
429 bool "Define U-boot binaries locations in NAND"
431 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
432 This option should not be enabled when compiling U-boot for boards
433 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
436 config SYS_NAND_U_BOOT_OFFS
437 hex "Location in NAND to read U-Boot from"
438 default 0x800000 if NAND_SUNXI
439 depends on SYS_NAND_U_BOOT_LOCATIONS
441 Set the offset from the start of the nand where u-boot should be
444 config SYS_NAND_U_BOOT_OFFS_REDUND
445 hex "Location in NAND to read U-Boot from"
446 default SYS_NAND_U_BOOT_OFFS
447 depends on SYS_NAND_U_BOOT_LOCATIONS
449 Set the offset from the start of the nand where the redundant u-boot
450 should be loaded from.
452 config SPL_NAND_AM33XX_BCH
453 bool "Enables SPL-NAND driver which supports ELM based"
454 depends on NAND_OMAP_GPMC && !OMAP34XX
457 Hardware ECC correction. This is useful for platforms which have ELM
458 hardware engine and use NAND boot mode.
459 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
460 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
461 SPL-NAND driver with software ECC correction support.
463 config SPL_NAND_DENALI
464 bool "Support Denali NAND controller for SPL"
466 This is a small implementation of the Denali NAND controller
469 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
470 int "Number of bytes skipped in OOB area"
471 depends on SPL_NAND_DENALI
474 This option specifies the number of bytes to skip from the beginning
475 of OOB area before last ECC sector data starts. This is potentially
476 used to preserve the bad block marker in the OOB area.
478 config SPL_NAND_SIMPLE
479 bool "Use simple SPL NAND driver"
480 depends on !SPL_NAND_AM33XX_BCH
482 Support for NAND boot using simple NAND drivers that
483 expose the cmd_ctrl() interface.