3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
13 bool "Support Atmel NAND controller"
14 imply SYS_NAND_USE_FLASH_BBT
16 Enable this driver for NAND flash platforms using an Atmel NAND
20 bool "Support TI Davinci NAND controller"
22 Enable this driver for NAND flash controllers available in TI Davinci
23 and Keystone2 platforms
27 select SYS_NAND_SELF_INIT
31 bool "Support Denali NAND controller as a DT device"
33 depends on OF_CONTROL && DM
35 Enable the driver for NAND flash on platforms using a Denali NAND
36 controller as a DT device.
38 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
39 int "Number of bytes skipped in OOB area"
40 depends on NAND_DENALI
43 This option specifies the number of bytes to skip from the beginning
44 of OOB area before last ECC sector data starts. This is potentially
45 used to preserve the bad block marker in the OOB area.
47 config NAND_LPC32XX_SLC
48 bool "Support LPC32XX_SLC controller"
50 Enable the LPC32XX SLC NAND controller.
53 bool "Support OMAP GPMC NAND controller"
54 depends on ARCH_OMAP2PLUS
56 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
57 GPMC controller is used for parallel NAND flash devices, and can
58 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
59 and BCH16 ECC algorithms.
61 config NAND_OMAP_GPMC_PREFETCH
62 bool "Enable GPMC Prefetch"
63 depends on NAND_OMAP_GPMC
66 On OMAP platforms that use the GPMC controller
67 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
68 uses the prefetch mode to speed up read operations.
71 bool "Enable ELM driver for OMAPxx and AMxx platforms."
72 depends on NAND_OMAP_GPMC && !OMAP34XX
74 ELM controller is used for ECC error detection (not ECC calculation)
75 of BCH4, BCH8 and BCH16 ECC algorithms.
76 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
77 thus such SoC platforms need to depend on software library for ECC error
78 detection. However ECC calculation on such plaforms would still be
79 done by GPMC controller.
82 bool "Support for Freescale NFC for VF610"
83 select SYS_NAND_SELF_INIT
86 Enables support for NAND Flash Controller on some Freescale
87 processors like the VF610, MCF54418 or Kinetis K70.
88 The driver supports a maximum 2k page size. The driver
89 currently does not support hardware ECC.
93 config NAND_VF610_NFC_DT
94 bool "Support Vybrid's vf610 NAND controller as a DT device"
95 depends on OF_CONTROL && MTD
97 Enable the driver for Vybrid's vf610 NAND flash on platforms
101 prompt "Hardware ECC strength"
102 depends on NAND_VF610_NFC
103 default SYS_NAND_VF610_NFC_45_ECC_BYTES
105 Select the ECC strength used in the hardware BCH ECC block.
107 config SYS_NAND_VF610_NFC_45_ECC_BYTES
108 bool "24-error correction (45 ECC bytes)"
110 config SYS_NAND_VF610_NFC_60_ECC_BYTES
111 bool "32-error correction (60 ECC bytes)"
118 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
119 select SYS_NAND_SELF_INIT
122 This enables the driver for the NAND flash device found on
123 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
126 bool "Support for NAND on Allwinner SoCs"
128 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
129 select SYS_NAND_SELF_INIT
130 select SYS_NAND_U_BOOT_LOCATIONS
131 select SPL_NAND_SUPPORT
134 Enable support for NAND. This option enables the standard and
136 The SPL driver only supports reading from the NAND using DMA
141 config NAND_SUNXI_SPL_ECC_STRENGTH
142 int "Allwinner NAND SPL ECC Strength"
145 config NAND_SUNXI_SPL_ECC_SIZE
146 int "Allwinner NAND SPL ECC Step Size"
149 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
150 int "Allwinner NAND SPL Usable Page Size"
156 bool "Configure Arasan Nand"
157 select SYS_NAND_SELF_INIT
160 This enables Nand driver support for Arasan nand flash
161 controller. This uses the hardware ECC for read and
165 bool "MXC NAND support"
166 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
169 This enables the NAND driver for the NAND flash controller on the
170 i.MX27 / i.MX31 / i.MX5 rocessors.
173 bool "MXS NAND support"
174 depends on MX23 || MX28 || MX6 || MX7
175 select SYS_NAND_SELF_INIT
178 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
179 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
181 This enables NAND driver for the NAND flash controller on the
187 bool "Support MXS NAND controller as a DT device"
188 depends on OF_CONTROL && MTD
190 Enable the driver for MXS NAND flash on platforms using
193 config NAND_MXS_USE_MINIMUM_ECC
194 bool "Use minimum ECC strength supported by the controller"
200 bool "Support for Zynq Nand controller"
201 select SYS_NAND_SELF_INIT
204 This enables Nand driver support for Nand flash controller
207 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
208 bool "Enable use of 1st stage bootloader timing for NAND"
211 This flag prevent U-boot reconfigure NAND flash controller and reuse
212 the NAND timing from 1st stage bootloader.
214 comment "Generic NAND options"
216 config SYS_NAND_BLOCK_SIZE
217 hex "NAND chip eraseblock size"
218 depends on ARCH_SUNXI
220 Number of data bytes in one eraseblock for the NAND chip on the
221 board. This is the multiple of NAND_PAGE_SIZE and the number of
224 config SYS_NAND_PAGE_SIZE
225 hex "NAND chip page size"
226 depends on ARCH_SUNXI
228 Number of data bytes in one page for the NAND chip on the
229 board, not including the OOB area.
231 config SYS_NAND_OOBSIZE
232 hex "NAND chip OOB size"
233 depends on ARCH_SUNXI
235 Number of bytes in the Out-Of-Band area for the NAND chip on
238 # Enhance depends when converting drivers to Kconfig which use this config
239 # option (mxc_nand, ndfc, omap_gpmc).
240 config SYS_NAND_BUSWIDTH_16BIT
241 bool "Use 16-bit NAND interface"
242 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
244 Indicates that NAND device has 16-bit wide data-bus. In absence of this
245 config, bus-width of NAND device is assumed to be either 8-bit and later
246 determined by reading ONFI params.
247 Above config is useful when NAND device's bus-width information cannot
248 be determined from on-chip ONFI params, like in following scenarios:
249 - SPL boot does not support reading of ONFI parameters. This is done to
250 keep SPL code foot-print small.
251 - In current U-Boot flow using nand_init(), driver initialization
252 happens in board_nand_init() which is called before any device probe
253 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
254 not available while configuring controller. So a static CONFIG_NAND_xx
255 is needed to know the device's bus-width in advance.
259 config SYS_NAND_U_BOOT_LOCATIONS
260 bool "Define U-boot binaries locations in NAND"
262 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
263 This option should not be enabled when compiling U-boot for boards
264 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
267 config SYS_NAND_U_BOOT_OFFS
268 hex "Location in NAND to read U-Boot from"
269 default 0x800000 if NAND_SUNXI
270 depends on SYS_NAND_U_BOOT_LOCATIONS
272 Set the offset from the start of the nand where u-boot should be
275 config SYS_NAND_U_BOOT_OFFS_REDUND
276 hex "Location in NAND to read U-Boot from"
277 default SYS_NAND_U_BOOT_OFFS
278 depends on SYS_NAND_U_BOOT_LOCATIONS
280 Set the offset from the start of the nand where the redundant u-boot
281 should be loaded from.
283 config SPL_NAND_AM33XX_BCH
284 bool "Enables SPL-NAND driver which supports ELM based"
285 depends on NAND_OMAP_GPMC && !OMAP34XX
288 Hardware ECC correction. This is useful for platforms which have ELM
289 hardware engine and use NAND boot mode.
290 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
291 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
292 SPL-NAND driver with software ECC correction support.
294 config SPL_NAND_DENALI
295 bool "Support Denali NAND controller for SPL"
297 This is a small implementation of the Denali NAND controller
300 config SPL_NAND_SIMPLE
301 bool "Use simple SPL NAND driver"
302 depends on !SPL_NAND_AM33XX_BCH
304 Support for NAND boot using simple NAND drivers that
305 expose the cmd_ctrl() interface.