2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SYS_NAND_DRIVER_ECC_LAYOUT
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
18 config SYS_NAND_USE_FLASH_BBT
19 bool "Enable BBT (Bad Block Table) support"
21 Enable the BBT (Bad Block Table) usage.
24 bool "Support Atmel NAND controller"
25 imply SYS_NAND_USE_FLASH_BBT
27 Enable this driver for NAND flash platforms using an Atmel NAND
32 config ATMEL_NAND_HWECC
33 bool "Atmel Hardware ECC"
35 config ATMEL_NAND_HW_PMECC
36 bool "Atmel Programmable Multibit ECC (PMECC)"
37 select ATMEL_NAND_HWECC
39 The Programmable Multibit ECC (PMECC) controller is a programmable
40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
43 int "PMECC Correctable ECC Bits"
44 depends on ATMEL_NAND_HW_PMECC
47 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
49 config PMECC_SECTOR_SIZE
50 int "PMECC Sector Size"
51 depends on ATMEL_NAND_HW_PMECC
54 Sector size, in bytes, can be 512 or 1024.
56 config SPL_GENERATE_ATMEL_PMECC_HEADER
57 bool "Atmel PMECC Header Generation"
58 select ATMEL_NAND_HWECC
59 select ATMEL_NAND_HW_PMECC
61 Generate Programmable Multibit ECC (PMECC) header for SPL image.
66 bool "Support Broadcom NAND controller"
67 depends on OF_CONTROL && DM && DM_MTD
69 Enable the driver for NAND flash on platforms using a Broadcom NAND
72 config NAND_BRCMNAND_6368
73 bool "Support Broadcom NAND controller on bcm6368"
74 depends on NAND_BRCMNAND && ARCH_BMIPS
76 Enable support for broadcom nand driver on bcm6368.
78 config NAND_BRCMNAND_68360
79 bool "Support Broadcom NAND controller on bcm68360"
80 depends on NAND_BRCMNAND && ARCH_BCM68360
82 Enable support for broadcom nand driver on bcm68360.
84 config NAND_BRCMNAND_6838
85 bool "Support Broadcom NAND controller on bcm6838"
86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
88 Enable support for broadcom nand driver on bcm6838.
90 config NAND_BRCMNAND_6858
91 bool "Support Broadcom NAND controller on bcm6858"
92 depends on NAND_BRCMNAND && ARCH_BCM6858
94 Enable support for broadcom nand driver on bcm6858.
96 config NAND_BRCMNAND_63158
97 bool "Support Broadcom NAND controller on bcm63158"
98 depends on NAND_BRCMNAND && ARCH_BCM63158
100 Enable support for broadcom nand driver on bcm63158.
103 bool "Support TI Davinci NAND controller"
105 Enable this driver for NAND flash controllers available in TI Davinci
106 and Keystone2 platforms
108 config KEYSTONE_RBL_NAND
109 depends on ARCH_KEYSTONE
114 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
118 select SYS_NAND_SELF_INIT
121 config NAND_DENALI_DT
122 bool "Support Denali NAND controller as a DT device"
124 depends on OF_CONTROL && DM_MTD
126 Enable the driver for NAND flash on platforms using a Denali NAND
127 controller as a DT device.
130 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
133 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
136 bool "Support Freescale Integrated Flash Controller NAND driver"
138 Enable the Freescale Integrated Flash Controller NAND driver.
140 config NAND_LPC32XX_MLC
141 bool "Support LPC32XX_MLC controller"
143 Enable the LPC32XX MLC NAND controller.
145 config NAND_LPC32XX_SLC
146 bool "Support LPC32XX_SLC controller"
148 Enable the LPC32XX SLC NAND controller.
150 config NAND_OMAP_GPMC
151 bool "Support OMAP GPMC NAND controller"
152 depends on ARCH_OMAP2PLUS
154 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
155 GPMC controller is used for parallel NAND flash devices, and can
156 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
157 and BCH16 ECC algorithms.
159 config NAND_OMAP_GPMC_PREFETCH
160 bool "Enable GPMC Prefetch"
161 depends on NAND_OMAP_GPMC
164 On OMAP platforms that use the GPMC controller
165 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
166 uses the prefetch mode to speed up read operations.
169 bool "Enable ELM driver for OMAPxx and AMxx platforms."
170 depends on NAND_OMAP_GPMC && !OMAP34XX
172 ELM controller is used for ECC error detection (not ECC calculation)
173 of BCH4, BCH8 and BCH16 ECC algorithms.
174 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
175 thus such SoC platforms need to depend on software library for ECC error
176 detection. However ECC calculation on such plaforms would still be
177 done by GPMC controller.
179 config NAND_VF610_NFC
180 bool "Support for Freescale NFC for VF610"
181 select SYS_NAND_SELF_INIT
182 select SYS_NAND_DRIVER_ECC_LAYOUT
185 Enables support for NAND Flash Controller on some Freescale
186 processors like the VF610, MCF54418 or Kinetis K70.
187 The driver supports a maximum 2k page size. The driver
188 currently does not support hardware ECC.
192 config NAND_VF610_NFC_DT
193 bool "Support Vybrid's vf610 NAND controller as a DT device"
194 depends on OF_CONTROL && DM_MTD
196 Enable the driver for Vybrid's vf610 NAND flash on platforms
200 prompt "Hardware ECC strength"
201 depends on NAND_VF610_NFC
202 default SYS_NAND_VF610_NFC_45_ECC_BYTES
204 Select the ECC strength used in the hardware BCH ECC block.
206 config SYS_NAND_VF610_NFC_45_ECC_BYTES
207 bool "24-error correction (45 ECC bytes)"
209 config SYS_NAND_VF610_NFC_60_ECC_BYTES
210 bool "32-error correction (60 ECC bytes)"
217 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
218 select SYS_NAND_SELF_INIT
224 This enables the driver for the NAND flash device found on
225 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
228 bool "Support for NAND on Allwinner SoCs"
230 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
231 select SYS_NAND_SELF_INIT
232 select SYS_NAND_U_BOOT_LOCATIONS
233 select SPL_NAND_SUPPORT
236 Enable support for NAND. This option enables the standard and
238 The SPL driver only supports reading from the NAND using DMA
243 config NAND_SUNXI_SPL_ECC_STRENGTH
244 int "Allwinner NAND SPL ECC Strength"
247 config NAND_SUNXI_SPL_ECC_SIZE
248 int "Allwinner NAND SPL ECC Step Size"
251 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
252 int "Allwinner NAND SPL Usable Page Size"
258 bool "Configure Arasan Nand"
259 select SYS_NAND_SELF_INIT
263 This enables Nand driver support for Arasan nand flash
264 controller. This uses the hardware ECC for read and
268 bool "MXC NAND support"
269 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
272 This enables the NAND driver for the NAND flash controller on the
273 i.MX27 / i.MX31 / i.MX5 rocessors.
276 bool "MXS NAND support"
277 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
278 select SYS_NAND_SELF_INIT
281 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
282 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
284 This enables NAND driver for the NAND flash controller on the
290 bool "Support MXS NAND controller as a DT device"
291 depends on OF_CONTROL && DM_MTD
293 Enable the driver for MXS NAND flash on platforms using
296 config NAND_MXS_USE_MINIMUM_ECC
297 bool "Use minimum ECC strength supported by the controller"
303 bool "Support for Zynq Nand controller"
304 select SYS_NAND_SELF_INIT
308 This enables Nand driver support for Nand flash controller
311 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
312 bool "Enable use of 1st stage bootloader timing for NAND"
315 This flag prevent U-boot reconfigure NAND flash controller and reuse
316 the NAND timing from 1st stage bootloader.
319 bool "Support for OcteonTX NAND controller"
320 select SYS_NAND_SELF_INIT
323 This enables Nand flash controller hardware found on the OcteonTX
326 config NAND_OCTEONTX_HW_ECC
327 bool "Support Hardware ECC for OcteonTX NAND controller"
328 depends on NAND_OCTEONTX
331 This enables Hardware BCH engine found on the OcteonTX processors to
332 support ECC for NAND flash controller.
334 config NAND_STM32_FMC2
335 bool "Support for NAND controller on STM32MP SoCs"
336 depends on ARCH_STM32MP
337 select SYS_NAND_SELF_INIT
340 Enables support for NAND Flash chips on SoCs containing the FMC2
341 NAND controller. This controller is found on STM32MP SoCs.
342 The controller supports a maximum 8k page size and supports
343 a maximum 8-bit correction error per sector of 512 bytes.
346 bool "Support for NAND controller on Cortina-Access SoCs"
347 depends on CORTINA_PLATFORM
348 select SYS_NAND_SELF_INIT
352 Enables support for NAND Flash chips on Coartina-Access SoCs platform
353 This controller is found on Presidio/Venus SoCs.
354 The controller supports a maximum 8k page size and supports
355 a maximum 40-bit error correction per sector of 1024 bytes.
358 bool "Support for NAND controller on Rockchip SoCs"
359 depends on ARCH_ROCKCHIP
360 select SYS_NAND_SELF_INIT
364 Enables support for NAND Flash chips on Rockchip SoCs platform.
365 This controller is found on Rockchip SoCs.
366 There are four different versions of NAND FLASH Controllers,
368 NFC v600: RK2928, RK3066, RK3188
369 NFC v622: RK3036, RK3128
370 NFC v800: RK3308, RV1108
371 NFC v900: PX30, RK3326
373 comment "Generic NAND options"
375 config SYS_NAND_BLOCK_SIZE
376 hex "NAND chip eraseblock size"
377 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
378 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
380 Number of data bytes in one eraseblock for the NAND chip on the
381 board. This is the multiple of NAND_PAGE_SIZE and the number of
384 config SYS_NAND_ONFI_DETECTION
385 bool "Enable detection of ONFI compliant devices during probe"
387 Enables detection of ONFI compliant devices during probe.
388 And fetching device parameters flashed on device, by parsing
391 config SYS_NAND_PAGE_COUNT
392 hex "NAND chip page count"
393 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
394 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
396 Number of pages in the NAND chip.
398 config SYS_NAND_PAGE_SIZE
399 hex "NAND chip page size"
400 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
401 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
402 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
403 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
405 Number of data bytes in one page for the NAND chip on the
406 board, not including the OOB area.
408 config SYS_NAND_OOBSIZE
409 hex "NAND chip OOB size"
410 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
411 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
412 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
413 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
415 Number of bytes in the Out-Of-Band area for the NAND chip on
418 # Enhance depends when converting drivers to Kconfig which use this config
419 # option (mxc_nand, ndfc, omap_gpmc).
420 config SYS_NAND_BUSWIDTH_16BIT
421 bool "Use 16-bit NAND interface"
422 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
424 Indicates that NAND device has 16-bit wide data-bus. In absence of this
425 config, bus-width of NAND device is assumed to be either 8-bit and later
426 determined by reading ONFI params.
427 Above config is useful when NAND device's bus-width information cannot
428 be determined from on-chip ONFI params, like in following scenarios:
429 - SPL boot does not support reading of ONFI parameters. This is done to
430 keep SPL code foot-print small.
431 - In current U-Boot flow using nand_init(), driver initialization
432 happens in board_nand_init() which is called before any device probe
433 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
434 not available while configuring controller. So a static CONFIG_NAND_xx
435 is needed to know the device's bus-width in advance.
439 config SYS_NAND_5_ADDR_CYCLE
440 bool "Wait 5 address cycles during NAND commands"
441 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
442 (SPL_NAND_SUPPORT && NAND_ATMEL)
445 Some controllers require waiting for 5 address cycles when issuing
446 some commands, on NAND chips larger than 128MiB.
449 prompt "NAND bad block marker/indicator position in the OOB"
450 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
451 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
452 default HAS_NAND_LARGE_BADBLOCK_POS
454 In the OOB, which position contains the badblock information.
456 config HAS_NAND_LARGE_BADBLOCK_POS
457 bool "Set the bad block marker/indicator to the 'large' position"
459 config HAS_NAND_SMALL_BADBLOCK_POS
460 bool "Set the bad block marker/indicator to the 'small' position"
464 config SYS_NAND_BAD_BLOCK_POS
466 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
467 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
469 config SYS_NAND_U_BOOT_LOCATIONS
470 bool "Define U-boot binaries locations in NAND"
472 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
473 This option should not be enabled when compiling U-boot for boards
474 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
477 config SYS_NAND_U_BOOT_OFFS
478 hex "Location in NAND to read U-Boot from"
479 default 0x800000 if NAND_SUNXI
480 depends on SYS_NAND_U_BOOT_LOCATIONS
482 Set the offset from the start of the nand where u-boot should be
485 config SYS_NAND_U_BOOT_OFFS_REDUND
486 hex "Location in NAND to read U-Boot from"
487 default SYS_NAND_U_BOOT_OFFS
488 depends on SYS_NAND_U_BOOT_LOCATIONS
490 Set the offset from the start of the nand where the redundant u-boot
491 should be loaded from.
493 config SPL_NAND_AM33XX_BCH
494 bool "Enables SPL-NAND driver which supports ELM based"
495 depends on NAND_OMAP_GPMC && !OMAP34XX
498 Hardware ECC correction. This is useful for platforms which have ELM
499 hardware engine and use NAND boot mode.
500 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
501 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
502 SPL-NAND driver with software ECC correction support.
504 config SPL_NAND_DENALI
505 bool "Support Denali NAND controller for SPL"
507 This is a small implementation of the Denali NAND controller
510 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
511 int "Number of bytes skipped in OOB area"
512 depends on SPL_NAND_DENALI
515 This option specifies the number of bytes to skip from the beginning
516 of OOB area before last ECC sector data starts. This is potentially
517 used to preserve the bad block marker in the OOB area.
519 config SPL_NAND_SIMPLE
520 bool "Use simple SPL NAND driver"
521 depends on !SPL_NAND_AM33XX_BCH
523 Support for NAND boot using simple NAND drivers that
524 expose the cmd_ctrl() interface.